Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Macros
defBF547.h File Reference
#include "defBF54x_base.h"

Go to the source code of this file.

Macros

#define TIMER8_CONFIG   0xffc00600 /* Timer 8 Configuration Register */
 
#define TIMER8_COUNTER   0xffc00604 /* Timer 8 Counter Register */
 
#define TIMER8_PERIOD   0xffc00608 /* Timer 8 Period Register */
 
#define TIMER8_WIDTH   0xffc0060c /* Timer 8 Width Register */
 
#define TIMER9_CONFIG   0xffc00610 /* Timer 9 Configuration Register */
 
#define TIMER9_COUNTER   0xffc00614 /* Timer 9 Counter Register */
 
#define TIMER9_PERIOD   0xffc00618 /* Timer 9 Period Register */
 
#define TIMER9_WIDTH   0xffc0061c /* Timer 9 Width Register */
 
#define TIMER10_CONFIG   0xffc00620 /* Timer 10 Configuration Register */
 
#define TIMER10_COUNTER   0xffc00624 /* Timer 10 Counter Register */
 
#define TIMER10_PERIOD   0xffc00628 /* Timer 10 Period Register */
 
#define TIMER10_WIDTH   0xffc0062c /* Timer 10 Width Register */
 
#define TIMER_ENABLE1   0xffc00640 /* Timer Group of 3 Enable Register */
 
#define TIMER_DISABLE1   0xffc00644 /* Timer Group of 3 Disable Register */
 
#define TIMER_STATUS1   0xffc00648 /* Timer Group of 3 Status Register */
 
#define SPORT0_TCR1   0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
 
#define SPORT0_TCR2   0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
 
#define SPORT0_TCLKDIV   0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
 
#define SPORT0_TFSDIV   0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
 
#define SPORT0_TX   0xffc00810 /* SPORT0 Transmit Data Register */
 
#define SPORT0_RX   0xffc00818 /* SPORT0 Receive Data Register */
 
#define SPORT0_RCR1   0xffc00820 /* SPORT0 Receive Configuration 1 Register */
 
#define SPORT0_RCR2   0xffc00824 /* SPORT0 Receive Configuration 2 Register */
 
#define SPORT0_RCLKDIV   0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
 
#define SPORT0_RFSDIV   0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
 
#define SPORT0_STAT   0xffc00830 /* SPORT0 Status Register */
 
#define SPORT0_CHNL   0xffc00834 /* SPORT0 Current Channel Register */
 
#define SPORT0_MCMC1   0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
 
#define SPORT0_MCMC2   0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
 
#define SPORT0_MTCS0   0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
 
#define SPORT0_MTCS1   0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
 
#define SPORT0_MTCS2   0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
 
#define SPORT0_MTCS3   0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
 
#define SPORT0_MRCS0   0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
 
#define SPORT0_MRCS1   0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
 
#define SPORT0_MRCS2   0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
 
#define SPORT0_MRCS3   0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
 
#define EPPI0_STATUS   0xffc01000 /* EPPI0 Status Register */
 
#define EPPI0_HCOUNT   0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
 
#define EPPI0_HDELAY   0xffc01008 /* EPPI0 Horizontal Delay Count Register */
 
#define EPPI0_VCOUNT   0xffc0100c /* EPPI0 Vertical Transfer Count Register */
 
#define EPPI0_VDELAY   0xffc01010 /* EPPI0 Vertical Delay Count Register */
 
#define EPPI0_FRAME   0xffc01014 /* EPPI0 Lines per Frame Register */
 
#define EPPI0_LINE   0xffc01018 /* EPPI0 Samples per Line Register */
 
#define EPPI0_CLKDIV   0xffc0101c /* EPPI0 Clock Divide Register */
 
#define EPPI0_CONTROL   0xffc01020 /* EPPI0 Control Register */
 
#define EPPI0_FS1W_HBL   0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
 
#define EPPI0_FS1P_AVPL   0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
 
#define EPPI0_FS2W_LVB   0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
 
#define EPPI0_FS2P_LAVF   0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
 
#define EPPI0_CLIP   0xffc01034 /* EPPI0 Clipping Register */
 
#define UART2_DLL   0xffc02100 /* Divisor Latch Low Byte */
 
#define UART2_DLH   0xffc02104 /* Divisor Latch High Byte */
 
#define UART2_GCTL   0xffc02108 /* Global Control Register */
 
#define UART2_LCR   0xffc0210c /* Line Control Register */
 
#define UART2_MCR   0xffc02110 /* Modem Control Register */
 
#define UART2_LSR   0xffc02114 /* Line Status Register */
 
#define UART2_MSR   0xffc02118 /* Modem Status Register */
 
#define UART2_SCR   0xffc0211c /* Scratch Register */
 
#define UART2_IER_SET   0xffc02120 /* Interrupt Enable Register Set */
 
#define UART2_IER_CLEAR   0xffc02124 /* Interrupt Enable Register Clear */
 
#define UART2_RBR   0xffc0212c /* Receive Buffer Register */
 
#define TWI1_REGBASE   0xffc02200
 
#define TWI1_CLKDIV   0xffc02200 /* Clock Divider Register */
 
#define TWI1_CONTROL   0xffc02204 /* TWI Control Register */
 
#define TWI1_SLAVE_CTL   0xffc02208 /* TWI Slave Mode Control Register */
 
#define TWI1_SLAVE_STAT   0xffc0220c /* TWI Slave Mode Status Register */
 
#define TWI1_SLAVE_ADDR   0xffc02210 /* TWI Slave Mode Address Register */
 
#define TWI1_MASTER_CTL   0xffc02214 /* TWI Master Mode Control Register */
 
#define TWI1_MASTER_STAT   0xffc02218 /* TWI Master Mode Status Register */
 
#define TWI1_MASTER_ADDR   0xffc0221c /* TWI Master Mode Address Register */
 
#define TWI1_INT_STAT   0xffc02220 /* TWI Interrupt Status Register */
 
#define TWI1_INT_MASK   0xffc02224 /* TWI Interrupt Mask Register */
 
#define TWI1_FIFO_CTL   0xffc02228 /* TWI FIFO Control Register */
 
#define TWI1_FIFO_STAT   0xffc0222c /* TWI FIFO Status Register */
 
#define TWI1_XMT_DATA8   0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
 
#define TWI1_XMT_DATA16   0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
 
#define TWI1_RCV_DATA8   0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
 
#define TWI1_RCV_DATA16   0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
 
#define SPI2_REGBASE   0xffc02400
 
#define SPI2_CTL   0xffc02400 /* SPI2 Control Register */
 
#define SPI2_FLG   0xffc02404 /* SPI2 Flag Register */
 
#define SPI2_STAT   0xffc02408 /* SPI2 Status Register */
 
#define SPI2_TDBR   0xffc0240c /* SPI2 Transmit Data Buffer Register */
 
#define SPI2_RDBR   0xffc02410 /* SPI2 Receive Data Buffer Register */
 
#define SPI2_BAUD   0xffc02414 /* SPI2 Baud Rate Register */
 
#define SPI2_SHADOW   0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
 
#define ATAPI_CONTROL   0xffc03800 /* ATAPI Control Register */
 
#define ATAPI_STATUS   0xffc03804 /* ATAPI Status Register */
 
#define ATAPI_DEV_ADDR   0xffc03808 /* ATAPI Device Register Address */
 
#define ATAPI_DEV_TXBUF   0xffc0380c /* ATAPI Device Register Write Data */
 
#define ATAPI_DEV_RXBUF   0xffc03810 /* ATAPI Device Register Read Data */
 
#define ATAPI_INT_MASK   0xffc03814 /* ATAPI Interrupt Mask Register */
 
#define ATAPI_INT_STATUS   0xffc03818 /* ATAPI Interrupt Status Register */
 
#define ATAPI_XFER_LEN   0xffc0381c /* ATAPI Length of Transfer */
 
#define ATAPI_LINE_STATUS   0xffc03820 /* ATAPI Line Status */
 
#define ATAPI_SM_STATE   0xffc03824 /* ATAPI State Machine Status */
 
#define ATAPI_TERMINATE   0xffc03828 /* ATAPI Host Terminate */
 
#define ATAPI_PIO_TFRCNT   0xffc0382c /* ATAPI PIO mode transfer count */
 
#define ATAPI_DMA_TFRCNT   0xffc03830 /* ATAPI DMA mode transfer count */
 
#define ATAPI_UMAIN_TFRCNT   0xffc03834 /* ATAPI UDMAIN transfer count */
 
#define ATAPI_UDMAOUT_TFRCNT   0xffc03838 /* ATAPI UDMAOUT transfer count */
 
#define ATAPI_REG_TIM_0   0xffc03840 /* ATAPI Register Transfer Timing 0 */
 
#define ATAPI_PIO_TIM_0   0xffc03844 /* ATAPI PIO Timing 0 Register */
 
#define ATAPI_PIO_TIM_1   0xffc03848 /* ATAPI PIO Timing 1 Register */
 
#define ATAPI_MULTI_TIM_0   0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
 
#define ATAPI_MULTI_TIM_1   0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
 
#define ATAPI_MULTI_TIM_2   0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
 
#define ATAPI_ULTRA_TIM_0   0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
 
#define ATAPI_ULTRA_TIM_1   0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
 
#define ATAPI_ULTRA_TIM_2   0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
 
#define ATAPI_ULTRA_TIM_3   0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
 
#define SDH_PWR_CTL   0xffc03900 /* SDH Power Control */
 
#define SDH_CLK_CTL   0xffc03904 /* SDH Clock Control */
 
#define SDH_ARGUMENT   0xffc03908 /* SDH Argument */
 
#define SDH_COMMAND   0xffc0390c /* SDH Command */
 
#define SDH_RESP_CMD   0xffc03910 /* SDH Response Command */
 
#define SDH_RESPONSE0   0xffc03914 /* SDH Response0 */
 
#define SDH_RESPONSE1   0xffc03918 /* SDH Response1 */
 
#define SDH_RESPONSE2   0xffc0391c /* SDH Response2 */
 
#define SDH_RESPONSE3   0xffc03920 /* SDH Response3 */
 
#define SDH_DATA_TIMER   0xffc03924 /* SDH Data Timer */
 
#define SDH_DATA_LGTH   0xffc03928 /* SDH Data Length */
 
#define SDH_DATA_CTL   0xffc0392c /* SDH Data Control */
 
#define SDH_DATA_CNT   0xffc03930 /* SDH Data Counter */
 
#define SDH_STATUS   0xffc03934 /* SDH Status */
 
#define SDH_STATUS_CLR   0xffc03938 /* SDH Status Clear */
 
#define SDH_MASK0   0xffc0393c /* SDH Interrupt0 Mask */
 
#define SDH_MASK1   0xffc03940 /* SDH Interrupt1 Mask */
 
#define SDH_FIFO_CNT   0xffc03948 /* SDH FIFO Counter */
 
#define SDH_FIFO   0xffc03980 /* SDH Data FIFO */
 
#define SDH_E_STATUS   0xffc039c0 /* SDH Exception Status */
 
#define SDH_E_MASK   0xffc039c4 /* SDH Exception Mask */
 
#define SDH_CFG   0xffc039c8 /* SDH Configuration */
 
#define SDH_RD_WAIT_EN   0xffc039cc /* SDH Read Wait Enable */
 
#define SDH_PID0   0xffc039d0 /* SDH Peripheral Identification0 */
 
#define SDH_PID1   0xffc039d4 /* SDH Peripheral Identification1 */
 
#define SDH_PID2   0xffc039d8 /* SDH Peripheral Identification2 */
 
#define SDH_PID3   0xffc039dc /* SDH Peripheral Identification3 */
 
#define SDH_PID4   0xffc039e0 /* SDH Peripheral Identification4 */
 
#define SDH_PID5   0xffc039e4 /* SDH Peripheral Identification5 */
 
#define SDH_PID6   0xffc039e8 /* SDH Peripheral Identification6 */
 
#define SDH_PID7   0xffc039ec /* SDH Peripheral Identification7 */
 
#define HOST_CONTROL   0xffc03a00 /* HOST Control Register */
 
#define HOST_STATUS   0xffc03a04 /* HOST Status Register */
 
#define HOST_TIMEOUT   0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
 
#define USB_FADDR   0xffc03c00 /* Function address register */
 
#define USB_POWER   0xffc03c04 /* Power management register */
 
#define USB_INTRTX   0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 
#define USB_INTRRX   0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
 
#define USB_INTRTXE   0xffc03c10 /* Interrupt enable register for IntrTx */
 
#define USB_INTRRXE   0xffc03c14 /* Interrupt enable register for IntrRx */
 
#define USB_INTRUSB   0xffc03c18 /* Interrupt register for common USB interrupts */
 
#define USB_INTRUSBE   0xffc03c1c /* Interrupt enable register for IntrUSB */
 
#define USB_FRAME   0xffc03c20 /* USB frame number */
 
#define USB_INDEX   0xffc03c24 /* Index register for selecting the indexed endpoint registers */
 
#define USB_TESTMODE   0xffc03c28 /* Enabled USB 20 test modes */
 
#define USB_GLOBINTR   0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 
#define USB_GLOBAL_CTL   0xffc03c30 /* Global Clock Control for the core */
 
#define USB_TX_MAX_PACKET   0xffc03c40 /* Maximum packet size for Host Tx endpoint */
 
#define USB_CSR0   0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 
#define USB_TXCSR   0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 
#define USB_RX_MAX_PACKET   0xffc03c48 /* Maximum packet size for Host Rx endpoint */
 
#define USB_RXCSR   0xffc03c4c /* Control Status register for Host Rx endpoint */
 
#define USB_COUNT0   0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 
#define USB_RXCOUNT   0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 
#define USB_TXTYPE   0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 
#define USB_NAKLIMIT0   0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 
#define USB_TXINTERVAL   0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 
#define USB_RXTYPE   0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 
#define USB_RXINTERVAL   0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 
#define USB_TXCOUNT   0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
 
#define USB_EP0_FIFO   0xffc03c80 /* Endpoint 0 FIFO */
 
#define USB_EP1_FIFO   0xffc03c88 /* Endpoint 1 FIFO */
 
#define USB_EP2_FIFO   0xffc03c90 /* Endpoint 2 FIFO */
 
#define USB_EP3_FIFO   0xffc03c98 /* Endpoint 3 FIFO */
 
#define USB_EP4_FIFO   0xffc03ca0 /* Endpoint 4 FIFO */
 
#define USB_EP5_FIFO   0xffc03ca8 /* Endpoint 5 FIFO */
 
#define USB_EP6_FIFO   0xffc03cb0 /* Endpoint 6 FIFO */
 
#define USB_EP7_FIFO   0xffc03cb8 /* Endpoint 7 FIFO */
 
#define USB_OTG_DEV_CTL   0xffc03d00 /* OTG Device Control Register */
 
#define USB_OTG_VBUS_IRQ   0xffc03d04 /* OTG VBUS Control Interrupts */
 
#define USB_OTG_VBUS_MASK   0xffc03d08 /* VBUS Control Interrupt Enable */
 
#define USB_LINKINFO   0xffc03d48 /* Enables programming of some PHY-side delays */
 
#define USB_VPLEN   0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
 
#define USB_HS_EOF1   0xffc03d50 /* Time buffer for High-Speed transactions */
 
#define USB_FS_EOF1   0xffc03d54 /* Time buffer for Full-Speed transactions */
 
#define USB_LS_EOF1   0xffc03d58 /* Time buffer for Low-Speed transactions */
 
#define USB_APHY_CNTRL   0xffc03de0 /* Register that increases visibility of Analog PHY */
 
#define USB_APHY_CALIB   0xffc03de4 /* Register used to set some calibration values */
 
#define USB_APHY_CNTRL2   0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 
#define USB_PHY_TEST   0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
 
#define USB_PLLOSC_CTRL   0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
 
#define USB_SRP_CLKDIV   0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
 
#define USB_EP_NI0_TXMAXP   0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
 
#define USB_EP_NI0_TXCSR   0xffc03e04 /* Control Status register for endpoint 0 */
 
#define USB_EP_NI0_RXMAXP   0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
 
#define USB_EP_NI0_RXCSR   0xffc03e0c /* Control Status register for Host Rx endpoint0 */
 
#define USB_EP_NI0_RXCOUNT   0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
 
#define USB_EP_NI0_TXTYPE   0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 
#define USB_EP_NI0_TXINTERVAL   0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
 
#define USB_EP_NI0_RXTYPE   0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 
#define USB_EP_NI0_RXINTERVAL   0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 
#define USB_EP_NI0_TXCOUNT   0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
 
#define USB_EP_NI1_TXMAXP   0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
 
#define USB_EP_NI1_TXCSR   0xffc03e44 /* Control Status register for endpoint1 */
 
#define USB_EP_NI1_RXMAXP   0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
 
#define USB_EP_NI1_RXCSR   0xffc03e4c /* Control Status register for Host Rx endpoint1 */
 
#define USB_EP_NI1_RXCOUNT   0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
 
#define USB_EP_NI1_TXTYPE   0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 
#define USB_EP_NI1_TXINTERVAL   0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
 
#define USB_EP_NI1_RXTYPE   0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 
#define USB_EP_NI1_RXINTERVAL   0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 
#define USB_EP_NI1_TXCOUNT   0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 
#define USB_EP_NI2_TXMAXP   0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
 
#define USB_EP_NI2_TXCSR   0xffc03e84 /* Control Status register for endpoint2 */
 
#define USB_EP_NI2_RXMAXP   0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
 
#define USB_EP_NI2_RXCSR   0xffc03e8c /* Control Status register for Host Rx endpoint2 */
 
#define USB_EP_NI2_RXCOUNT   0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
 
#define USB_EP_NI2_TXTYPE   0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 
#define USB_EP_NI2_TXINTERVAL   0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
 
#define USB_EP_NI2_RXTYPE   0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 
#define USB_EP_NI2_RXINTERVAL   0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 
#define USB_EP_NI2_TXCOUNT   0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
 
#define USB_EP_NI3_TXMAXP   0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
 
#define USB_EP_NI3_TXCSR   0xffc03ec4 /* Control Status register for endpoint3 */
 
#define USB_EP_NI3_RXMAXP   0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
 
#define USB_EP_NI3_RXCSR   0xffc03ecc /* Control Status register for Host Rx endpoint3 */
 
#define USB_EP_NI3_RXCOUNT   0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
 
#define USB_EP_NI3_TXTYPE   0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 
#define USB_EP_NI3_TXINTERVAL   0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
 
#define USB_EP_NI3_RXTYPE   0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 
#define USB_EP_NI3_RXINTERVAL   0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 
#define USB_EP_NI3_TXCOUNT   0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 
#define USB_EP_NI4_TXMAXP   0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
 
#define USB_EP_NI4_TXCSR   0xffc03f04 /* Control Status register for endpoint4 */
 
#define USB_EP_NI4_RXMAXP   0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
 
#define USB_EP_NI4_RXCSR   0xffc03f0c /* Control Status register for Host Rx endpoint4 */
 
#define USB_EP_NI4_RXCOUNT   0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
 
#define USB_EP_NI4_TXTYPE   0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 
#define USB_EP_NI4_TXINTERVAL   0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
 
#define USB_EP_NI4_RXTYPE   0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 
#define USB_EP_NI4_RXINTERVAL   0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 
#define USB_EP_NI4_TXCOUNT   0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
 
#define USB_EP_NI5_TXMAXP   0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
 
#define USB_EP_NI5_TXCSR   0xffc03f44 /* Control Status register for endpoint5 */
 
#define USB_EP_NI5_RXMAXP   0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
 
#define USB_EP_NI5_RXCSR   0xffc03f4c /* Control Status register for Host Rx endpoint5 */
 
#define USB_EP_NI5_RXCOUNT   0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
 
#define USB_EP_NI5_TXTYPE   0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 
#define USB_EP_NI5_TXINTERVAL   0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
 
#define USB_EP_NI5_RXTYPE   0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 
#define USB_EP_NI5_RXINTERVAL   0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 
#define USB_EP_NI5_TXCOUNT   0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
 
#define USB_EP_NI6_TXMAXP   0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
 
#define USB_EP_NI6_TXCSR   0xffc03f84 /* Control Status register for endpoint6 */
 
#define USB_EP_NI6_RXMAXP   0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
 
#define USB_EP_NI6_RXCSR   0xffc03f8c /* Control Status register for Host Rx endpoint6 */
 
#define USB_EP_NI6_RXCOUNT   0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
 
#define USB_EP_NI6_TXTYPE   0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 
#define USB_EP_NI6_TXINTERVAL   0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
 
#define USB_EP_NI6_RXTYPE   0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 
#define USB_EP_NI6_RXINTERVAL   0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 
#define USB_EP_NI6_TXCOUNT   0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
 
#define USB_EP_NI7_TXMAXP   0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
 
#define USB_EP_NI7_TXCSR   0xffc03fc4 /* Control Status register for endpoint7 */
 
#define USB_EP_NI7_RXMAXP   0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
 
#define USB_EP_NI7_RXCSR   0xffc03fcc /* Control Status register for Host Rx endpoint7 */
 
#define USB_EP_NI7_RXCOUNT   0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
 
#define USB_EP_NI7_TXTYPE   0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 
#define USB_EP_NI7_TXINTERVAL   0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
 
#define USB_EP_NI7_RXTYPE   0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 
#define USB_EP_NI7_RXINTERVAL   0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 
#define USB_EP_NI7_TXCOUNT   0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
 
#define USB_DMA_INTERRUPT   0xffc04000 /* Indicates pending interrupts for the DMA channels */
 
#define USB_DMA0CONTROL   0xffc04004 /* DMA master channel 0 configuration */
 
#define USB_DMA0ADDRLOW   0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 
#define USB_DMA0ADDRHIGH   0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 
#define USB_DMA0COUNTLOW   0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 
#define USB_DMA0COUNTHIGH   0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 
#define USB_DMA1CONTROL   0xffc04024 /* DMA master channel 1 configuration */
 
#define USB_DMA1ADDRLOW   0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 
#define USB_DMA1ADDRHIGH   0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 
#define USB_DMA1COUNTLOW   0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 
#define USB_DMA1COUNTHIGH   0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 
#define USB_DMA2CONTROL   0xffc04044 /* DMA master channel 2 configuration */
 
#define USB_DMA2ADDRLOW   0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 
#define USB_DMA2ADDRHIGH   0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 
#define USB_DMA2COUNTLOW   0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 
#define USB_DMA2COUNTHIGH   0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 
#define USB_DMA3CONTROL   0xffc04064 /* DMA master channel 3 configuration */
 
#define USB_DMA3ADDRLOW   0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 
#define USB_DMA3ADDRHIGH   0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 
#define USB_DMA3COUNTLOW   0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 
#define USB_DMA3COUNTHIGH   0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 
#define USB_DMA4CONTROL   0xffc04084 /* DMA master channel 4 configuration */
 
#define USB_DMA4ADDRLOW   0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 
#define USB_DMA4ADDRHIGH   0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 
#define USB_DMA4COUNTLOW   0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 
#define USB_DMA4COUNTHIGH   0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 
#define USB_DMA5CONTROL   0xffc040a4 /* DMA master channel 5 configuration */
 
#define USB_DMA5ADDRLOW   0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 
#define USB_DMA5ADDRHIGH   0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 
#define USB_DMA5COUNTLOW   0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 
#define USB_DMA5COUNTHIGH   0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 
#define USB_DMA6CONTROL   0xffc040c4 /* DMA master channel 6 configuration */
 
#define USB_DMA6ADDRLOW   0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 
#define USB_DMA6ADDRHIGH   0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 
#define USB_DMA6COUNTLOW   0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 
#define USB_DMA6COUNTHIGH   0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 
#define USB_DMA7CONTROL   0xffc040e4 /* DMA master channel 7 configuration */
 
#define USB_DMA7ADDRLOW   0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 
#define USB_DMA7ADDRHIGH   0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 
#define USB_DMA7COUNTLOW   0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 
#define USB_DMA7COUNTHIGH   0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 
#define KPAD_CTL   0xffc04100 /* Controls keypad module enable and disable */
 
#define KPAD_PRESCALE   0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
 
#define KPAD_MSEL   0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
 
#define KPAD_ROWCOL   0xffc0410c /* Captures the row and column output values of the keys pressed */
 
#define KPAD_STAT   0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
 
#define KPAD_SOFTEVAL   0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
 
#define PIXC_CTL   0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
 
#define PIXC_PPL   0xffc04404 /* Holds the number of pixels per line of the display */
 
#define PIXC_LPF   0xffc04408 /* Holds the number of lines per frame of the display */
 
#define PIXC_AHSTART   0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
 
#define PIXC_AHEND   0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
 
#define PIXC_AVSTART   0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
 
#define PIXC_AVEND   0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
 
#define PIXC_ATRANSP   0xffc0441c /* Contains the transparency ratio (set A) */
 
#define PIXC_BHSTART   0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
 
#define PIXC_BHEND   0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
 
#define PIXC_BVSTART   0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
 
#define PIXC_BVEND   0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
 
#define PIXC_BTRANSP   0xffc04430 /* Contains the transparency ratio (set B) */
 
#define PIXC_INTRSTAT   0xffc0443c /* Overlay interrupt configuration/status */
 
#define PIXC_RYCON   0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
 
#define PIXC_GUCON   0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
 
#define PIXC_BVCON   0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
 
#define PIXC_CCBIAS   0xffc0444c /* Bias values for the color space conversion matrix */
 
#define PIXC_TC   0xffc04450 /* Holds the transparent color value */
 
#define HMDMA0_CONTROL   0xffc04500 /* Handshake MDMA0 Control Register */
 
#define HMDMA0_ECINIT   0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
 
#define HMDMA0_BCINIT   0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
 
#define HMDMA0_ECURGENT   0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
 
#define HMDMA0_ECOVERFLOW   0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
 
#define HMDMA0_ECOUNT   0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
 
#define HMDMA0_BCOUNT   0xffc04518 /* Handshake MDMA0 Current Block Count Register */
 
#define HMDMA1_CONTROL   0xffc04540 /* Handshake MDMA1 Control Register */
 
#define HMDMA1_ECINIT   0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
 
#define HMDMA1_BCINIT   0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
 
#define HMDMA1_ECURGENT   0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
 
#define HMDMA1_ECOVERFLOW   0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
 
#define HMDMA1_ECOUNT   0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
 
#define HMDMA1_BCOUNT   0xffc04558 /* Handshake MDMA1 Current Block Count Register */
 
#define PIXC_EN   0x1 /* Pixel Compositor Enable */
 
#define OVR_A_EN   0x2 /* Overlay A Enable */
 
#define OVR_B_EN   0x4 /* Overlay B Enable */
 
#define IMG_FORM   0x8 /* Image Data Format */
 
#define OVR_FORM   0x10 /* Overlay Data Format */
 
#define OUT_FORM   0x20 /* Output Data Format */
 
#define UDS_MOD   0x40 /* Resampling Mode */
 
#define TC_EN   0x80 /* Transparent Color Enable */
 
#define IMG_STAT   0x300 /* Image FIFO Status */
 
#define OVR_STAT   0xc00 /* Overlay FIFO Status */
 
#define WM_LVL   0x3000 /* FIFO Watermark Level */
 
#define A_HSTART   0xfff /* Horizontal Start Coordinates */
 
#define A_HEND   0xfff /* Horizontal End Coordinates */
 
#define A_VSTART   0x3ff /* Vertical Start Coordinates */
 
#define A_VEND   0x3ff /* Vertical End Coordinates */
 
#define A_TRANSP   0xf /* Transparency Value */
 
#define B_HSTART   0xfff /* Horizontal Start Coordinates */
 
#define B_HEND   0xfff /* Horizontal End Coordinates */
 
#define B_VSTART   0x3ff /* Vertical Start Coordinates */
 
#define B_VEND   0x3ff /* Vertical End Coordinates */
 
#define B_TRANSP   0xf /* Transparency Value */
 
#define OVR_INT_EN   0x1 /* Interrupt at End of Last Valid Overlay */
 
#define FRM_INT_EN   0x2 /* Interrupt at End of Frame */
 
#define OVR_INT_STAT   0x4 /* Overlay Interrupt Status */
 
#define FRM_INT_STAT   0x8 /* Frame Interrupt Status */
 
#define A11   0x3ff /* A11 in the Coefficient Matrix */
 
#define A12   0xffc00 /* A12 in the Coefficient Matrix */
 
#define A13   0x3ff00000 /* A13 in the Coefficient Matrix */
 
#define RY_MULT4   0x40000000 /* Multiply Row by 4 */
 
#define A21   0x3ff /* A21 in the Coefficient Matrix */
 
#define A22   0xffc00 /* A22 in the Coefficient Matrix */
 
#define A23   0x3ff00000 /* A23 in the Coefficient Matrix */
 
#define GU_MULT4   0x40000000 /* Multiply Row by 4 */
 
#define A31   0x3ff /* A31 in the Coefficient Matrix */
 
#define A32   0xffc00 /* A32 in the Coefficient Matrix */
 
#define A33   0x3ff00000 /* A33 in the Coefficient Matrix */
 
#define BV_MULT4   0x40000000 /* Multiply Row by 4 */
 
#define A14   0x3ff /* A14 in the Bias Vector */
 
#define A24   0xffc00 /* A24 in the Bias Vector */
 
#define A34   0x3ff00000 /* A34 in the Bias Vector */
 
#define RY_TRANS   0xff /* Transparent Color - R/Y Component */
 
#define GU_TRANS   0xff00 /* Transparent Color - G/U Component */
 
#define BV_TRANS   0xff0000 /* Transparent Color - B/V Component */
 
#define HOST_EN   0x1 /* Host Enable */
 
#define HOST_END   0x2 /* Host Endianess */
 
#define DATA_SIZE   0x4 /* Data Size */
 
#define HOST_RST   0x8 /* Host Reset */
 
#define HRDY_OVR   0x20 /* Host Ready Override */
 
#define INT_MODE   0x40 /* Interrupt Mode */
 
#define BT_EN   0x80 /* Bus Timeout Enable */
 
#define EHW   0x100 /* Enable Host Write */
 
#define EHR   0x200 /* Enable Host Read */
 
#define BDR   0x400 /* Burst DMA Requests */
 
#define DMA_READY   0x1 /* DMA Ready */
 
#define FIFOFULL   0x2 /* FIFO Full */
 
#define FIFOEMPTY   0x4 /* FIFO Empty */
 
#define DMA_COMPLETE   0x8 /* DMA Complete */
 
#define HSHK   0x10 /* Host Handshake */
 
#define HSTIMEOUT   0x20 /* Host Timeout */
 
#define HIRQ   0x40 /* Host Interrupt Request */
 
#define ALLOW_CNFG   0x80 /* Allow New Configuration */
 
#define DMA_DIR   0x100 /* DMA Direction */
 
#define BTE   0x200 /* Bus Timeout Enabled */
 
#define COUNT_TIMEOUT   0x7ff /* Host Timeout count */
 
#define KPAD_EN   0x1 /* Keypad Enable */
 
#define KPAD_IRQMODE   0x6 /* Key Press Interrupt Enable */
 
#define KPAD_ROWEN   0x1c00 /* Row Enable Width */
 
#define KPAD_COLEN   0xe000 /* Column Enable Width */
 
#define KPAD_PRESCALE_VAL   0x3f /* Key Prescale Value */
 
#define DBON_SCALE   0xff /* Debounce Scale Value */
 
#define COLDRV_SCALE   0xff00 /* Column Driver Scale Value */
 
#define KPAD_ROW   0xff /* Rows Pressed */
 
#define KPAD_COL   0xff00 /* Columns Pressed */
 
#define KPAD_IRQ   0x1 /* Keypad Interrupt Status */
 
#define KPAD_MROWCOL   0x6 /* Multiple Row/Column Keypress Status */
 
#define KPAD_PRESSED   0x8 /* Key press current status */
 
#define KPAD_SOFTEVAL_E   0x2 /* Software Programmable Force Evaluate */
 
#define PIO_START   0x1 /* Start PIO/Reg Op */
 
#define MULTI_START   0x2 /* Start Multi-DMA Op */
 
#define ULTRA_START   0x4 /* Start Ultra-DMA Op */
 
#define XFER_DIR   0x8 /* Transfer Direction */
 
#define IORDY_EN   0x10 /* IORDY Enable */
 
#define FIFO_FLUSH   0x20 /* Flush FIFOs */
 
#define SOFT_RST   0x40 /* Soft Reset */
 
#define DEV_RST   0x80 /* Device Reset */
 
#define TFRCNT_RST   0x100 /* Trans Count Reset */
 
#define END_ON_TERM   0x200 /* End/Terminate Select */
 
#define PIO_USE_DMA   0x400 /* PIO-DMA Enable */
 
#define UDMAIN_FIFO_THRS   0xf000 /* Ultra DMA-IN FIFO Threshold */
 
#define PIO_XFER_ON   0x1 /* PIO transfer in progress */
 
#define MULTI_XFER_ON   0x2 /* Multi-word DMA transfer in progress */
 
#define ULTRA_XFER_ON   0x4 /* Ultra DMA transfer in progress */
 
#define ULTRA_IN_FL   0xf0 /* Ultra DMA Input FIFO Level */
 
#define DEV_ADDR   0x1f /* Device Address */
 
#define ATAPI_DEV_INT_MASK   0x1 /* Device interrupt mask */
 
#define PIO_DONE_MASK   0x2 /* PIO transfer done interrupt mask */
 
#define MULTI_DONE_MASK   0x4 /* Multi-DMA transfer done interrupt mask */
 
#define UDMAIN_DONE_MASK   0x8 /* Ultra-DMA in transfer done interrupt mask */
 
#define UDMAOUT_DONE_MASK   0x10 /* Ultra-DMA out transfer done interrupt mask */
 
#define HOST_TERM_XFER_MASK   0x20 /* Host terminate current transfer interrupt mask */
 
#define MULTI_TERM_MASK   0x40 /* Device terminate Multi-DMA transfer interrupt mask */
 
#define UDMAIN_TERM_MASK   0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
 
#define UDMAOUT_TERM_MASK   0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
 
#define ATAPI_DEV_INT   0x1 /* Device interrupt status */
 
#define PIO_DONE_INT   0x2 /* PIO transfer done interrupt status */
 
#define MULTI_DONE_INT   0x4 /* Multi-DMA transfer done interrupt status */
 
#define UDMAIN_DONE_INT   0x8 /* Ultra-DMA in transfer done interrupt status */
 
#define UDMAOUT_DONE_INT   0x10 /* Ultra-DMA out transfer done interrupt status */
 
#define HOST_TERM_XFER_INT   0x20 /* Host terminate current transfer interrupt status */
 
#define MULTI_TERM_INT   0x40 /* Device terminate Multi-DMA transfer interrupt status */
 
#define UDMAIN_TERM_INT   0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
 
#define UDMAOUT_TERM_INT   0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
 
#define ATAPI_INTR   0x1 /* Device interrupt to host line status */
 
#define ATAPI_DASP   0x2 /* Device dasp to host line status */
 
#define ATAPI_CS0N   0x4 /* ATAPI chip select 0 line status */
 
#define ATAPI_CS1N   0x8 /* ATAPI chip select 1 line status */
 
#define ATAPI_ADDR   0x70 /* ATAPI address line status */
 
#define ATAPI_DMAREQ   0x80 /* ATAPI DMA request line status */
 
#define ATAPI_DMAACKN   0x100 /* ATAPI DMA acknowledge line status */
 
#define ATAPI_DIOWN   0x200 /* ATAPI write line status */
 
#define ATAPI_DIORN   0x400 /* ATAPI read line status */
 
#define ATAPI_IORDY   0x800 /* ATAPI IORDY line status */
 
#define PIO_CSTATE   0xf /* PIO mode state machine current state */
 
#define DMA_CSTATE   0xf0 /* DMA mode state machine current state */
 
#define UDMAIN_CSTATE   0xf00 /* Ultra DMA-In mode state machine current state */
 
#define UDMAOUT_CSTATE   0xf000 /* ATAPI IORDY line status */
 
#define ATAPI_HOST_TERM   0x1 /* Host terminationation */
 
#define T2_REG   0xff /* End of cycle time for register access transfers */
 
#define TEOC_REG   0xff00 /* Selects DIOR/DIOW pulsewidth */
 
#define T1_REG   0xf /* Time from address valid to DIOR/DIOW */
 
#define T2_REG_PIO   0xff0 /* DIOR/DIOW pulsewidth */
 
#define T4_REG   0xf000 /* DIOW data hold */
 
#define TEOC_REG_PIO   0xff /* End of cycle time for PIO access transfers. */
 
#define TD   0xff /* DIOR/DIOW asserted pulsewidth */
 
#define TM   0xff00 /* Time from address valid to DIOR/DIOW */
 
#define TKW   0xff /* Selects DIOW negated pulsewidth */
 
#define TKR   0xff00 /* Selects DIOR negated pulsewidth */
 
#define TH   0xff /* Selects DIOW data hold */
 
#define TEOC   0xff00 /* Selects end of cycle for DMA */
 
#define TACK   0xff /* Selects setup and hold times for TACK */
 
#define TENV   0xff00 /* Selects envelope time */
 
#define TDVS   0xff /* Selects data valid setup time */
 
#define TCYC_TDVS   0xff00 /* Selects cycle time - TDVS time */
 
#define TSS   0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
 
#define TMLI   0xff00 /* Selects interlock time */
 
#define TZAH   0xff /* Selects minimum delay required for output */
 
#define READY_PAUSE   0xff00 /* Selects ready to pause */
 
#define TIMEN8   0x1 /* Timer 8 Enable */
 
#define TIMEN9   0x2 /* Timer 9 Enable */
 
#define TIMEN10   0x4 /* Timer 10 Enable */
 
#define TIMDIS8   0x1 /* Timer 8 Disable */
 
#define TIMDIS9   0x2 /* Timer 9 Disable */
 
#define TIMDIS10   0x4 /* Timer 10 Disable */
 
#define TIMIL8   0x1 /* Timer 8 Interrupt */
 
#define TIMIL9   0x2 /* Timer 9 Interrupt */
 
#define TIMIL10   0x4 /* Timer 10 Interrupt */
 
#define TOVF_ERR8   0x10 /* Timer 8 Counter Overflow */
 
#define TOVF_ERR9   0x20 /* Timer 9 Counter Overflow */
 
#define TOVF_ERR10   0x40 /* Timer 10 Counter Overflow */
 
#define TRUN8   0x1000 /* Timer 8 Slave Enable Status */
 
#define TRUN9   0x2000 /* Timer 9 Slave Enable Status */
 
#define TRUN10   0x4000 /* Timer 10 Slave Enable Status */
 
#define FUNCTION_ADDRESS   0x7f /* Function address */
 
#define ENABLE_SUSPENDM   0x1 /* enable SuspendM output */
 
#define SUSPEND_MODE   0x2 /* Suspend Mode indicator */
 
#define RESUME_MODE   0x4 /* DMA Mode */
 
#define RESET   0x8 /* Reset indicator */
 
#define HS_MODE   0x10 /* High Speed mode indicator */
 
#define HS_ENABLE   0x20 /* high Speed Enable */
 
#define SOFT_CONN   0x40 /* Soft connect */
 
#define ISO_UPDATE   0x80 /* Isochronous update */
 
#define EP0_TX   0x1 /* Tx Endpoint 0 interrupt */
 
#define EP1_TX   0x2 /* Tx Endpoint 1 interrupt */
 
#define EP2_TX   0x4 /* Tx Endpoint 2 interrupt */
 
#define EP3_TX   0x8 /* Tx Endpoint 3 interrupt */
 
#define EP4_TX   0x10 /* Tx Endpoint 4 interrupt */
 
#define EP5_TX   0x20 /* Tx Endpoint 5 interrupt */
 
#define EP6_TX   0x40 /* Tx Endpoint 6 interrupt */
 
#define EP7_TX   0x80 /* Tx Endpoint 7 interrupt */
 
#define EP1_RX   0x2 /* Rx Endpoint 1 interrupt */
 
#define EP2_RX   0x4 /* Rx Endpoint 2 interrupt */
 
#define EP3_RX   0x8 /* Rx Endpoint 3 interrupt */
 
#define EP4_RX   0x10 /* Rx Endpoint 4 interrupt */
 
#define EP5_RX   0x20 /* Rx Endpoint 5 interrupt */
 
#define EP6_RX   0x40 /* Rx Endpoint 6 interrupt */
 
#define EP7_RX   0x80 /* Rx Endpoint 7 interrupt */
 
#define EP0_TX_E   0x1 /* Endpoint 0 interrupt Enable */
 
#define EP1_TX_E   0x2 /* Tx Endpoint 1 interrupt Enable */
 
#define EP2_TX_E   0x4 /* Tx Endpoint 2 interrupt Enable */
 
#define EP3_TX_E   0x8 /* Tx Endpoint 3 interrupt Enable */
 
#define EP4_TX_E   0x10 /* Tx Endpoint 4 interrupt Enable */
 
#define EP5_TX_E   0x20 /* Tx Endpoint 5 interrupt Enable */
 
#define EP6_TX_E   0x40 /* Tx Endpoint 6 interrupt Enable */
 
#define EP7_TX_E   0x80 /* Tx Endpoint 7 interrupt Enable */
 
#define EP1_RX_E   0x2 /* Rx Endpoint 1 interrupt Enable */
 
#define EP2_RX_E   0x4 /* Rx Endpoint 2 interrupt Enable */
 
#define EP3_RX_E   0x8 /* Rx Endpoint 3 interrupt Enable */
 
#define EP4_RX_E   0x10 /* Rx Endpoint 4 interrupt Enable */
 
#define EP5_RX_E   0x20 /* Rx Endpoint 5 interrupt Enable */
 
#define EP6_RX_E   0x40 /* Rx Endpoint 6 interrupt Enable */
 
#define EP7_RX_E   0x80 /* Rx Endpoint 7 interrupt Enable */
 
#define SUSPEND_B   0x1 /* Suspend indicator */
 
#define RESUME_B   0x2 /* Resume indicator */
 
#define RESET_OR_BABLE_B   0x4 /* Reset/babble indicator */
 
#define SOF_B   0x8 /* Start of frame */
 
#define CONN_B   0x10 /* Connection indicator */
 
#define DISCON_B   0x20 /* Disconnect indicator */
 
#define SESSION_REQ_B   0x40 /* Session Request */
 
#define VBUS_ERROR_B   0x80 /* Vbus threshold indicator */
 
#define SUSPEND_BE   0x1 /* Suspend indicator int enable */
 
#define RESUME_BE   0x2 /* Resume indicator int enable */
 
#define RESET_OR_BABLE_BE   0x4 /* Reset/babble indicator int enable */
 
#define SOF_BE   0x8 /* Start of frame int enable */
 
#define CONN_BE   0x10 /* Connection indicator int enable */
 
#define DISCON_BE   0x20 /* Disconnect indicator int enable */
 
#define SESSION_REQ_BE   0x40 /* Session Request int enable */
 
#define VBUS_ERROR_BE   0x80 /* Vbus threshold indicator int enable */
 
#define FRAME_NUMBER   0x7ff /* Frame number */
 
#define SELECTED_ENDPOINT   0xf /* selected endpoint */
 
#define GLOBAL_ENA   0x1 /* enables USB module */
 
#define EP1_TX_ENA   0x2 /* Transmit endpoint 1 enable */
 
#define EP2_TX_ENA   0x4 /* Transmit endpoint 2 enable */
 
#define EP3_TX_ENA   0x8 /* Transmit endpoint 3 enable */
 
#define EP4_TX_ENA   0x10 /* Transmit endpoint 4 enable */
 
#define EP5_TX_ENA   0x20 /* Transmit endpoint 5 enable */
 
#define EP6_TX_ENA   0x40 /* Transmit endpoint 6 enable */
 
#define EP7_TX_ENA   0x80 /* Transmit endpoint 7 enable */
 
#define EP1_RX_ENA   0x100 /* Receive endpoint 1 enable */
 
#define EP2_RX_ENA   0x200 /* Receive endpoint 2 enable */
 
#define EP3_RX_ENA   0x400 /* Receive endpoint 3 enable */
 
#define EP4_RX_ENA   0x800 /* Receive endpoint 4 enable */
 
#define EP5_RX_ENA   0x1000 /* Receive endpoint 5 enable */
 
#define EP6_RX_ENA   0x2000 /* Receive endpoint 6 enable */
 
#define EP7_RX_ENA   0x4000 /* Receive endpoint 7 enable */
 
#define SESSION   0x1 /* session indicator */
 
#define HOST_REQ   0x2 /* Host negotiation request */
 
#define HOST_MODE   0x4 /* indicates USBDRC is a host */
 
#define VBUS0   0x8 /* Vbus level indicator[0] */
 
#define VBUS1   0x10 /* Vbus level indicator[1] */
 
#define LSDEV   0x20 /* Low-speed indicator */
 
#define FSDEV   0x40 /* Full or High-speed indicator */
 
#define B_DEVICE   0x80 /* A' or 'B' device indicator */
 
#define DRIVE_VBUS_ON   0x1 /* indicator to drive VBUS control circuit */
 
#define DRIVE_VBUS_OFF   0x2 /* indicator to shut off charge pump */
 
#define CHRG_VBUS_START   0x4 /* indicator for external circuit to start charging VBUS */
 
#define CHRG_VBUS_END   0x8 /* indicator for external circuit to end charging VBUS */
 
#define DISCHRG_VBUS_START   0x10 /* indicator to start discharging VBUS */
 
#define DISCHRG_VBUS_END   0x20 /* indicator to stop discharging VBUS */
 
#define DRIVE_VBUS_ON_ENA   0x1 /* enable DRIVE_VBUS_ON interrupt */
 
#define DRIVE_VBUS_OFF_ENA   0x2 /* enable DRIVE_VBUS_OFF interrupt */
 
#define CHRG_VBUS_START_ENA   0x4 /* enable CHRG_VBUS_START interrupt */
 
#define CHRG_VBUS_END_ENA   0x8 /* enable CHRG_VBUS_END interrupt */
 
#define DISCHRG_VBUS_START_ENA   0x10 /* enable DISCHRG_VBUS_START interrupt */
 
#define DISCHRG_VBUS_END_ENA   0x20 /* enable DISCHRG_VBUS_END interrupt */
 
#define RXPKTRDY   0x1 /* data packet receive indicator */
 
#define TXPKTRDY   0x2 /* data packet in FIFO indicator */
 
#define STALL_SENT   0x4 /* STALL handshake sent */
 
#define DATAEND   0x8 /* Data end indicator */
 
#define SETUPEND   0x10 /* Setup end */
 
#define SENDSTALL   0x20 /* Send STALL handshake */
 
#define SERVICED_RXPKTRDY   0x40 /* used to clear the RxPktRdy bit */
 
#define SERVICED_SETUPEND   0x80 /* used to clear the SetupEnd bit */
 
#define FLUSHFIFO   0x100 /* flush endpoint FIFO */
 
#define STALL_RECEIVED_H   0x4 /* STALL handshake received host mode */
 
#define SETUPPKT_H   0x8 /* send Setup token host mode */
 
#define ERROR_H   0x10 /* timeout error indicator host mode */
 
#define REQPKT_H   0x20 /* Request an IN transaction host mode */
 
#define STATUSPKT_H   0x40 /* Status stage transaction host mode */
 
#define NAK_TIMEOUT_H   0x80 /* EP0 halted after a NAK host mode */
 
#define EP0_RX_COUNT   0x7f /* number of received bytes in EP0 FIFO */
 
#define EP0_NAK_LIMIT   0x1f /* number of frames/micro frames after which EP0 timeouts */
 
#define MAX_PACKET_SIZE_T   0x7ff /* maximum data pay load in a frame */
 
#define MAX_PACKET_SIZE_R   0x7ff /* maximum data pay load in a frame */
 
#define TXPKTRDY_T   0x1 /* data packet in FIFO indicator */
 
#define FIFO_NOT_EMPTY_T   0x2 /* FIFO not empty */
 
#define UNDERRUN_T   0x4 /* TxPktRdy not set for an IN token */
 
#define FLUSHFIFO_T   0x8 /* flush endpoint FIFO */
 
#define STALL_SEND_T   0x10 /* issue a Stall handshake */
 
#define STALL_SENT_T   0x20 /* Stall handshake transmitted */
 
#define CLEAR_DATATOGGLE_T   0x40 /* clear endpoint data toggle */
 
#define INCOMPTX_T   0x80 /* indicates that a large packet is split */
 
#define DMAREQMODE_T   0x400 /* DMA mode (0 or 1) selection */
 
#define FORCE_DATATOGGLE_T   0x800 /* Force data toggle */
 
#define DMAREQ_ENA_T   0x1000 /* Enable DMA request for Tx EP */
 
#define ISO_T   0x4000 /* enable Isochronous transfers */
 
#define AUTOSET_T   0x8000 /* allows TxPktRdy to be set automatically */
 
#define ERROR_TH   0x4 /* error condition host mode */
 
#define STALL_RECEIVED_TH   0x20 /* Stall handshake received host mode */
 
#define NAK_TIMEOUT_TH   0x80 /* NAK timeout host mode */
 
#define TX_COUNT   0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
 
#define RXPKTRDY_R   0x1 /* data packet in FIFO indicator */
 
#define FIFO_FULL_R   0x2 /* FIFO not empty */
 
#define OVERRUN_R   0x4 /* TxPktRdy not set for an IN token */
 
#define DATAERROR_R   0x8 /* Out packet cannot be loaded into Rx FIFO */
 
#define FLUSHFIFO_R   0x10 /* flush endpoint FIFO */
 
#define STALL_SEND_R   0x20 /* issue a Stall handshake */
 
#define STALL_SENT_R   0x40 /* Stall handshake transmitted */
 
#define CLEAR_DATATOGGLE_R   0x80 /* clear endpoint data toggle */
 
#define INCOMPRX_R   0x100 /* indicates that a large packet is split */
 
#define DMAREQMODE_R   0x800 /* DMA mode (0 or 1) selection */
 
#define DISNYET_R   0x1000 /* disable Nyet handshakes */
 
#define DMAREQ_ENA_R   0x2000 /* Enable DMA request for Tx EP */
 
#define ISO_R   0x4000 /* enable Isochronous transfers */
 
#define AUTOCLEAR_R   0x8000 /* allows TxPktRdy to be set automatically */
 
#define ERROR_RH   0x4 /* TxPktRdy not set for an IN token host mode */
 
#define REQPKT_RH   0x20 /* request an IN transaction host mode */
 
#define STALL_RECEIVED_RH   0x40 /* Stall handshake received host mode */
 
#define INCOMPRX_RH   0x100 /* indicates that a large packet is split host mode */
 
#define DMAREQMODE_RH   0x800 /* DMA mode (0 or 1) selection host mode */
 
#define AUTOREQ_RH   0x4000 /* sets ReqPkt automatically host mode */
 
#define RX_COUNT   0x1fff /* Number of received bytes in the packet in the Rx FIFO */
 
#define TARGET_EP_NO_T   0xf /* EP number */
 
#define PROTOCOL_T   0xc /* transfer type */
 
#define TX_POLL_INTERVAL   0xff /* polling interval for selected Tx EP */
 
#define TARGET_EP_NO_R   0xf /* EP number */
 
#define PROTOCOL_R   0xc /* transfer type */
 
#define RX_POLL_INTERVAL   0xff /* polling interval for selected Rx EP */
 
#define DMA0_INT   0x1 /* DMA0 pending interrupt */
 
#define DMA1_INT   0x2 /* DMA1 pending interrupt */
 
#define DMA2_INT   0x4 /* DMA2 pending interrupt */
 
#define DMA3_INT   0x8 /* DMA3 pending interrupt */
 
#define DMA4_INT   0x10 /* DMA4 pending interrupt */
 
#define DMA5_INT   0x20 /* DMA5 pending interrupt */
 
#define DMA6_INT   0x40 /* DMA6 pending interrupt */
 
#define DMA7_INT   0x80 /* DMA7 pending interrupt */
 
#define DMA_ENA   0x1 /* DMA enable */
 
#define DIRECTION   0x2 /* direction of DMA transfer */
 
#define MODE   0x4 /* DMA Bus error */
 
#define INT_ENA   0x8 /* Interrupt enable */
 
#define EPNUM   0xf0 /* EP number */
 
#define BUSERROR   0x100 /* DMA Bus error */
 
#define DMA_ADDR_HIGH   0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
 
#define DMA_ADDR_LOW   0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
 
#define DMA_COUNT_HIGH   0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
 
#define DMA_COUNT_LOW   0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
 

Macro Definition Documentation

#define A11   0x3ff /* A11 in the Coefficient Matrix */

Definition at line 553 of file defBF547.h.

#define A12   0xffc00 /* A12 in the Coefficient Matrix */

Definition at line 554 of file defBF547.h.

#define A13   0x3ff00000 /* A13 in the Coefficient Matrix */

Definition at line 555 of file defBF547.h.

#define A14   0x3ff /* A14 in the Bias Vector */

Definition at line 574 of file defBF547.h.

#define A21   0x3ff /* A21 in the Coefficient Matrix */

Definition at line 560 of file defBF547.h.

#define A22   0xffc00 /* A22 in the Coefficient Matrix */

Definition at line 561 of file defBF547.h.

#define A23   0x3ff00000 /* A23 in the Coefficient Matrix */

Definition at line 562 of file defBF547.h.

#define A24   0xffc00 /* A24 in the Bias Vector */

Definition at line 575 of file defBF547.h.

#define A31   0x3ff /* A31 in the Coefficient Matrix */

Definition at line 567 of file defBF547.h.

#define A32   0xffc00 /* A32 in the Coefficient Matrix */

Definition at line 568 of file defBF547.h.

#define A33   0x3ff00000 /* A33 in the Coefficient Matrix */

Definition at line 569 of file defBF547.h.

#define A34   0x3ff00000 /* A34 in the Bias Vector */

Definition at line 576 of file defBF547.h.

#define A_HEND   0xfff /* Horizontal End Coordinates */

Definition at line 510 of file defBF547.h.

#define A_HSTART   0xfff /* Horizontal Start Coordinates */

Definition at line 506 of file defBF547.h.

#define A_TRANSP   0xf /* Transparency Value */

Definition at line 522 of file defBF547.h.

#define A_VEND   0x3ff /* Vertical End Coordinates */

Definition at line 518 of file defBF547.h.

#define A_VSTART   0x3ff /* Vertical Start Coordinates */

Definition at line 514 of file defBF547.h.

#define ALLOW_CNFG   0x80 /* Allow New Configuration */

Definition at line 606 of file defBF547.h.

#define ATAPI_ADDR   0x70 /* ATAPI address line status */

Definition at line 701 of file defBF547.h.

#define ATAPI_CONTROL   0xffc03800 /* ATAPI Control Register */

Definition at line 125 of file defBF547.h.

#define ATAPI_CS0N   0x4 /* ATAPI chip select 0 line status */

Definition at line 699 of file defBF547.h.

#define ATAPI_CS1N   0x8 /* ATAPI chip select 1 line status */

Definition at line 700 of file defBF547.h.

#define ATAPI_DASP   0x2 /* Device dasp to host line status */

Definition at line 698 of file defBF547.h.

#define ATAPI_DEV_ADDR   0xffc03808 /* ATAPI Device Register Address */

Definition at line 127 of file defBF547.h.

#define ATAPI_DEV_INT   0x1 /* Device interrupt status */

Definition at line 685 of file defBF547.h.

#define ATAPI_DEV_INT_MASK   0x1 /* Device interrupt mask */

Definition at line 673 of file defBF547.h.

#define ATAPI_DEV_RXBUF   0xffc03810 /* ATAPI Device Register Read Data */

Definition at line 129 of file defBF547.h.

#define ATAPI_DEV_TXBUF   0xffc0380c /* ATAPI Device Register Write Data */

Definition at line 128 of file defBF547.h.

#define ATAPI_DIORN   0x400 /* ATAPI read line status */

Definition at line 705 of file defBF547.h.

#define ATAPI_DIOWN   0x200 /* ATAPI write line status */

Definition at line 704 of file defBF547.h.

#define ATAPI_DMA_TFRCNT   0xffc03830 /* ATAPI DMA mode transfer count */

Definition at line 137 of file defBF547.h.

#define ATAPI_DMAACKN   0x100 /* ATAPI DMA acknowledge line status */

Definition at line 703 of file defBF547.h.

#define ATAPI_DMAREQ   0x80 /* ATAPI DMA request line status */

Definition at line 702 of file defBF547.h.

#define ATAPI_HOST_TERM   0x1 /* Host terminationation */

Definition at line 717 of file defBF547.h.

#define ATAPI_INT_MASK   0xffc03814 /* ATAPI Interrupt Mask Register */

Definition at line 130 of file defBF547.h.

#define ATAPI_INT_STATUS   0xffc03818 /* ATAPI Interrupt Status Register */

Definition at line 131 of file defBF547.h.

#define ATAPI_INTR   0x1 /* Device interrupt to host line status */

Definition at line 697 of file defBF547.h.

#define ATAPI_IORDY   0x800 /* ATAPI IORDY line status */

Definition at line 706 of file defBF547.h.

#define ATAPI_LINE_STATUS   0xffc03820 /* ATAPI Line Status */

Definition at line 133 of file defBF547.h.

#define ATAPI_MULTI_TIM_0   0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */

Definition at line 143 of file defBF547.h.

#define ATAPI_MULTI_TIM_1   0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */

Definition at line 144 of file defBF547.h.

#define ATAPI_MULTI_TIM_2   0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */

Definition at line 145 of file defBF547.h.

#define ATAPI_PIO_TFRCNT   0xffc0382c /* ATAPI PIO mode transfer count */

Definition at line 136 of file defBF547.h.

#define ATAPI_PIO_TIM_0   0xffc03844 /* ATAPI PIO Timing 0 Register */

Definition at line 141 of file defBF547.h.

#define ATAPI_PIO_TIM_1   0xffc03848 /* ATAPI PIO Timing 1 Register */

Definition at line 142 of file defBF547.h.

#define ATAPI_REG_TIM_0   0xffc03840 /* ATAPI Register Transfer Timing 0 */

Definition at line 140 of file defBF547.h.

#define ATAPI_SM_STATE   0xffc03824 /* ATAPI State Machine Status */

Definition at line 134 of file defBF547.h.

#define ATAPI_STATUS   0xffc03804 /* ATAPI Status Register */

Definition at line 126 of file defBF547.h.

#define ATAPI_TERMINATE   0xffc03828 /* ATAPI Host Terminate */

Definition at line 135 of file defBF547.h.

#define ATAPI_UDMAOUT_TFRCNT   0xffc03838 /* ATAPI UDMAOUT transfer count */

Definition at line 139 of file defBF547.h.

#define ATAPI_ULTRA_TIM_0   0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */

Definition at line 146 of file defBF547.h.

#define ATAPI_ULTRA_TIM_1   0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */

Definition at line 147 of file defBF547.h.

#define ATAPI_ULTRA_TIM_2   0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */

Definition at line 148 of file defBF547.h.

#define ATAPI_ULTRA_TIM_3   0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */

Definition at line 149 of file defBF547.h.

#define ATAPI_UMAIN_TFRCNT   0xffc03834 /* ATAPI UDMAIN transfer count */

Definition at line 138 of file defBF547.h.

#define ATAPI_XFER_LEN   0xffc0381c /* ATAPI Length of Transfer */

Definition at line 132 of file defBF547.h.

#define AUTOCLEAR_R   0x8000 /* allows TxPktRdy to be set automatically */

Definition at line 1001 of file defBF547.h.

#define AUTOREQ_RH   0x4000 /* sets ReqPkt automatically host mode */

Definition at line 1007 of file defBF547.h.

#define AUTOSET_T   0x8000 /* allows TxPktRdy to be set automatically */

Definition at line 977 of file defBF547.h.

#define B_DEVICE   0x80 /* A' or 'B' device indicator */

Definition at line 909 of file defBF547.h.

#define B_HEND   0xfff /* Horizontal End Coordinates */

Definition at line 530 of file defBF547.h.

#define B_HSTART   0xfff /* Horizontal Start Coordinates */

Definition at line 526 of file defBF547.h.

#define B_TRANSP   0xf /* Transparency Value */

Definition at line 542 of file defBF547.h.

#define B_VEND   0x3ff /* Vertical End Coordinates */

Definition at line 538 of file defBF547.h.

#define B_VSTART   0x3ff /* Vertical Start Coordinates */

Definition at line 534 of file defBF547.h.

#define BDR   0x400 /* Burst DMA Requests */

Definition at line 595 of file defBF547.h.

#define BT_EN   0x80 /* Bus Timeout Enable */

Definition at line 592 of file defBF547.h.

#define BTE   0x200 /* Bus Timeout Enabled */

Definition at line 608 of file defBF547.h.

#define BUSERROR   0x100 /* DMA Bus error */

Definition at line 1049 of file defBF547.h.

#define BV_MULT4   0x40000000 /* Multiply Row by 4 */

Definition at line 570 of file defBF547.h.

#define BV_TRANS   0xff0000 /* Transparent Color - B/V Component */

Definition at line 582 of file defBF547.h.

#define CHRG_VBUS_END   0x8 /* indicator for external circuit to end charging VBUS */

Definition at line 916 of file defBF547.h.

#define CHRG_VBUS_END_ENA   0x8 /* enable CHRG_VBUS_END interrupt */

Definition at line 925 of file defBF547.h.

#define CHRG_VBUS_START   0x4 /* indicator for external circuit to start charging VBUS */

Definition at line 915 of file defBF547.h.

#define CHRG_VBUS_START_ENA   0x4 /* enable CHRG_VBUS_START interrupt */

Definition at line 924 of file defBF547.h.

#define CLEAR_DATATOGGLE_R   0x80 /* clear endpoint data toggle */

Definition at line 995 of file defBF547.h.

#define CLEAR_DATATOGGLE_T   0x40 /* clear endpoint data toggle */

Definition at line 971 of file defBF547.h.

#define COLDRV_SCALE   0xff00 /* Column Driver Scale Value */

Definition at line 628 of file defBF547.h.

#define CONN_B   0x10 /* Connection indicator */

Definition at line 858 of file defBF547.h.

#define CONN_BE   0x10 /* Connection indicator int enable */

Definition at line 869 of file defBF547.h.

#define COUNT_TIMEOUT   0x7ff /* Host Timeout count */

Definition at line 612 of file defBF547.h.

#define DATA_SIZE   0x4 /* Data Size */

Definition at line 588 of file defBF547.h.

#define DATAEND   0x8 /* Data end indicator */

Definition at line 934 of file defBF547.h.

#define DATAERROR_R   0x8 /* Out packet cannot be loaded into Rx FIFO */

Definition at line 991 of file defBF547.h.

#define DBON_SCALE   0xff /* Debounce Scale Value */

Definition at line 627 of file defBF547.h.

#define DEV_ADDR   0x1f /* Device Address */

Definition at line 669 of file defBF547.h.

#define DEV_RST   0x80 /* Device Reset */

Definition at line 654 of file defBF547.h.

#define DIRECTION   0x2 /* direction of DMA transfer */

Definition at line 1045 of file defBF547.h.

#define DISCHRG_VBUS_END   0x20 /* indicator to stop discharging VBUS */

Definition at line 918 of file defBF547.h.

#define DISCHRG_VBUS_END_ENA   0x20 /* enable DISCHRG_VBUS_END interrupt */

Definition at line 927 of file defBF547.h.

#define DISCHRG_VBUS_START   0x10 /* indicator to start discharging VBUS */

Definition at line 917 of file defBF547.h.

#define DISCHRG_VBUS_START_ENA   0x10 /* enable DISCHRG_VBUS_START interrupt */

Definition at line 926 of file defBF547.h.

#define DISCON_B   0x20 /* Disconnect indicator */

Definition at line 859 of file defBF547.h.

#define DISCON_BE   0x20 /* Disconnect indicator int enable */

Definition at line 870 of file defBF547.h.

#define DISNYET_R   0x1000 /* disable Nyet handshakes */

Definition at line 998 of file defBF547.h.

#define DMA0_INT   0x1 /* DMA0 pending interrupt */

Definition at line 1033 of file defBF547.h.

#define DMA1_INT   0x2 /* DMA1 pending interrupt */

Definition at line 1034 of file defBF547.h.

#define DMA2_INT   0x4 /* DMA2 pending interrupt */

Definition at line 1035 of file defBF547.h.

#define DMA3_INT   0x8 /* DMA3 pending interrupt */

Definition at line 1036 of file defBF547.h.

#define DMA4_INT   0x10 /* DMA4 pending interrupt */

Definition at line 1037 of file defBF547.h.

#define DMA5_INT   0x20 /* DMA5 pending interrupt */

Definition at line 1038 of file defBF547.h.

#define DMA6_INT   0x40 /* DMA6 pending interrupt */

Definition at line 1039 of file defBF547.h.

#define DMA7_INT   0x80 /* DMA7 pending interrupt */

Definition at line 1040 of file defBF547.h.

#define DMA_ADDR_HIGH   0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */

Definition at line 1053 of file defBF547.h.

#define DMA_ADDR_LOW   0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */

Definition at line 1057 of file defBF547.h.

#define DMA_COMPLETE   0x8 /* DMA Complete */

Definition at line 602 of file defBF547.h.

#define DMA_COUNT_HIGH   0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */

Definition at line 1061 of file defBF547.h.

#define DMA_COUNT_LOW   0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */

Definition at line 1065 of file defBF547.h.

#define DMA_CSTATE   0xf0 /* DMA mode state machine current state */

Definition at line 711 of file defBF547.h.

#define DMA_DIR   0x100 /* DMA Direction */

Definition at line 607 of file defBF547.h.

#define DMA_ENA   0x1 /* DMA enable */

Definition at line 1044 of file defBF547.h.

#define DMA_READY   0x1 /* DMA Ready */

Definition at line 599 of file defBF547.h.

#define DMAREQ_ENA_R   0x2000 /* Enable DMA request for Tx EP */

Definition at line 999 of file defBF547.h.

#define DMAREQ_ENA_T   0x1000 /* Enable DMA request for Tx EP */

Definition at line 975 of file defBF547.h.

#define DMAREQMODE_R   0x800 /* DMA mode (0 or 1) selection */

Definition at line 997 of file defBF547.h.

#define DMAREQMODE_RH   0x800 /* DMA mode (0 or 1) selection host mode */

Definition at line 1006 of file defBF547.h.

#define DMAREQMODE_T   0x400 /* DMA mode (0 or 1) selection */

Definition at line 973 of file defBF547.h.

#define DRIVE_VBUS_OFF   0x2 /* indicator to shut off charge pump */

Definition at line 914 of file defBF547.h.

#define DRIVE_VBUS_OFF_ENA   0x2 /* enable DRIVE_VBUS_OFF interrupt */

Definition at line 923 of file defBF547.h.

#define DRIVE_VBUS_ON   0x1 /* indicator to drive VBUS control circuit */

Definition at line 913 of file defBF547.h.

#define DRIVE_VBUS_ON_ENA   0x1 /* enable DRIVE_VBUS_ON interrupt */

Definition at line 922 of file defBF547.h.

#define EHR   0x200 /* Enable Host Read */

Definition at line 594 of file defBF547.h.

#define EHW   0x100 /* Enable Host Write */

Definition at line 593 of file defBF547.h.

#define ENABLE_SUSPENDM   0x1 /* enable SuspendM output */

Definition at line 801 of file defBF547.h.

#define END_ON_TERM   0x200 /* End/Terminate Select */

Definition at line 656 of file defBF547.h.

#define EP0_NAK_LIMIT   0x1f /* number of frames/micro frames after which EP0 timeouts */

Definition at line 953 of file defBF547.h.

#define EP0_RX_COUNT   0x7f /* number of received bytes in EP0 FIFO */

Definition at line 949 of file defBF547.h.

#define EP0_TX   0x1 /* Tx Endpoint 0 interrupt */

Definition at line 812 of file defBF547.h.

#define EP0_TX_E   0x1 /* Endpoint 0 interrupt Enable */

Definition at line 833 of file defBF547.h.

#define EP1_RX   0x2 /* Rx Endpoint 1 interrupt */

Definition at line 823 of file defBF547.h.

#define EP1_RX_E   0x2 /* Rx Endpoint 1 interrupt Enable */

Definition at line 844 of file defBF547.h.

#define EP1_RX_ENA   0x100 /* Receive endpoint 1 enable */

Definition at line 892 of file defBF547.h.

#define EP1_TX   0x2 /* Tx Endpoint 1 interrupt */

Definition at line 813 of file defBF547.h.

#define EP1_TX_E   0x2 /* Tx Endpoint 1 interrupt Enable */

Definition at line 834 of file defBF547.h.

#define EP1_TX_ENA   0x2 /* Transmit endpoint 1 enable */

Definition at line 885 of file defBF547.h.

#define EP2_RX   0x4 /* Rx Endpoint 2 interrupt */

Definition at line 824 of file defBF547.h.

#define EP2_RX_E   0x4 /* Rx Endpoint 2 interrupt Enable */

Definition at line 845 of file defBF547.h.

#define EP2_RX_ENA   0x200 /* Receive endpoint 2 enable */

Definition at line 893 of file defBF547.h.

#define EP2_TX   0x4 /* Tx Endpoint 2 interrupt */

Definition at line 814 of file defBF547.h.

#define EP2_TX_E   0x4 /* Tx Endpoint 2 interrupt Enable */

Definition at line 835 of file defBF547.h.

#define EP2_TX_ENA   0x4 /* Transmit endpoint 2 enable */

Definition at line 886 of file defBF547.h.

#define EP3_RX   0x8 /* Rx Endpoint 3 interrupt */

Definition at line 825 of file defBF547.h.

#define EP3_RX_E   0x8 /* Rx Endpoint 3 interrupt Enable */

Definition at line 846 of file defBF547.h.

#define EP3_RX_ENA   0x400 /* Receive endpoint 3 enable */

Definition at line 894 of file defBF547.h.

#define EP3_TX   0x8 /* Tx Endpoint 3 interrupt */

Definition at line 815 of file defBF547.h.

#define EP3_TX_E   0x8 /* Tx Endpoint 3 interrupt Enable */

Definition at line 836 of file defBF547.h.

#define EP3_TX_ENA   0x8 /* Transmit endpoint 3 enable */

Definition at line 887 of file defBF547.h.

#define EP4_RX   0x10 /* Rx Endpoint 4 interrupt */

Definition at line 826 of file defBF547.h.

#define EP4_RX_E   0x10 /* Rx Endpoint 4 interrupt Enable */

Definition at line 847 of file defBF547.h.

#define EP4_RX_ENA   0x800 /* Receive endpoint 4 enable */

Definition at line 895 of file defBF547.h.

#define EP4_TX   0x10 /* Tx Endpoint 4 interrupt */

Definition at line 816 of file defBF547.h.

#define EP4_TX_E   0x10 /* Tx Endpoint 4 interrupt Enable */

Definition at line 837 of file defBF547.h.

#define EP4_TX_ENA   0x10 /* Transmit endpoint 4 enable */

Definition at line 888 of file defBF547.h.

#define EP5_RX   0x20 /* Rx Endpoint 5 interrupt */

Definition at line 827 of file defBF547.h.

#define EP5_RX_E   0x20 /* Rx Endpoint 5 interrupt Enable */

Definition at line 848 of file defBF547.h.

#define EP5_RX_ENA   0x1000 /* Receive endpoint 5 enable */

Definition at line 896 of file defBF547.h.

#define EP5_TX   0x20 /* Tx Endpoint 5 interrupt */

Definition at line 817 of file defBF547.h.

#define EP5_TX_E   0x20 /* Tx Endpoint 5 interrupt Enable */

Definition at line 838 of file defBF547.h.

#define EP5_TX_ENA   0x20 /* Transmit endpoint 5 enable */

Definition at line 889 of file defBF547.h.

#define EP6_RX   0x40 /* Rx Endpoint 6 interrupt */

Definition at line 828 of file defBF547.h.

#define EP6_RX_E   0x40 /* Rx Endpoint 6 interrupt Enable */

Definition at line 849 of file defBF547.h.

#define EP6_RX_ENA   0x2000 /* Receive endpoint 6 enable */

Definition at line 897 of file defBF547.h.

#define EP6_TX   0x40 /* Tx Endpoint 6 interrupt */

Definition at line 818 of file defBF547.h.

#define EP6_TX_E   0x40 /* Tx Endpoint 6 interrupt Enable */

Definition at line 839 of file defBF547.h.

#define EP6_TX_ENA   0x40 /* Transmit endpoint 6 enable */

Definition at line 890 of file defBF547.h.

#define EP7_RX   0x80 /* Rx Endpoint 7 interrupt */

Definition at line 829 of file defBF547.h.

#define EP7_RX_E   0x80 /* Rx Endpoint 7 interrupt Enable */

Definition at line 850 of file defBF547.h.

#define EP7_RX_ENA   0x4000 /* Receive endpoint 7 enable */

Definition at line 898 of file defBF547.h.

#define EP7_TX   0x80 /* Tx Endpoint 7 interrupt */

Definition at line 819 of file defBF547.h.

#define EP7_TX_E   0x80 /* Tx Endpoint 7 interrupt Enable */

Definition at line 840 of file defBF547.h.

#define EP7_TX_ENA   0x80 /* Transmit endpoint 7 enable */

Definition at line 891 of file defBF547.h.

#define EPNUM   0xf0 /* EP number */

Definition at line 1048 of file defBF547.h.

#define EPPI0_CLIP   0xffc01034 /* EPPI0 Clipping Register */

Definition at line 76 of file defBF547.h.

#define EPPI0_CLKDIV   0xffc0101c /* EPPI0 Clock Divide Register */

Definition at line 70 of file defBF547.h.

#define EPPI0_CONTROL   0xffc01020 /* EPPI0 Control Register */

Definition at line 71 of file defBF547.h.

#define EPPI0_FRAME   0xffc01014 /* EPPI0 Lines per Frame Register */

Definition at line 68 of file defBF547.h.

#define EPPI0_FS1P_AVPL   0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */

Definition at line 73 of file defBF547.h.

#define EPPI0_FS1W_HBL   0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */

Definition at line 72 of file defBF547.h.

#define EPPI0_FS2P_LAVF   0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */

Definition at line 75 of file defBF547.h.

#define EPPI0_FS2W_LVB   0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */

Definition at line 74 of file defBF547.h.

#define EPPI0_HCOUNT   0xffc01004 /* EPPI0 Horizontal Transfer Count Register */

Definition at line 64 of file defBF547.h.

#define EPPI0_HDELAY   0xffc01008 /* EPPI0 Horizontal Delay Count Register */

Definition at line 65 of file defBF547.h.

#define EPPI0_LINE   0xffc01018 /* EPPI0 Samples per Line Register */

Definition at line 69 of file defBF547.h.

#define EPPI0_STATUS   0xffc01000 /* EPPI0 Status Register */

Definition at line 63 of file defBF547.h.

#define EPPI0_VCOUNT   0xffc0100c /* EPPI0 Vertical Transfer Count Register */

Definition at line 66 of file defBF547.h.

#define EPPI0_VDELAY   0xffc01010 /* EPPI0 Vertical Delay Count Register */

Definition at line 67 of file defBF547.h.

#define ERROR_H   0x10 /* timeout error indicator host mode */

Definition at line 942 of file defBF547.h.

#define ERROR_RH   0x4 /* TxPktRdy not set for an IN token host mode */

Definition at line 1002 of file defBF547.h.

#define ERROR_TH   0x4 /* error condition host mode */

Definition at line 978 of file defBF547.h.

#define FIFO_FLUSH   0x20 /* Flush FIFOs */

Definition at line 652 of file defBF547.h.

#define FIFO_FULL_R   0x2 /* FIFO not empty */

Definition at line 989 of file defBF547.h.

#define FIFO_NOT_EMPTY_T   0x2 /* FIFO not empty */

Definition at line 966 of file defBF547.h.

#define FIFOEMPTY   0x4 /* FIFO Empty */

Definition at line 601 of file defBF547.h.

#define FIFOFULL   0x2 /* FIFO Full */

Definition at line 600 of file defBF547.h.

#define FLUSHFIFO   0x100 /* flush endpoint FIFO */

Definition at line 939 of file defBF547.h.

#define FLUSHFIFO_R   0x10 /* flush endpoint FIFO */

Definition at line 992 of file defBF547.h.

#define FLUSHFIFO_T   0x8 /* flush endpoint FIFO */

Definition at line 968 of file defBF547.h.

#define FORCE_DATATOGGLE_T   0x800 /* Force data toggle */

Definition at line 974 of file defBF547.h.

#define FRAME_NUMBER   0x7ff /* Frame number */

Definition at line 876 of file defBF547.h.

#define FRM_INT_EN   0x2 /* Interrupt at End of Frame */

Definition at line 547 of file defBF547.h.

#define FRM_INT_STAT   0x8 /* Frame Interrupt Status */

Definition at line 549 of file defBF547.h.

#define FSDEV   0x40 /* Full or High-speed indicator */

Definition at line 908 of file defBF547.h.

#define FUNCTION_ADDRESS   0x7f /* Function address */

Definition at line 797 of file defBF547.h.

#define GLOBAL_ENA   0x1 /* enables USB module */

Definition at line 884 of file defBF547.h.

#define GU_MULT4   0x40000000 /* Multiply Row by 4 */

Definition at line 563 of file defBF547.h.

#define GU_TRANS   0xff00 /* Transparent Color - G/U Component */

Definition at line 581 of file defBF547.h.

#define HIRQ   0x40 /* Host Interrupt Request */

Definition at line 605 of file defBF547.h.

#define HMDMA0_BCINIT   0xffc04508 /* Handshake MDMA0 Initial Block Count Register */

Definition at line 468 of file defBF547.h.

#define HMDMA0_BCOUNT   0xffc04518 /* Handshake MDMA0 Current Block Count Register */

Definition at line 472 of file defBF547.h.

#define HMDMA0_CONTROL   0xffc04500 /* Handshake MDMA0 Control Register */

Definition at line 466 of file defBF547.h.

#define HMDMA0_ECINIT   0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */

Definition at line 467 of file defBF547.h.

#define HMDMA0_ECOUNT   0xffc04514 /* Handshake MDMA0 Current Edge Count Register */

Definition at line 471 of file defBF547.h.

#define HMDMA0_ECOVERFLOW   0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */

Definition at line 470 of file defBF547.h.

#define HMDMA0_ECURGENT   0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */

Definition at line 469 of file defBF547.h.

#define HMDMA1_BCINIT   0xffc04548 /* Handshake MDMA1 Initial Block Count Register */

Definition at line 478 of file defBF547.h.

#define HMDMA1_BCOUNT   0xffc04558 /* Handshake MDMA1 Current Block Count Register */

Definition at line 482 of file defBF547.h.

#define HMDMA1_CONTROL   0xffc04540 /* Handshake MDMA1 Control Register */

Definition at line 476 of file defBF547.h.

#define HMDMA1_ECINIT   0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */

Definition at line 477 of file defBF547.h.

#define HMDMA1_ECOUNT   0xffc04554 /* Handshake MDMA1 Current Edge Count Register */

Definition at line 481 of file defBF547.h.

#define HMDMA1_ECOVERFLOW   0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */

Definition at line 480 of file defBF547.h.

#define HMDMA1_ECURGENT   0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */

Definition at line 479 of file defBF547.h.

#define HOST_CONTROL   0xffc03a00 /* HOST Control Register */

Definition at line 187 of file defBF547.h.

#define HOST_EN   0x1 /* Host Enable */

Definition at line 586 of file defBF547.h.

#define HOST_END   0x2 /* Host Endianess */

Definition at line 587 of file defBF547.h.

#define HOST_MODE   0x4 /* indicates USBDRC is a host */

Definition at line 904 of file defBF547.h.

#define HOST_REQ   0x2 /* Host negotiation request */

Definition at line 903 of file defBF547.h.

#define HOST_RST   0x8 /* Host Reset */

Definition at line 589 of file defBF547.h.

#define HOST_STATUS   0xffc03a04 /* HOST Status Register */

Definition at line 188 of file defBF547.h.

#define HOST_TERM_XFER_INT   0x20 /* Host terminate current transfer interrupt status */

Definition at line 690 of file defBF547.h.

#define HOST_TERM_XFER_MASK   0x20 /* Host terminate current transfer interrupt mask */

Definition at line 678 of file defBF547.h.

#define HOST_TIMEOUT   0xffc03a08 /* HOST Acknowledge Mode Timeout Register */

Definition at line 189 of file defBF547.h.

#define HRDY_OVR   0x20 /* Host Ready Override */

Definition at line 590 of file defBF547.h.

#define HS_ENABLE   0x20 /* high Speed Enable */

Definition at line 806 of file defBF547.h.

#define HS_MODE   0x10 /* High Speed mode indicator */

Definition at line 805 of file defBF547.h.

#define HSHK   0x10 /* Host Handshake */

Definition at line 603 of file defBF547.h.

#define HSTIMEOUT   0x20 /* Host Timeout */

Definition at line 604 of file defBF547.h.

#define IMG_FORM   0x8 /* Image Data Format */

Definition at line 495 of file defBF547.h.

#define IMG_STAT   0x300 /* Image FIFO Status */

Definition at line 500 of file defBF547.h.

#define INCOMPRX_R   0x100 /* indicates that a large packet is split */

Definition at line 996 of file defBF547.h.

#define INCOMPRX_RH   0x100 /* indicates that a large packet is split host mode */

Definition at line 1005 of file defBF547.h.

#define INCOMPTX_T   0x80 /* indicates that a large packet is split */

Definition at line 972 of file defBF547.h.

#define INT_ENA   0x8 /* Interrupt enable */

Definition at line 1047 of file defBF547.h.

#define INT_MODE   0x40 /* Interrupt Mode */

Definition at line 591 of file defBF547.h.

#define IORDY_EN   0x10 /* IORDY Enable */

Definition at line 651 of file defBF547.h.

#define ISO_R   0x4000 /* enable Isochronous transfers */

Definition at line 1000 of file defBF547.h.

#define ISO_T   0x4000 /* enable Isochronous transfers */

Definition at line 976 of file defBF547.h.

#define ISO_UPDATE   0x80 /* Isochronous update */

Definition at line 808 of file defBF547.h.

#define KPAD_COL   0xff00 /* Columns Pressed */

Definition at line 633 of file defBF547.h.

#define KPAD_COLEN   0xe000 /* Column Enable Width */

Definition at line 619 of file defBF547.h.

#define KPAD_CTL   0xffc04100 /* Controls keypad module enable and disable */

Definition at line 435 of file defBF547.h.

#define KPAD_EN   0x1 /* Keypad Enable */

Definition at line 616 of file defBF547.h.

#define KPAD_IRQ   0x1 /* Keypad Interrupt Status */

Definition at line 637 of file defBF547.h.

#define KPAD_IRQMODE   0x6 /* Key Press Interrupt Enable */

Definition at line 617 of file defBF547.h.

#define KPAD_MROWCOL   0x6 /* Multiple Row/Column Keypress Status */

Definition at line 638 of file defBF547.h.

#define KPAD_MSEL   0xffc04108 /* Selects delay parameters for keypad interface sensitivity */

Definition at line 437 of file defBF547.h.

#define KPAD_PRESCALE   0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */

Definition at line 436 of file defBF547.h.

#define KPAD_PRESCALE_VAL   0x3f /* Key Prescale Value */

Definition at line 623 of file defBF547.h.

#define KPAD_PRESSED   0x8 /* Key press current status */

Definition at line 639 of file defBF547.h.

#define KPAD_ROW   0xff /* Rows Pressed */

Definition at line 632 of file defBF547.h.

#define KPAD_ROWCOL   0xffc0410c /* Captures the row and column output values of the keys pressed */

Definition at line 438 of file defBF547.h.

#define KPAD_ROWEN   0x1c00 /* Row Enable Width */

Definition at line 618 of file defBF547.h.

#define KPAD_SOFTEVAL   0xffc04114 /* Lets software force keypad interface to check for keys being pressed */

Definition at line 440 of file defBF547.h.

#define KPAD_SOFTEVAL_E   0x2 /* Software Programmable Force Evaluate */

Definition at line 643 of file defBF547.h.

#define KPAD_STAT   0xffc04110 /* Holds and clears the status of the keypad interface interrupt */

Definition at line 439 of file defBF547.h.

#define LSDEV   0x20 /* Low-speed indicator */

Definition at line 907 of file defBF547.h.

#define MAX_PACKET_SIZE_R   0x7ff /* maximum data pay load in a frame */

Definition at line 961 of file defBF547.h.

#define MAX_PACKET_SIZE_T   0x7ff /* maximum data pay load in a frame */

Definition at line 957 of file defBF547.h.

#define MODE   0x4 /* DMA Bus error */

Definition at line 1046 of file defBF547.h.

#define MULTI_DONE_INT   0x4 /* Multi-DMA transfer done interrupt status */

Definition at line 687 of file defBF547.h.

#define MULTI_DONE_MASK   0x4 /* Multi-DMA transfer done interrupt mask */

Definition at line 675 of file defBF547.h.

#define MULTI_START   0x2 /* Start Multi-DMA Op */

Definition at line 648 of file defBF547.h.

#define MULTI_TERM_INT   0x40 /* Device terminate Multi-DMA transfer interrupt status */

Definition at line 691 of file defBF547.h.

#define MULTI_TERM_MASK   0x40 /* Device terminate Multi-DMA transfer interrupt mask */

Definition at line 679 of file defBF547.h.

#define MULTI_XFER_ON   0x2 /* Multi-word DMA transfer in progress */

Definition at line 663 of file defBF547.h.

#define NAK_TIMEOUT_H   0x80 /* EP0 halted after a NAK host mode */

Definition at line 945 of file defBF547.h.

#define NAK_TIMEOUT_TH   0x80 /* NAK timeout host mode */

Definition at line 980 of file defBF547.h.

#define OUT_FORM   0x20 /* Output Data Format */

Definition at line 497 of file defBF547.h.

#define OVERRUN_R   0x4 /* TxPktRdy not set for an IN token */

Definition at line 990 of file defBF547.h.

#define OVR_A_EN   0x2 /* Overlay A Enable */

Definition at line 493 of file defBF547.h.

#define OVR_B_EN   0x4 /* Overlay B Enable */

Definition at line 494 of file defBF547.h.

#define OVR_FORM   0x10 /* Overlay Data Format */

Definition at line 496 of file defBF547.h.

#define OVR_INT_EN   0x1 /* Interrupt at End of Last Valid Overlay */

Definition at line 546 of file defBF547.h.

#define OVR_INT_STAT   0x4 /* Overlay Interrupt Status */

Definition at line 548 of file defBF547.h.

#define OVR_STAT   0xc00 /* Overlay FIFO Status */

Definition at line 501 of file defBF547.h.

#define PIO_CSTATE   0xf /* PIO mode state machine current state */

Definition at line 710 of file defBF547.h.

#define PIO_DONE_INT   0x2 /* PIO transfer done interrupt status */

Definition at line 686 of file defBF547.h.

#define PIO_DONE_MASK   0x2 /* PIO transfer done interrupt mask */

Definition at line 674 of file defBF547.h.

#define PIO_START   0x1 /* Start PIO/Reg Op */

Definition at line 647 of file defBF547.h.

#define PIO_USE_DMA   0x400 /* PIO-DMA Enable */

Definition at line 657 of file defBF547.h.

#define PIO_XFER_ON   0x1 /* PIO transfer in progress */

Definition at line 662 of file defBF547.h.

#define PIXC_AHEND   0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */

Definition at line 448 of file defBF547.h.

#define PIXC_AHSTART   0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */

Definition at line 447 of file defBF547.h.

#define PIXC_ATRANSP   0xffc0441c /* Contains the transparency ratio (set A) */

Definition at line 451 of file defBF547.h.

#define PIXC_AVEND   0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */

Definition at line 450 of file defBF547.h.

#define PIXC_AVSTART   0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */

Definition at line 449 of file defBF547.h.

#define PIXC_BHEND   0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */

Definition at line 453 of file defBF547.h.

#define PIXC_BHSTART   0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */

Definition at line 452 of file defBF547.h.

#define PIXC_BTRANSP   0xffc04430 /* Contains the transparency ratio (set B) */

Definition at line 456 of file defBF547.h.

#define PIXC_BVCON   0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */

Definition at line 460 of file defBF547.h.

#define PIXC_BVEND   0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */

Definition at line 455 of file defBF547.h.

#define PIXC_BVSTART   0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */

Definition at line 454 of file defBF547.h.

#define PIXC_CCBIAS   0xffc0444c /* Bias values for the color space conversion matrix */

Definition at line 461 of file defBF547.h.

#define PIXC_CTL   0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */

Definition at line 444 of file defBF547.h.

#define PIXC_EN   0x1 /* Pixel Compositor Enable */

Definition at line 492 of file defBF547.h.

#define PIXC_GUCON   0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */

Definition at line 459 of file defBF547.h.

#define PIXC_INTRSTAT   0xffc0443c /* Overlay interrupt configuration/status */

Definition at line 457 of file defBF547.h.

#define PIXC_LPF   0xffc04408 /* Holds the number of lines per frame of the display */

Definition at line 446 of file defBF547.h.

#define PIXC_PPL   0xffc04404 /* Holds the number of pixels per line of the display */

Definition at line 445 of file defBF547.h.

#define PIXC_RYCON   0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */

Definition at line 458 of file defBF547.h.

#define PIXC_TC   0xffc04450 /* Holds the transparent color value */

Definition at line 462 of file defBF547.h.

#define PROTOCOL_R   0xc /* transfer type */

Definition at line 1025 of file defBF547.h.

#define PROTOCOL_T   0xc /* transfer type */

Definition at line 1016 of file defBF547.h.

#define READY_PAUSE   0xff00 /* Selects ready to pause */

Definition at line 767 of file defBF547.h.

#define REQPKT_H   0x20 /* Request an IN transaction host mode */

Definition at line 943 of file defBF547.h.

#define REQPKT_RH   0x20 /* request an IN transaction host mode */

Definition at line 1003 of file defBF547.h.

#define RESET   0x8 /* Reset indicator */

Definition at line 804 of file defBF547.h.

#define RESET_OR_BABLE_B   0x4 /* Reset/babble indicator */

Definition at line 856 of file defBF547.h.

#define RESET_OR_BABLE_BE   0x4 /* Reset/babble indicator int enable */

Definition at line 867 of file defBF547.h.

#define RESUME_B   0x2 /* Resume indicator */

Definition at line 855 of file defBF547.h.

#define RESUME_BE   0x2 /* Resume indicator int enable */

Definition at line 866 of file defBF547.h.

#define RESUME_MODE   0x4 /* DMA Mode */

Definition at line 803 of file defBF547.h.

#define RX_COUNT   0x1fff /* Number of received bytes in the packet in the Rx FIFO */

Definition at line 1011 of file defBF547.h.

#define RX_POLL_INTERVAL   0xff /* polling interval for selected Rx EP */

Definition at line 1029 of file defBF547.h.

#define RXPKTRDY   0x1 /* data packet receive indicator */

Definition at line 931 of file defBF547.h.

#define RXPKTRDY_R   0x1 /* data packet in FIFO indicator */

Definition at line 988 of file defBF547.h.

#define RY_MULT4   0x40000000 /* Multiply Row by 4 */

Definition at line 556 of file defBF547.h.

#define RY_TRANS   0xff /* Transparent Color - R/Y Component */

Definition at line 580 of file defBF547.h.

#define SDH_ARGUMENT   0xffc03908 /* SDH Argument */

Definition at line 155 of file defBF547.h.

#define SDH_CFG   0xffc039c8 /* SDH Configuration */

Definition at line 174 of file defBF547.h.

#define SDH_CLK_CTL   0xffc03904 /* SDH Clock Control */

Definition at line 154 of file defBF547.h.

#define SDH_COMMAND   0xffc0390c /* SDH Command */

Definition at line 156 of file defBF547.h.

#define SDH_DATA_CNT   0xffc03930 /* SDH Data Counter */

Definition at line 165 of file defBF547.h.

#define SDH_DATA_CTL   0xffc0392c /* SDH Data Control */

Definition at line 164 of file defBF547.h.

#define SDH_DATA_LGTH   0xffc03928 /* SDH Data Length */

Definition at line 163 of file defBF547.h.

#define SDH_DATA_TIMER   0xffc03924 /* SDH Data Timer */

Definition at line 162 of file defBF547.h.

#define SDH_E_MASK   0xffc039c4 /* SDH Exception Mask */

Definition at line 173 of file defBF547.h.

#define SDH_E_STATUS   0xffc039c0 /* SDH Exception Status */

Definition at line 172 of file defBF547.h.

#define SDH_FIFO   0xffc03980 /* SDH Data FIFO */

Definition at line 171 of file defBF547.h.

#define SDH_FIFO_CNT   0xffc03948 /* SDH FIFO Counter */

Definition at line 170 of file defBF547.h.

#define SDH_MASK0   0xffc0393c /* SDH Interrupt0 Mask */

Definition at line 168 of file defBF547.h.

#define SDH_MASK1   0xffc03940 /* SDH Interrupt1 Mask */

Definition at line 169 of file defBF547.h.

#define SDH_PID0   0xffc039d0 /* SDH Peripheral Identification0 */

Definition at line 176 of file defBF547.h.

#define SDH_PID1   0xffc039d4 /* SDH Peripheral Identification1 */

Definition at line 177 of file defBF547.h.

#define SDH_PID2   0xffc039d8 /* SDH Peripheral Identification2 */

Definition at line 178 of file defBF547.h.

#define SDH_PID3   0xffc039dc /* SDH Peripheral Identification3 */

Definition at line 179 of file defBF547.h.

#define SDH_PID4   0xffc039e0 /* SDH Peripheral Identification4 */

Definition at line 180 of file defBF547.h.

#define SDH_PID5   0xffc039e4 /* SDH Peripheral Identification5 */

Definition at line 181 of file defBF547.h.

#define SDH_PID6   0xffc039e8 /* SDH Peripheral Identification6 */

Definition at line 182 of file defBF547.h.

#define SDH_PID7   0xffc039ec /* SDH Peripheral Identification7 */

Definition at line 183 of file defBF547.h.

#define SDH_PWR_CTL   0xffc03900 /* SDH Power Control */

Definition at line 153 of file defBF547.h.

#define SDH_RD_WAIT_EN   0xffc039cc /* SDH Read Wait Enable */

Definition at line 175 of file defBF547.h.

#define SDH_RESP_CMD   0xffc03910 /* SDH Response Command */

Definition at line 157 of file defBF547.h.

#define SDH_RESPONSE0   0xffc03914 /* SDH Response0 */

Definition at line 158 of file defBF547.h.

#define SDH_RESPONSE1   0xffc03918 /* SDH Response1 */

Definition at line 159 of file defBF547.h.

#define SDH_RESPONSE2   0xffc0391c /* SDH Response2 */

Definition at line 160 of file defBF547.h.

#define SDH_RESPONSE3   0xffc03920 /* SDH Response3 */

Definition at line 161 of file defBF547.h.

#define SDH_STATUS   0xffc03934 /* SDH Status */

Definition at line 166 of file defBF547.h.

#define SDH_STATUS_CLR   0xffc03938 /* SDH Status Clear */

Definition at line 167 of file defBF547.h.

#define SELECTED_ENDPOINT   0xf /* selected endpoint */

Definition at line 880 of file defBF547.h.

#define SENDSTALL   0x20 /* Send STALL handshake */

Definition at line 936 of file defBF547.h.

#define SERVICED_RXPKTRDY   0x40 /* used to clear the RxPktRdy bit */

Definition at line 937 of file defBF547.h.

#define SERVICED_SETUPEND   0x80 /* used to clear the SetupEnd bit */

Definition at line 938 of file defBF547.h.

#define SESSION   0x1 /* session indicator */

Definition at line 902 of file defBF547.h.

#define SESSION_REQ_B   0x40 /* Session Request */

Definition at line 860 of file defBF547.h.

#define SESSION_REQ_BE   0x40 /* Session Request int enable */

Definition at line 871 of file defBF547.h.

#define SETUPEND   0x10 /* Setup end */

Definition at line 935 of file defBF547.h.

#define SETUPPKT_H   0x8 /* send Setup token host mode */

Definition at line 941 of file defBF547.h.

#define SOF_B   0x8 /* Start of frame */

Definition at line 857 of file defBF547.h.

#define SOF_BE   0x8 /* Start of frame int enable */

Definition at line 868 of file defBF547.h.

#define SOFT_CONN   0x40 /* Soft connect */

Definition at line 807 of file defBF547.h.

#define SOFT_RST   0x40 /* Soft Reset */

Definition at line 653 of file defBF547.h.

#define SPI2_BAUD   0xffc02414 /* SPI2 Baud Rate Register */

Definition at line 120 of file defBF547.h.

#define SPI2_CTL   0xffc02400 /* SPI2 Control Register */

Definition at line 115 of file defBF547.h.

#define SPI2_FLG   0xffc02404 /* SPI2 Flag Register */

Definition at line 116 of file defBF547.h.

#define SPI2_RDBR   0xffc02410 /* SPI2 Receive Data Buffer Register */

Definition at line 119 of file defBF547.h.

#define SPI2_REGBASE   0xffc02400

Definition at line 114 of file defBF547.h.

#define SPI2_SHADOW   0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */

Definition at line 121 of file defBF547.h.

#define SPI2_STAT   0xffc02408 /* SPI2 Status Register */

Definition at line 117 of file defBF547.h.

#define SPI2_TDBR   0xffc0240c /* SPI2 Transmit Data Buffer Register */

Definition at line 118 of file defBF547.h.

#define SPORT0_CHNL   0xffc00834 /* SPORT0 Current Channel Register */

Definition at line 49 of file defBF547.h.

#define SPORT0_MCMC1   0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */

Definition at line 50 of file defBF547.h.

#define SPORT0_MCMC2   0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */

Definition at line 51 of file defBF547.h.

#define SPORT0_MRCS0   0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */

Definition at line 56 of file defBF547.h.

#define SPORT0_MRCS1   0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */

Definition at line 57 of file defBF547.h.

#define SPORT0_MRCS2   0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */

Definition at line 58 of file defBF547.h.

#define SPORT0_MRCS3   0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */

Definition at line 59 of file defBF547.h.

#define SPORT0_MTCS0   0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */

Definition at line 52 of file defBF547.h.

#define SPORT0_MTCS1   0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */

Definition at line 53 of file defBF547.h.

#define SPORT0_MTCS2   0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */

Definition at line 54 of file defBF547.h.

#define SPORT0_MTCS3   0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */

Definition at line 55 of file defBF547.h.

#define SPORT0_RCLKDIV   0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */

Definition at line 46 of file defBF547.h.

#define SPORT0_RCR1   0xffc00820 /* SPORT0 Receive Configuration 1 Register */

Definition at line 44 of file defBF547.h.

#define SPORT0_RCR2   0xffc00824 /* SPORT0 Receive Configuration 2 Register */

Definition at line 45 of file defBF547.h.

#define SPORT0_RFSDIV   0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */

Definition at line 47 of file defBF547.h.

#define SPORT0_RX   0xffc00818 /* SPORT0 Receive Data Register */

Definition at line 43 of file defBF547.h.

#define SPORT0_STAT   0xffc00830 /* SPORT0 Status Register */

Definition at line 48 of file defBF547.h.

#define SPORT0_TCLKDIV   0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */

Definition at line 40 of file defBF547.h.

#define SPORT0_TCR1   0xffc00800 /* SPORT0 Transmit Configuration 1 Register */

Definition at line 38 of file defBF547.h.

#define SPORT0_TCR2   0xffc00804 /* SPORT0 Transmit Configuration 2 Register */

Definition at line 39 of file defBF547.h.

#define SPORT0_TFSDIV   0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */

Definition at line 41 of file defBF547.h.

#define SPORT0_TX   0xffc00810 /* SPORT0 Transmit Data Register */

Definition at line 42 of file defBF547.h.

#define STALL_RECEIVED_H   0x4 /* STALL handshake received host mode */

Definition at line 940 of file defBF547.h.

#define STALL_RECEIVED_RH   0x40 /* Stall handshake received host mode */

Definition at line 1004 of file defBF547.h.

#define STALL_RECEIVED_TH   0x20 /* Stall handshake received host mode */

Definition at line 979 of file defBF547.h.

#define STALL_SEND_R   0x20 /* issue a Stall handshake */

Definition at line 993 of file defBF547.h.

#define STALL_SEND_T   0x10 /* issue a Stall handshake */

Definition at line 969 of file defBF547.h.

#define STALL_SENT   0x4 /* STALL handshake sent */

Definition at line 933 of file defBF547.h.

#define STALL_SENT_R   0x40 /* Stall handshake transmitted */

Definition at line 994 of file defBF547.h.

#define STALL_SENT_T   0x20 /* Stall handshake transmitted */

Definition at line 970 of file defBF547.h.

#define STATUSPKT_H   0x40 /* Status stage transaction host mode */

Definition at line 944 of file defBF547.h.

#define SUSPEND_B   0x1 /* Suspend indicator */

Definition at line 854 of file defBF547.h.

#define SUSPEND_BE   0x1 /* Suspend indicator int enable */

Definition at line 865 of file defBF547.h.

#define SUSPEND_MODE   0x2 /* Suspend Mode indicator */

Definition at line 802 of file defBF547.h.

#define T1_REG   0xf /* Time from address valid to DIOR/DIOW */

Definition at line 726 of file defBF547.h.

#define T2_REG   0xff /* End of cycle time for register access transfers */

Definition at line 721 of file defBF547.h.

#define T2_REG_PIO   0xff0 /* DIOR/DIOW pulsewidth */

Definition at line 727 of file defBF547.h.

#define T4_REG   0xf000 /* DIOW data hold */

Definition at line 728 of file defBF547.h.

#define TACK   0xff /* Selects setup and hold times for TACK */

Definition at line 751 of file defBF547.h.

#define TARGET_EP_NO_R   0xf /* EP number */

Definition at line 1024 of file defBF547.h.

#define TARGET_EP_NO_T   0xf /* EP number */

Definition at line 1015 of file defBF547.h.

#define TC_EN   0x80 /* Transparent Color Enable */

Definition at line 499 of file defBF547.h.

#define TCYC_TDVS   0xff00 /* Selects cycle time - TDVS time */

Definition at line 757 of file defBF547.h.

#define TD   0xff /* DIOR/DIOW asserted pulsewidth */

Definition at line 736 of file defBF547.h.

#define TDVS   0xff /* Selects data valid setup time */

Definition at line 756 of file defBF547.h.

#define TENV   0xff00 /* Selects envelope time */

Definition at line 752 of file defBF547.h.

#define TEOC   0xff00 /* Selects end of cycle for DMA */

Definition at line 747 of file defBF547.h.

#define TEOC_REG   0xff00 /* Selects DIOR/DIOW pulsewidth */

Definition at line 722 of file defBF547.h.

#define TEOC_REG_PIO   0xff /* End of cycle time for PIO access transfers. */

Definition at line 732 of file defBF547.h.

#define TFRCNT_RST   0x100 /* Trans Count Reset */

Definition at line 655 of file defBF547.h.

#define TH   0xff /* Selects DIOW data hold */

Definition at line 746 of file defBF547.h.

#define TIMDIS10   0x4 /* Timer 10 Disable */

Definition at line 779 of file defBF547.h.

#define TIMDIS8   0x1 /* Timer 8 Disable */

Definition at line 777 of file defBF547.h.

#define TIMDIS9   0x2 /* Timer 9 Disable */

Definition at line 778 of file defBF547.h.

#define TIMEN10   0x4 /* Timer 10 Enable */

Definition at line 773 of file defBF547.h.

#define TIMEN8   0x1 /* Timer 8 Enable */

Definition at line 771 of file defBF547.h.

#define TIMEN9   0x2 /* Timer 9 Enable */

Definition at line 772 of file defBF547.h.

#define TIMER10_CONFIG   0xffc00620 /* Timer 10 Configuration Register */

Definition at line 25 of file defBF547.h.

#define TIMER10_COUNTER   0xffc00624 /* Timer 10 Counter Register */

Definition at line 26 of file defBF547.h.

#define TIMER10_PERIOD   0xffc00628 /* Timer 10 Period Register */

Definition at line 27 of file defBF547.h.

#define TIMER10_WIDTH   0xffc0062c /* Timer 10 Width Register */

Definition at line 28 of file defBF547.h.

#define TIMER8_CONFIG   0xffc00600 /* Timer 8 Configuration Register */

Definition at line 17 of file defBF547.h.

#define TIMER8_COUNTER   0xffc00604 /* Timer 8 Counter Register */

Definition at line 18 of file defBF547.h.

#define TIMER8_PERIOD   0xffc00608 /* Timer 8 Period Register */

Definition at line 19 of file defBF547.h.

#define TIMER8_WIDTH   0xffc0060c /* Timer 8 Width Register */

Definition at line 20 of file defBF547.h.

#define TIMER9_CONFIG   0xffc00610 /* Timer 9 Configuration Register */

Definition at line 21 of file defBF547.h.

#define TIMER9_COUNTER   0xffc00614 /* Timer 9 Counter Register */

Definition at line 22 of file defBF547.h.

#define TIMER9_PERIOD   0xffc00618 /* Timer 9 Period Register */

Definition at line 23 of file defBF547.h.

#define TIMER9_WIDTH   0xffc0061c /* Timer 9 Width Register */

Definition at line 24 of file defBF547.h.

#define TIMER_DISABLE1   0xffc00644 /* Timer Group of 3 Disable Register */

Definition at line 33 of file defBF547.h.

#define TIMER_ENABLE1   0xffc00640 /* Timer Group of 3 Enable Register */

Definition at line 32 of file defBF547.h.

#define TIMER_STATUS1   0xffc00648 /* Timer Group of 3 Status Register */

Definition at line 34 of file defBF547.h.

#define TIMIL10   0x4 /* Timer 10 Interrupt */

Definition at line 785 of file defBF547.h.

#define TIMIL8   0x1 /* Timer 8 Interrupt */

Definition at line 783 of file defBF547.h.

#define TIMIL9   0x2 /* Timer 9 Interrupt */

Definition at line 784 of file defBF547.h.

#define TKR   0xff00 /* Selects DIOR negated pulsewidth */

Definition at line 742 of file defBF547.h.

#define TKW   0xff /* Selects DIOW negated pulsewidth */

Definition at line 741 of file defBF547.h.

#define TM   0xff00 /* Time from address valid to DIOR/DIOW */

Definition at line 737 of file defBF547.h.

#define TMLI   0xff00 /* Selects interlock time */

Definition at line 762 of file defBF547.h.

#define TOVF_ERR10   0x40 /* Timer 10 Counter Overflow */

Definition at line 788 of file defBF547.h.

#define TOVF_ERR8   0x10 /* Timer 8 Counter Overflow */

Definition at line 786 of file defBF547.h.

#define TOVF_ERR9   0x20 /* Timer 9 Counter Overflow */

Definition at line 787 of file defBF547.h.

#define TRUN10   0x4000 /* Timer 10 Slave Enable Status */

Definition at line 791 of file defBF547.h.

#define TRUN8   0x1000 /* Timer 8 Slave Enable Status */

Definition at line 789 of file defBF547.h.

#define TRUN9   0x2000 /* Timer 9 Slave Enable Status */

Definition at line 790 of file defBF547.h.

#define TSS   0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */

Definition at line 761 of file defBF547.h.

#define TWI1_CLKDIV   0xffc02200 /* Clock Divider Register */

Definition at line 95 of file defBF547.h.

#define TWI1_CONTROL   0xffc02204 /* TWI Control Register */

Definition at line 96 of file defBF547.h.

#define TWI1_FIFO_CTL   0xffc02228 /* TWI FIFO Control Register */

Definition at line 105 of file defBF547.h.

#define TWI1_FIFO_STAT   0xffc0222c /* TWI FIFO Status Register */

Definition at line 106 of file defBF547.h.

#define TWI1_INT_MASK   0xffc02224 /* TWI Interrupt Mask Register */

Definition at line 104 of file defBF547.h.

#define TWI1_INT_STAT   0xffc02220 /* TWI Interrupt Status Register */

Definition at line 103 of file defBF547.h.

#define TWI1_MASTER_ADDR   0xffc0221c /* TWI Master Mode Address Register */

Definition at line 102 of file defBF547.h.

#define TWI1_MASTER_CTL   0xffc02214 /* TWI Master Mode Control Register */

Definition at line 100 of file defBF547.h.

#define TWI1_MASTER_STAT   0xffc02218 /* TWI Master Mode Status Register */

Definition at line 101 of file defBF547.h.

#define TWI1_RCV_DATA16   0xffc0228c /* TWI FIFO Receive Data Double Byte Register */

Definition at line 110 of file defBF547.h.

#define TWI1_RCV_DATA8   0xffc02288 /* TWI FIFO Receive Data Single Byte Register */

Definition at line 109 of file defBF547.h.

#define TWI1_REGBASE   0xffc02200

Definition at line 94 of file defBF547.h.

#define TWI1_SLAVE_ADDR   0xffc02210 /* TWI Slave Mode Address Register */

Definition at line 99 of file defBF547.h.

#define TWI1_SLAVE_CTL   0xffc02208 /* TWI Slave Mode Control Register */

Definition at line 97 of file defBF547.h.

#define TWI1_SLAVE_STAT   0xffc0220c /* TWI Slave Mode Status Register */

Definition at line 98 of file defBF547.h.

#define TWI1_XMT_DATA16   0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */

Definition at line 108 of file defBF547.h.

#define TWI1_XMT_DATA8   0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */

Definition at line 107 of file defBF547.h.

#define TX_COUNT   0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */

Definition at line 984 of file defBF547.h.

#define TX_POLL_INTERVAL   0xff /* polling interval for selected Tx EP */

Definition at line 1020 of file defBF547.h.

#define TXPKTRDY   0x2 /* data packet in FIFO indicator */

Definition at line 932 of file defBF547.h.

#define TXPKTRDY_T   0x1 /* data packet in FIFO indicator */

Definition at line 965 of file defBF547.h.

#define TZAH   0xff /* Selects minimum delay required for output */

Definition at line 766 of file defBF547.h.

#define UART2_DLH   0xffc02104 /* Divisor Latch High Byte */

Definition at line 81 of file defBF547.h.

#define UART2_DLL   0xffc02100 /* Divisor Latch Low Byte */

Definition at line 80 of file defBF547.h.

#define UART2_GCTL   0xffc02108 /* Global Control Register */

Definition at line 82 of file defBF547.h.

#define UART2_IER_CLEAR   0xffc02124 /* Interrupt Enable Register Clear */

Definition at line 89 of file defBF547.h.

#define UART2_IER_SET   0xffc02120 /* Interrupt Enable Register Set */

Definition at line 88 of file defBF547.h.

#define UART2_LCR   0xffc0210c /* Line Control Register */

Definition at line 83 of file defBF547.h.

#define UART2_LSR   0xffc02114 /* Line Status Register */

Definition at line 85 of file defBF547.h.

#define UART2_MCR   0xffc02110 /* Modem Control Register */

Definition at line 84 of file defBF547.h.

#define UART2_MSR   0xffc02118 /* Modem Status Register */

Definition at line 86 of file defBF547.h.

#define UART2_RBR   0xffc0212c /* Receive Buffer Register */

Definition at line 90 of file defBF547.h.

#define UART2_SCR   0xffc0211c /* Scratch Register */

Definition at line 87 of file defBF547.h.

#define UDMAIN_CSTATE   0xf00 /* Ultra DMA-In mode state machine current state */

Definition at line 712 of file defBF547.h.

#define UDMAIN_DONE_INT   0x8 /* Ultra-DMA in transfer done interrupt status */

Definition at line 688 of file defBF547.h.

#define UDMAIN_DONE_MASK   0x8 /* Ultra-DMA in transfer done interrupt mask */

Definition at line 676 of file defBF547.h.

#define UDMAIN_FIFO_THRS   0xf000 /* Ultra DMA-IN FIFO Threshold */

Definition at line 658 of file defBF547.h.

#define UDMAIN_TERM_INT   0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */

Definition at line 692 of file defBF547.h.

#define UDMAIN_TERM_MASK   0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */

Definition at line 680 of file defBF547.h.

#define UDMAOUT_CSTATE   0xf000 /* ATAPI IORDY line status */

Definition at line 713 of file defBF547.h.

#define UDMAOUT_DONE_INT   0x10 /* Ultra-DMA out transfer done interrupt status */

Definition at line 689 of file defBF547.h.

#define UDMAOUT_DONE_MASK   0x10 /* Ultra-DMA out transfer done interrupt mask */

Definition at line 677 of file defBF547.h.

#define UDMAOUT_TERM_INT   0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */

Definition at line 693 of file defBF547.h.

#define UDMAOUT_TERM_MASK   0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */

Definition at line 681 of file defBF547.h.

#define UDS_MOD   0x40 /* Resampling Mode */

Definition at line 498 of file defBF547.h.

#define ULTRA_IN_FL   0xf0 /* Ultra DMA Input FIFO Level */

Definition at line 665 of file defBF547.h.

#define ULTRA_START   0x4 /* Start Ultra-DMA Op */

Definition at line 649 of file defBF547.h.

#define ULTRA_XFER_ON   0x4 /* Ultra DMA transfer in progress */

Definition at line 664 of file defBF547.h.

#define UNDERRUN_T   0x4 /* TxPktRdy not set for an IN token */

Definition at line 967 of file defBF547.h.

#define USB_APHY_CALIB   0xffc03de4 /* Register used to set some calibration values */

Definition at line 254 of file defBF547.h.

#define USB_APHY_CNTRL   0xffc03de0 /* Register that increases visibility of Analog PHY */

Definition at line 250 of file defBF547.h.

#define USB_APHY_CNTRL2   0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */

Definition at line 255 of file defBF547.h.

#define USB_COUNT0   0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */

Definition at line 214 of file defBF547.h.

#define USB_CSR0   0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */

Definition at line 210 of file defBF547.h.

#define USB_DMA0ADDRHIGH   0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */

Definition at line 373 of file defBF547.h.

#define USB_DMA0ADDRLOW   0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */

Definition at line 372 of file defBF547.h.

#define USB_DMA0CONTROL   0xffc04004 /* DMA master channel 0 configuration */

Definition at line 371 of file defBF547.h.

#define USB_DMA0COUNTHIGH   0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */

Definition at line 375 of file defBF547.h.

#define USB_DMA0COUNTLOW   0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */

Definition at line 374 of file defBF547.h.

#define USB_DMA1ADDRHIGH   0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */

Definition at line 381 of file defBF547.h.

#define USB_DMA1ADDRLOW   0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */

Definition at line 380 of file defBF547.h.

#define USB_DMA1CONTROL   0xffc04024 /* DMA master channel 1 configuration */

Definition at line 379 of file defBF547.h.

#define USB_DMA1COUNTHIGH   0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */

Definition at line 383 of file defBF547.h.

#define USB_DMA1COUNTLOW   0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */

Definition at line 382 of file defBF547.h.

#define USB_DMA2ADDRHIGH   0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */

Definition at line 389 of file defBF547.h.

#define USB_DMA2ADDRLOW   0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */

Definition at line 388 of file defBF547.h.

#define USB_DMA2CONTROL   0xffc04044 /* DMA master channel 2 configuration */

Definition at line 387 of file defBF547.h.

#define USB_DMA2COUNTHIGH   0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */

Definition at line 391 of file defBF547.h.

#define USB_DMA2COUNTLOW   0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */

Definition at line 390 of file defBF547.h.

#define USB_DMA3ADDRHIGH   0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */

Definition at line 397 of file defBF547.h.

#define USB_DMA3ADDRLOW   0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */

Definition at line 396 of file defBF547.h.

#define USB_DMA3CONTROL   0xffc04064 /* DMA master channel 3 configuration */

Definition at line 395 of file defBF547.h.

#define USB_DMA3COUNTHIGH   0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */

Definition at line 399 of file defBF547.h.

#define USB_DMA3COUNTLOW   0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */

Definition at line 398 of file defBF547.h.

#define USB_DMA4ADDRHIGH   0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */

Definition at line 405 of file defBF547.h.

#define USB_DMA4ADDRLOW   0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */

Definition at line 404 of file defBF547.h.

#define USB_DMA4CONTROL   0xffc04084 /* DMA master channel 4 configuration */

Definition at line 403 of file defBF547.h.

#define USB_DMA4COUNTHIGH   0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */

Definition at line 407 of file defBF547.h.

#define USB_DMA4COUNTLOW   0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */

Definition at line 406 of file defBF547.h.

#define USB_DMA5ADDRHIGH   0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */

Definition at line 413 of file defBF547.h.

#define USB_DMA5ADDRLOW   0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */

Definition at line 412 of file defBF547.h.

#define USB_DMA5CONTROL   0xffc040a4 /* DMA master channel 5 configuration */

Definition at line 411 of file defBF547.h.

#define USB_DMA5COUNTHIGH   0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */

Definition at line 415 of file defBF547.h.

#define USB_DMA5COUNTLOW   0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */

Definition at line 414 of file defBF547.h.

#define USB_DMA6ADDRHIGH   0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */

Definition at line 421 of file defBF547.h.

#define USB_DMA6ADDRLOW   0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */

Definition at line 420 of file defBF547.h.

#define USB_DMA6CONTROL   0xffc040c4 /* DMA master channel 6 configuration */

Definition at line 419 of file defBF547.h.

#define USB_DMA6COUNTHIGH   0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */

Definition at line 423 of file defBF547.h.

#define USB_DMA6COUNTLOW   0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */

Definition at line 422 of file defBF547.h.

#define USB_DMA7ADDRHIGH   0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */

Definition at line 429 of file defBF547.h.

#define USB_DMA7ADDRLOW   0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */

Definition at line 428 of file defBF547.h.

#define USB_DMA7CONTROL   0xffc040e4 /* DMA master channel 7 configuration */

Definition at line 427 of file defBF547.h.

#define USB_DMA7COUNTHIGH   0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */

Definition at line 431 of file defBF547.h.

#define USB_DMA7COUNTLOW   0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */

Definition at line 430 of file defBF547.h.

#define USB_DMA_INTERRUPT   0xffc04000 /* Indicates pending interrupts for the DMA channels */

Definition at line 367 of file defBF547.h.

#define USB_EP0_FIFO   0xffc03c80 /* Endpoint 0 FIFO */

Definition at line 225 of file defBF547.h.

#define USB_EP1_FIFO   0xffc03c88 /* Endpoint 1 FIFO */

Definition at line 226 of file defBF547.h.

#define USB_EP2_FIFO   0xffc03c90 /* Endpoint 2 FIFO */

Definition at line 227 of file defBF547.h.

#define USB_EP3_FIFO   0xffc03c98 /* Endpoint 3 FIFO */

Definition at line 228 of file defBF547.h.

#define USB_EP4_FIFO   0xffc03ca0 /* Endpoint 4 FIFO */

Definition at line 229 of file defBF547.h.

#define USB_EP5_FIFO   0xffc03ca8 /* Endpoint 5 FIFO */

Definition at line 230 of file defBF547.h.

#define USB_EP6_FIFO   0xffc03cb0 /* Endpoint 6 FIFO */

Definition at line 231 of file defBF547.h.

#define USB_EP7_FIFO   0xffc03cb8 /* Endpoint 7 FIFO */

Definition at line 232 of file defBF547.h.

#define USB_EP_NI0_RXCOUNT   0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */

Definition at line 269 of file defBF547.h.

#define USB_EP_NI0_RXCSR   0xffc03e0c /* Control Status register for Host Rx endpoint0 */

Definition at line 268 of file defBF547.h.

#define USB_EP_NI0_RXINTERVAL   0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */

Definition at line 273 of file defBF547.h.

#define USB_EP_NI0_RXMAXP   0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */

Definition at line 267 of file defBF547.h.

#define USB_EP_NI0_RXTYPE   0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */

Definition at line 272 of file defBF547.h.

#define USB_EP_NI0_TXCOUNT   0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */

Definition at line 274 of file defBF547.h.

#define USB_EP_NI0_TXCSR   0xffc03e04 /* Control Status register for endpoint 0 */

Definition at line 266 of file defBF547.h.

#define USB_EP_NI0_TXINTERVAL   0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */

Definition at line 271 of file defBF547.h.

#define USB_EP_NI0_TXMAXP   0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */

Definition at line 265 of file defBF547.h.

#define USB_EP_NI0_TXTYPE   0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */

Definition at line 270 of file defBF547.h.

#define USB_EP_NI1_RXCOUNT   0xffc03e50 /* Number of bytes received in endpoint1 FIFO */

Definition at line 282 of file defBF547.h.

#define USB_EP_NI1_RXCSR   0xffc03e4c /* Control Status register for Host Rx endpoint1 */

Definition at line 281 of file defBF547.h.

#define USB_EP_NI1_RXINTERVAL   0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */

Definition at line 286 of file defBF547.h.

#define USB_EP_NI1_RXMAXP   0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */

Definition at line 280 of file defBF547.h.

#define USB_EP_NI1_RXTYPE   0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */

Definition at line 285 of file defBF547.h.

#define USB_EP_NI1_TXCOUNT   0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */

Definition at line 287 of file defBF547.h.

#define USB_EP_NI1_TXCSR   0xffc03e44 /* Control Status register for endpoint1 */

Definition at line 279 of file defBF547.h.

#define USB_EP_NI1_TXINTERVAL   0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */

Definition at line 284 of file defBF547.h.

#define USB_EP_NI1_TXMAXP   0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */

Definition at line 278 of file defBF547.h.

#define USB_EP_NI1_TXTYPE   0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */

Definition at line 283 of file defBF547.h.

#define USB_EP_NI2_RXCOUNT   0xffc03e90 /* Number of bytes received in endpoint2 FIFO */

Definition at line 295 of file defBF547.h.

#define USB_EP_NI2_RXCSR   0xffc03e8c /* Control Status register for Host Rx endpoint2 */

Definition at line 294 of file defBF547.h.

#define USB_EP_NI2_RXINTERVAL   0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */

Definition at line 299 of file defBF547.h.

#define USB_EP_NI2_RXMAXP   0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */

Definition at line 293 of file defBF547.h.

#define USB_EP_NI2_RXTYPE   0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */

Definition at line 298 of file defBF547.h.

#define USB_EP_NI2_TXCOUNT   0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */

Definition at line 300 of file defBF547.h.

#define USB_EP_NI2_TXCSR   0xffc03e84 /* Control Status register for endpoint2 */

Definition at line 292 of file defBF547.h.

#define USB_EP_NI2_TXINTERVAL   0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */

Definition at line 297 of file defBF547.h.

#define USB_EP_NI2_TXMAXP   0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */

Definition at line 291 of file defBF547.h.

#define USB_EP_NI2_TXTYPE   0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */

Definition at line 296 of file defBF547.h.

#define USB_EP_NI3_RXCOUNT   0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */

Definition at line 308 of file defBF547.h.

#define USB_EP_NI3_RXCSR   0xffc03ecc /* Control Status register for Host Rx endpoint3 */

Definition at line 307 of file defBF547.h.

#define USB_EP_NI3_RXINTERVAL   0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */

Definition at line 312 of file defBF547.h.

#define USB_EP_NI3_RXMAXP   0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */

Definition at line 306 of file defBF547.h.

#define USB_EP_NI3_RXTYPE   0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */

Definition at line 311 of file defBF547.h.

#define USB_EP_NI3_TXCOUNT   0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */

Definition at line 313 of file defBF547.h.

#define USB_EP_NI3_TXCSR   0xffc03ec4 /* Control Status register for endpoint3 */

Definition at line 305 of file defBF547.h.

#define USB_EP_NI3_TXINTERVAL   0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */

Definition at line 310 of file defBF547.h.

#define USB_EP_NI3_TXMAXP   0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */

Definition at line 304 of file defBF547.h.

#define USB_EP_NI3_TXTYPE   0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */

Definition at line 309 of file defBF547.h.

#define USB_EP_NI4_RXCOUNT   0xffc03f10 /* Number of bytes received in endpoint4 FIFO */

Definition at line 321 of file defBF547.h.

#define USB_EP_NI4_RXCSR   0xffc03f0c /* Control Status register for Host Rx endpoint4 */

Definition at line 320 of file defBF547.h.

#define USB_EP_NI4_RXINTERVAL   0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */

Definition at line 325 of file defBF547.h.

#define USB_EP_NI4_RXMAXP   0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */

Definition at line 319 of file defBF547.h.

#define USB_EP_NI4_RXTYPE   0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */

Definition at line 324 of file defBF547.h.

#define USB_EP_NI4_TXCOUNT   0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */

Definition at line 326 of file defBF547.h.

#define USB_EP_NI4_TXCSR   0xffc03f04 /* Control Status register for endpoint4 */

Definition at line 318 of file defBF547.h.

#define USB_EP_NI4_TXINTERVAL   0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */

Definition at line 323 of file defBF547.h.

#define USB_EP_NI4_TXMAXP   0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */

Definition at line 317 of file defBF547.h.

#define USB_EP_NI4_TXTYPE   0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */

Definition at line 322 of file defBF547.h.

#define USB_EP_NI5_RXCOUNT   0xffc03f50 /* Number of bytes received in endpoint5 FIFO */

Definition at line 334 of file defBF547.h.

#define USB_EP_NI5_RXCSR   0xffc03f4c /* Control Status register for Host Rx endpoint5 */

Definition at line 333 of file defBF547.h.

#define USB_EP_NI5_RXINTERVAL   0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */

Definition at line 338 of file defBF547.h.

#define USB_EP_NI5_RXMAXP   0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */

Definition at line 332 of file defBF547.h.

#define USB_EP_NI5_RXTYPE   0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */

Definition at line 337 of file defBF547.h.

#define USB_EP_NI5_TXCOUNT   0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */

Definition at line 339 of file defBF547.h.

#define USB_EP_NI5_TXCSR   0xffc03f44 /* Control Status register for endpoint5 */

Definition at line 331 of file defBF547.h.

#define USB_EP_NI5_TXINTERVAL   0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */

Definition at line 336 of file defBF547.h.

#define USB_EP_NI5_TXMAXP   0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */

Definition at line 330 of file defBF547.h.

#define USB_EP_NI5_TXTYPE   0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */

Definition at line 335 of file defBF547.h.

#define USB_EP_NI6_RXCOUNT   0xffc03f90 /* Number of bytes received in endpoint6 FIFO */

Definition at line 347 of file defBF547.h.

#define USB_EP_NI6_RXCSR   0xffc03f8c /* Control Status register for Host Rx endpoint6 */

Definition at line 346 of file defBF547.h.

#define USB_EP_NI6_RXINTERVAL   0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */

Definition at line 351 of file defBF547.h.

#define USB_EP_NI6_RXMAXP   0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */

Definition at line 345 of file defBF547.h.

#define USB_EP_NI6_RXTYPE   0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */

Definition at line 350 of file defBF547.h.

#define USB_EP_NI6_TXCOUNT   0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */

Definition at line 352 of file defBF547.h.

#define USB_EP_NI6_TXCSR   0xffc03f84 /* Control Status register for endpoint6 */

Definition at line 344 of file defBF547.h.

#define USB_EP_NI6_TXINTERVAL   0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */

Definition at line 349 of file defBF547.h.

#define USB_EP_NI6_TXMAXP   0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */

Definition at line 343 of file defBF547.h.

#define USB_EP_NI6_TXTYPE   0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */

Definition at line 348 of file defBF547.h.

#define USB_EP_NI7_RXCOUNT   0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */

Definition at line 360 of file defBF547.h.

#define USB_EP_NI7_RXCSR   0xffc03fcc /* Control Status register for Host Rx endpoint7 */

Definition at line 359 of file defBF547.h.

#define USB_EP_NI7_RXINTERVAL   0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */

Definition at line 364 of file defBF547.h.

#define USB_EP_NI7_RXMAXP   0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */

Definition at line 358 of file defBF547.h.

#define USB_EP_NI7_RXTYPE   0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */

Definition at line 363 of file defBF547.h.

#define USB_EP_NI7_TXCOUNT   0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */

Definition at line 365 of file defBF547.h.

#define USB_EP_NI7_TXCSR   0xffc03fc4 /* Control Status register for endpoint7 */

Definition at line 357 of file defBF547.h.

#define USB_EP_NI7_TXINTERVAL   0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */

Definition at line 362 of file defBF547.h.

#define USB_EP_NI7_TXMAXP   0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */

Definition at line 356 of file defBF547.h.

#define USB_EP_NI7_TXTYPE   0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */

Definition at line 361 of file defBF547.h.

#define USB_FADDR   0xffc03c00 /* Function address register */

Definition at line 193 of file defBF547.h.

#define USB_FRAME   0xffc03c20 /* USB frame number */

Definition at line 201 of file defBF547.h.

#define USB_FS_EOF1   0xffc03d54 /* Time buffer for Full-Speed transactions */

Definition at line 245 of file defBF547.h.

#define USB_GLOBAL_CTL   0xffc03c30 /* Global Clock Control for the core */

Definition at line 205 of file defBF547.h.

#define USB_GLOBINTR   0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */

Definition at line 204 of file defBF547.h.

#define USB_HS_EOF1   0xffc03d50 /* Time buffer for High-Speed transactions */

Definition at line 244 of file defBF547.h.

#define USB_INDEX   0xffc03c24 /* Index register for selecting the indexed endpoint registers */

Definition at line 202 of file defBF547.h.

#define USB_INTRRX   0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */

Definition at line 196 of file defBF547.h.

#define USB_INTRRXE   0xffc03c14 /* Interrupt enable register for IntrRx */

Definition at line 198 of file defBF547.h.

#define USB_INTRTX   0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */

Definition at line 195 of file defBF547.h.

#define USB_INTRTXE   0xffc03c10 /* Interrupt enable register for IntrTx */

Definition at line 197 of file defBF547.h.

#define USB_INTRUSB   0xffc03c18 /* Interrupt register for common USB interrupts */

Definition at line 199 of file defBF547.h.

#define USB_INTRUSBE   0xffc03c1c /* Interrupt enable register for IntrUSB */

Definition at line 200 of file defBF547.h.

#define USB_LINKINFO   0xffc03d48 /* Enables programming of some PHY-side delays */

Definition at line 242 of file defBF547.h.

#define USB_LS_EOF1   0xffc03d58 /* Time buffer for Low-Speed transactions */

Definition at line 246 of file defBF547.h.

#define USB_NAKLIMIT0   0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */

Definition at line 217 of file defBF547.h.

#define USB_OTG_DEV_CTL   0xffc03d00 /* OTG Device Control Register */

Definition at line 236 of file defBF547.h.

#define USB_OTG_VBUS_IRQ   0xffc03d04 /* OTG VBUS Control Interrupts */

Definition at line 237 of file defBF547.h.

#define USB_OTG_VBUS_MASK   0xffc03d08 /* VBUS Control Interrupt Enable */

Definition at line 238 of file defBF547.h.

#define USB_PHY_TEST   0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */

Definition at line 259 of file defBF547.h.

#define USB_PLLOSC_CTRL   0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */

Definition at line 260 of file defBF547.h.

#define USB_POWER   0xffc03c04 /* Power management register */

Definition at line 194 of file defBF547.h.

#define USB_RX_MAX_PACKET   0xffc03c48 /* Maximum packet size for Host Rx endpoint */

Definition at line 212 of file defBF547.h.

#define USB_RXCOUNT   0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */

Definition at line 215 of file defBF547.h.

#define USB_RXCSR   0xffc03c4c /* Control Status register for Host Rx endpoint */

Definition at line 213 of file defBF547.h.

#define USB_RXINTERVAL   0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */

Definition at line 220 of file defBF547.h.

#define USB_RXTYPE   0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */

Definition at line 219 of file defBF547.h.

#define USB_SRP_CLKDIV   0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */

Definition at line 261 of file defBF547.h.

#define USB_TESTMODE   0xffc03c28 /* Enabled USB 20 test modes */

Definition at line 203 of file defBF547.h.

#define USB_TX_MAX_PACKET   0xffc03c40 /* Maximum packet size for Host Tx endpoint */

Definition at line 209 of file defBF547.h.

#define USB_TXCOUNT   0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */

Definition at line 221 of file defBF547.h.

#define USB_TXCSR   0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */

Definition at line 211 of file defBF547.h.

#define USB_TXINTERVAL   0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */

Definition at line 218 of file defBF547.h.

#define USB_TXTYPE   0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */

Definition at line 216 of file defBF547.h.

#define USB_VPLEN   0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */

Definition at line 243 of file defBF547.h.

#define VBUS0   0x8 /* Vbus level indicator[0] */

Definition at line 905 of file defBF547.h.

#define VBUS1   0x10 /* Vbus level indicator[1] */

Definition at line 906 of file defBF547.h.

#define VBUS_ERROR_B   0x80 /* Vbus threshold indicator */

Definition at line 861 of file defBF547.h.

#define VBUS_ERROR_BE   0x80 /* Vbus threshold indicator int enable */

Definition at line 872 of file defBF547.h.

#define WM_LVL   0x3000 /* FIFO Watermark Level */

Definition at line 502 of file defBF547.h.

#define XFER_DIR   0x8 /* Transfer Direction */

Definition at line 650 of file defBF547.h.