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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */ |
| #define | MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */ |
| #define | MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */ |
| #define | MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */ |
| #define | MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */ |
| #define | MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */ |
| #define | MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */ |
| #define | MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */ |
| #define | MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */ |
| #define | MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */ |
| #define | MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */ |
| #define | MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */ |
| #define | MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */ |
| #define | MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */ |
| #define | MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */ |
| #define | MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */ |
| #define | MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */ |
| #define | MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */ |
| #define | MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */ |
| #define | MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */ |
| #define | MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */ |
| #define | MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */ |
| #define | MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */ |
| #define | MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */ |
| #define | MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */ |
| #define | MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */ |
| #define | MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */ |
| #define | MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */ |
| #define | MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */ |
| #define | MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ |
| #define | MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */ |
| #define | MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ |
| #define | MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ |
| #define | MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ |
| #define | MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */ |
| #define | MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ |
| #define | MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ |
| #define | MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */ |
| #define | MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */ |
| #define | MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */ |
| #define | MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */ |
| #define | MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */ |
| #define | MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */ |
| #define | MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */ |
| #define | MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */ |
| #define | MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */ |
| #define | MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */ |
| #define | MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */ |
| #define | MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */ |
| #define | MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */ |
| #define | MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ |
| #define | MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */ |
| #define | MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */ |
| #define | MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */ |
| #define | MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */ |
| #define | MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ |
| #define | MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */ |
| #define | MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */ |
| #define | MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */ |
| #define | MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */ |
| #define | MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */ |
| #define | MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */ |
| #define | MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */ |
| #define | MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */ |
| #define | MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */ |
| #define | MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */ |
| #define | MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */ |
| #define | MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */ |
| #define | MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */ |
| #define | MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */ |
| #define | MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */ |
| #define | MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */ |
| #define | MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */ |
| #define | MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */ |
| #define | MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */ |
| #define | MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */ |
| #define | MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */ |
| #define | MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */ |
| #define | MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */ |
| #define | MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */ |
| #define | MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */ |
| #define | MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */ |
| #define | MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */ |
| #define | MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */ |
| #define | MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */ |
| #define | MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */ |
| #define | MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */ |
| #define | MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */ |
| #define | MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */ |
| #define | MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */ |
| #define | MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */ |
| #define | MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */ |
| #define | MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */ |
| #define | MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */ |
| #define | MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */ |
| #define | MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */ |
| #define | MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */ |
| #define | MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */ |
| #define | MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */ |
| #define | MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */ |
| #define | MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */ |
| #define | MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */ |
| #define | MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */ |
| #define | MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */ |
| #define | MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */ |
| #define | MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */ |
| #define | MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */ |
| #define | MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */ |
| #define | MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */ |
| #define | MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */ |
| #define | MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */ |
| #define | MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ |
| #define | MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */ |
| #define | MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */ |
| #define | MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ |
| #define | MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ |
| #define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */ |
Definition at line 31 of file defBF549.h.
| #define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */ |
Definition at line 35 of file defBF549.h.
| #define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */ |
Definition at line 36 of file defBF549.h.
| #define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */ |
Definition at line 45 of file defBF549.h.
| #define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */ |
Definition at line 46 of file defBF549.h.
| #define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */ |
Definition at line 47 of file defBF549.h.
| #define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */ |
Definition at line 48 of file defBF549.h.
| #define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */ |
Definition at line 49 of file defBF549.h.
| #define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */ |
Definition at line 37 of file defBF549.h.
| #define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */ |
Definition at line 38 of file defBF549.h.
| #define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */ |
Definition at line 39 of file defBF549.h.
| #define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */ |
Definition at line 40 of file defBF549.h.
| #define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */ |
Definition at line 41 of file defBF549.h.
| #define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */ |
Definition at line 42 of file defBF549.h.
| #define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */ |
Definition at line 43 of file defBF549.h.
| #define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */ |
Definition at line 44 of file defBF549.h.
| #define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */ |
Definition at line 128 of file defBF549.h.
| #define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */ |
Definition at line 130 of file defBF549.h.
| #define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */ |
Definition at line 129 of file defBF549.h.
| #define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */ |
Definition at line 132 of file defBF549.h.
| #define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */ |
Definition at line 131 of file defBF549.h.
| #define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */ |
Definition at line 179 of file defBF549.h.
| #define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */ |
Definition at line 181 of file defBF549.h.
| #define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ |
Definition at line 180 of file defBF549.h.
| #define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */ |
Definition at line 136 of file defBF549.h.
| #define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */ |
Definition at line 138 of file defBF549.h.
| #define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */ |
Definition at line 137 of file defBF549.h.
| #define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */ |
Definition at line 140 of file defBF549.h.
| #define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */ |
Definition at line 139 of file defBF549.h.
| #define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */ |
Definition at line 18 of file defBF549.h.
| #define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */ |
Definition at line 27 of file defBF549.h.
| #define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */ |
Definition at line 64 of file defBF549.h.
| #define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */ |
Definition at line 66 of file defBF549.h.
| #define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */ |
Definition at line 67 of file defBF549.h.
| #define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */ |
Definition at line 68 of file defBF549.h.
| #define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */ |
Definition at line 65 of file defBF549.h.
| #define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */ |
Definition at line 72 of file defBF549.h.
| #define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */ |
Definition at line 74 of file defBF549.h.
| #define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */ |
Definition at line 75 of file defBF549.h.
| #define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */ |
Definition at line 76 of file defBF549.h.
| #define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */ |
Definition at line 73 of file defBF549.h.
| #define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */ |
Definition at line 80 of file defBF549.h.
| #define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */ |
Definition at line 82 of file defBF549.h.
| #define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ |
Definition at line 83 of file defBF549.h.
| #define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */ |
Definition at line 84 of file defBF549.h.
| #define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */ |
Definition at line 81 of file defBF549.h.
| #define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */ |
Definition at line 88 of file defBF549.h.
| #define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */ |
Definition at line 90 of file defBF549.h.
| #define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ |
Definition at line 91 of file defBF549.h.
| #define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */ |
Definition at line 92 of file defBF549.h.
| #define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */ |
Definition at line 89 of file defBF549.h.
| #define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */ |
Definition at line 96 of file defBF549.h.
| #define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */ |
Definition at line 98 of file defBF549.h.
| #define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */ |
Definition at line 99 of file defBF549.h.
| #define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */ |
Definition at line 100 of file defBF549.h.
| #define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */ |
Definition at line 97 of file defBF549.h.
| #define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */ |
Definition at line 104 of file defBF549.h.
| #define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */ |
Definition at line 106 of file defBF549.h.
| #define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */ |
Definition at line 107 of file defBF549.h.
| #define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */ |
Definition at line 108 of file defBF549.h.
| #define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */ |
Definition at line 105 of file defBF549.h.
| #define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */ |
Definition at line 112 of file defBF549.h.
| #define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */ |
Definition at line 114 of file defBF549.h.
| #define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */ |
Definition at line 115 of file defBF549.h.
| #define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */ |
Definition at line 116 of file defBF549.h.
| #define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */ |
Definition at line 113 of file defBF549.h.
| #define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */ |
Definition at line 120 of file defBF549.h.
| #define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */ |
Definition at line 122 of file defBF549.h.
| #define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */ |
Definition at line 123 of file defBF549.h.
| #define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */ |
Definition at line 124 of file defBF549.h.
| #define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */ |
Definition at line 121 of file defBF549.h.
| #define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */ |
Definition at line 182 of file defBF549.h.
| #define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */ |
Definition at line 156 of file defBF549.h.
| #define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */ |
Definition at line 157 of file defBF549.h.
| #define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */ |
Definition at line 30 of file defBF549.h.
| #define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */ |
Definition at line 23 of file defBF549.h.
| #define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */ |
Definition at line 24 of file defBF549.h.
| #define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */ |
Definition at line 21 of file defBF549.h.
| #define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */ |
Definition at line 22 of file defBF549.h.
| #define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */ |
Definition at line 29 of file defBF549.h.
| #define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */ |
Definition at line 28 of file defBF549.h.
| #define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */ |
Definition at line 26 of file defBF549.h.
| #define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */ |
Definition at line 149 of file defBF549.h.
| #define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */ |
Definition at line 151 of file defBF549.h.
| #define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */ |
Definition at line 150 of file defBF549.h.
| #define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */ |
Definition at line 152 of file defBF549.h.
| #define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ |
Definition at line 183 of file defBF549.h.
| #define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */ |
Definition at line 25 of file defBF549.h.
| #define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */ |
Definition at line 161 of file defBF549.h.
| #define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */ |
Definition at line 162 of file defBF549.h.
| #define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */ |
Definition at line 171 of file defBF549.h.
| #define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */ |
Definition at line 172 of file defBF549.h.
| #define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */ |
Definition at line 173 of file defBF549.h.
| #define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */ |
Definition at line 174 of file defBF549.h.
| #define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */ |
Definition at line 175 of file defBF549.h.
| #define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */ |
Definition at line 163 of file defBF549.h.
| #define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */ |
Definition at line 164 of file defBF549.h.
| #define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */ |
Definition at line 165 of file defBF549.h.
| #define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */ |
Definition at line 166 of file defBF549.h.
| #define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */ |
Definition at line 167 of file defBF549.h.
| #define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */ |
Definition at line 168 of file defBF549.h.
| #define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */ |
Definition at line 169 of file defBF549.h.
| #define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */ |
Definition at line 170 of file defBF549.h.
| #define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */ |
Definition at line 145 of file defBF549.h.
| #define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */ |
Definition at line 144 of file defBF549.h.
| #define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ |
Definition at line 184 of file defBF549.h.
| #define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */ |
Definition at line 19 of file defBF549.h.
| #define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */ |
Definition at line 20 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ |
Definition at line 53 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */ |
Definition at line 54 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ |
Definition at line 55 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ |
Definition at line 56 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ |
Definition at line 57 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */ |
Definition at line 58 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ |
Definition at line 59 of file defBF549.h.
| #define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ |
Definition at line 60 of file defBF549.h.
1.8.2