dilnetpc.c File Reference

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/concat.h>
#include <asm/io.h>

Go to the source code of this file.

Macros
#define	DNPC_BIOS_BLOCKS_WRITEPROTECTED
#define	BIOSID_BASE   0x000fe100
#define	ID_DNPC   "DNP1486"
#define	ID_ADNP   "ADNP1486"
#define	FLASH_BASE   0x2000000
#define	CSC_INDEX   0x22
#define	CSC_DATA   0x23
#define	CSC_MMSWAR   0x30 /* MMS window C-F attributes register */
#define	CSC_MMSWDSR   0x31 /* MMS window C-F device select register */
#define	CSC_RBWR   0xa7 /* GPIO Read-Back/Write Register B */
#define	CSC_CR   0xd0 /* internal I/O device disable/Echo */
#define	CSC_PCCMDCR   0xf1 /* PC card mode and DMA control register */
#define	PCC_INDEX   0x3e0
#define	PCC_DATA   0x3e1
#define	PCC_AWER_B   0x46 /* Socket B Address Window enable register */
#define	PCC_MWSAR_1_Lo   0x58 /* memory window 1 start address low register */
#define	PCC_MWSAR_1_Hi   0x59 /* memory window 1 start address high register */
#define	PCC_MWEAR_1_Lo   0x5A /* memory window 1 stop address low register */
#define	PCC_MWEAR_1_Hi   0x5B /* memory window 1 stop address high register */
#define	PCC_MWAOR_1_Lo   0x5C /* memory window 1 address offset low register */
#define	PCC_MWAOR_1_Hi   0x5D /* memory window 1 address offset high register */
#define	DNP_WINDOW_SIZE   0x00200000 /* DNP flash size is 2MiB */
#define	ADNP_WINDOW_SIZE   0x00400000 /* ADNP flash size is 4MiB */
#define	WINDOW_ADDR   FLASH_BASE
#define	NUM_PARTITIONS   ARRAY_SIZE(partition_info)
#define	NUM_HIGHLVL_PARTITIONS   ARRAY_SIZE(higlvl_partition_info)

Functions
	module_init (init_dnpc)
	module_exit (cleanup_dnpc)
	MODULE_LICENSE ("GPL")
	MODULE_AUTHOR ("Sysgo Real-Time Solutions GmbH")
	MODULE_DESCRIPTION ("MTD map driver for SSV DIL/NetPC DNP & ADNP")

Macro Definition Documentation

#define ADNP_WINDOW_SIZE   0x00400000 /* ADNP flash size is 4MiB */

Definition at line 249 of file dilnetpc.c.

#define BIOSID_BASE   0x000fe100

Definition at line 57 of file dilnetpc.c.

#define CSC_CR   0xd0 /* internal I/O device disable/Echo */

Definition at line 78 of file dilnetpc.c.

#define CSC_DATA   0x23

Definition at line 71 of file dilnetpc.c.

#define CSC_INDEX   0x22

Definition at line 70 of file dilnetpc.c.

#define CSC_MMSWAR   0x30 /* MMS window C-F attributes register */

Definition at line 73 of file dilnetpc.c.

#define CSC_MMSWDSR   0x31 /* MMS window C-F device select register */

Definition at line 74 of file dilnetpc.c.

#define CSC_PCCMDCR   0xf1 /* PC card mode and DMA control register */

Definition at line 81 of file dilnetpc.c.

#define CSC_RBWR   0xa7 /* GPIO Read-Back/Write Register B */

Definition at line 76 of file dilnetpc.c.

#define DNP_WINDOW_SIZE   0x00200000 /* DNP flash size is 2MiB */

Definition at line 248 of file dilnetpc.c.

#define DNPC_BIOS_BLOCKS_WRITEPROTECTED

Definition at line 51 of file dilnetpc.c.

#define FLASH_BASE   0x2000000

Definition at line 65 of file dilnetpc.c.

#define ID_ADNP   "ADNP1486"

Definition at line 60 of file dilnetpc.c.

#define ID_DNPC   "DNP1486"

Definition at line 59 of file dilnetpc.c.

#define NUM_HIGHLVL_PARTITIONS   ARRAY_SIZE(higlvl_partition_info)

Definition at line 345 of file dilnetpc.c.

#define NUM_PARTITIONS   ARRAY_SIZE(partition_info)

Definition at line 300 of file dilnetpc.c.

#define PCC_AWER_B   0x46 /* Socket B Address Window enable register */

Definition at line 91 of file dilnetpc.c.

#define PCC_DATA   0x3e1

Definition at line 89 of file dilnetpc.c.

#define PCC_INDEX   0x3e0

Definition at line 88 of file dilnetpc.c.

#define PCC_MWAOR_1_Hi   0x5D /* memory window 1 address offset high register */

Definition at line 97 of file dilnetpc.c.

#define PCC_MWAOR_1_Lo   0x5C /* memory window 1 address offset low register */

Definition at line 96 of file dilnetpc.c.

#define PCC_MWEAR_1_Hi   0x5B /* memory window 1 stop address high register */

Definition at line 95 of file dilnetpc.c.

#define PCC_MWEAR_1_Lo   0x5A /* memory window 1 stop address low register */

Definition at line 94 of file dilnetpc.c.

#define PCC_MWSAR_1_Hi   0x59 /* memory window 1 start address high register */

Definition at line 93 of file dilnetpc.c.

#define PCC_MWSAR_1_Lo   0x58 /* memory window 1 start address low register */

Definition at line 92 of file dilnetpc.c.

#define WINDOW_ADDR   FLASH_BASE

Definition at line 250 of file dilnetpc.c.

Function Documentation

MODULE_AUTHOR

(

"Sysgo Real-Time Solutions GmbH"

)

MODULE_DESCRIPTION

(

"MTD map driver for SSV DIL/NetPC DNP & ADNP"

)

module_exit

(

cleanup_dnpc

)

module_init

(

init_dnpc

)

MODULE_LICENSE

(

"GPL"

)