registers.h File Reference

Go to the source code of this file.

Macros
#define	IOAT_PCI_DMACTRL_OFFSET   0x48
#define	IOAT_PCI_DMACTRL_DMA_EN   0x00000001
#define	IOAT_PCI_DMACTRL_MSI_EN   0x00000002
#define	IOAT_PCI_DEVICE_ID_OFFSET   0x02
#define	IOAT_PCI_DMAUNCERRSTS_OFFSET   0x148
#define	IOAT_PCI_CHANERR_INT_OFFSET   0x180
#define	IOAT_PCI_CHANERRMASK_INT_OFFSET   0x184
#define	IOAT_CHANCNT_OFFSET   0x00 /* 8-bit */
#define	IOAT_XFERCAP_OFFSET   0x01 /* 8-bit */
#define	IOAT_XFERCAP_4KB   12
#define	IOAT_XFERCAP_8KB   13
#define	IOAT_XFERCAP_16KB   14
#define	IOAT_XFERCAP_32KB   15
#define	IOAT_XFERCAP_32GB   0
#define	IOAT_GENCTRL_OFFSET   0x02 /* 8-bit */
#define	IOAT_GENCTRL_DEBUG_EN   0x01
#define	IOAT_INTRCTRL_OFFSET   0x03 /* 8-bit */
#define	IOAT_INTRCTRL_MASTER_INT_EN   0x01 /* Master Interrupt Enable */
#define	IOAT_INTRCTRL_INT_STATUS   0x02 /* ATTNSTATUS -or- Channel Int */
#define	IOAT_INTRCTRL_INT   0x04 /* INT_STATUS -and- MASTER_INT_EN */
#define	IOAT_INTRCTRL_MSIX_VECTOR_CONTROL   0x08 /* Enable all MSI-X vectors */
#define	IOAT_ATTNSTATUS_OFFSET   0x04 /* Each bit is a channel */
#define	IOAT_VER_OFFSET   0x08 /* 8-bit */
#define	IOAT_VER_MAJOR_MASK   0xF0
#define	IOAT_VER_MINOR_MASK   0x0F
#define	GET_IOAT_VER_MAJOR(x)   (((x) & IOAT_VER_MAJOR_MASK) >> 4)
#define	GET_IOAT_VER_MINOR(x)   ((x) & IOAT_VER_MINOR_MASK)
#define	IOAT_PERPORTOFFSET_OFFSET   0x0A /* 16-bit */
#define	IOAT_INTRDELAY_OFFSET   0x0C /* 16-bit */
#define	IOAT_INTRDELAY_MASK   0x3FFF /* Interrupt Delay Time */
#define	IOAT_INTRDELAY_COALESE_SUPPORT   0x8000 /* Interrupt Coalescing Supported */
#define	IOAT_DEVICE_STATUS_OFFSET   0x0E /* 16-bit */
#define	IOAT_DEVICE_STATUS_DEGRADED_MODE   0x0001
#define	IOAT_DEVICE_MMIO_RESTRICTED   0x0002
#define	IOAT_DEVICE_MEMORY_BYPASS   0x0004
#define	IOAT_DEVICE_ADDRESS_REMAPPING   0x0008
#define	IOAT_DMA_CAP_OFFSET   0x10 /* 32-bit */
#define	IOAT_CAP_PAGE_BREAK   0x00000001
#define	IOAT_CAP_CRC   0x00000002
#define	IOAT_CAP_SKIP_MARKER   0x00000004
#define	IOAT_CAP_DCA   0x00000010
#define	IOAT_CAP_CRC_MOVE   0x00000020
#define	IOAT_CAP_FILL_BLOCK   0x00000040
#define	IOAT_CAP_APIC   0x00000080
#define	IOAT_CAP_XOR   0x00000100
#define	IOAT_CAP_PQ   0x00000200
#define	IOAT_CHANNEL_MMIO_SIZE   0x80 /* Each Channel MMIO space is this size */
#define	IOAT_CHANCTRL_OFFSET   0x00 /* 16-bit Channel Control Register */
#define	IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK   0xF000
#define	IOAT3_CHANCTRL_COMPL_DCA_EN   0x0200
#define	IOAT_CHANCTRL_CHANNEL_IN_USE   0x0100
#define	IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL   0x0020
#define	IOAT_CHANCTRL_ERR_INT_EN   0x0010
#define	IOAT_CHANCTRL_ANY_ERR_ABORT_EN   0x0008
#define	IOAT_CHANCTRL_ERR_COMPLETION_EN   0x0004
#define	IOAT_CHANCTRL_INT_REARM   0x0001
#define	IOAT_CHANCTRL_RUN
#define	IOAT_DMA_COMP_OFFSET   0x02 /* 16-bit DMA channel compatibility */
#define	IOAT_DMA_COMP_V1   0x0001 /* Compatibility with DMA version 1 */
#define	IOAT_DMA_COMP_V2   0x0002 /* Compatibility with DMA version 2 */
#define	IOAT1_CHANSTS_OFFSET   0x04 /* 64-bit Channel Status Register */
#define	IOAT2_CHANSTS_OFFSET   0x08 /* 64-bit Channel Status Register */
#define	IOAT_CHANSTS_OFFSET(ver)
#define	IOAT1_CHANSTS_OFFSET_LOW   0x04
#define	IOAT2_CHANSTS_OFFSET_LOW   0x08
#define	IOAT_CHANSTS_OFFSET_LOW(ver)
#define	IOAT1_CHANSTS_OFFSET_HIGH   0x08
#define	IOAT2_CHANSTS_OFFSET_HIGH   0x0C
#define	IOAT_CHANSTS_OFFSET_HIGH(ver)
#define	IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR   (~0x3fULL)
#define	IOAT_CHANSTS_SOFT_ERR   0x10ULL
#define	IOAT_CHANSTS_UNAFFILIATED_ERR   0x8ULL
#define	IOAT_CHANSTS_STATUS   0x7ULL
#define	IOAT_CHANSTS_ACTIVE   0x0
#define	IOAT_CHANSTS_DONE   0x1
#define	IOAT_CHANSTS_SUSPENDED   0x2
#define	IOAT_CHANSTS_HALTED   0x3
#define	IOAT_CHAN_DMACOUNT_OFFSET   0x06 /* 16-bit DMA Count register */
#define	IOAT_DCACTRL_OFFSET   0x30 /* 32 bit Direct Cache Access Control Register */
#define	IOAT_DCACTRL_CMPL_WRITE_ENABLE   0x10000
#define	IOAT_DCACTRL_TARGET_CPU_MASK   0xFFFF /* APIC ID */
#define	IOAT_DCAOFFSET_OFFSET   0x14
#define	IOAT_DCA_VER_OFFSET   0x00
#define	IOAT_DCA_VER_MAJOR_MASK   0xF0
#define	IOAT_DCA_VER_MINOR_MASK   0x0F
#define	IOAT_DCA_COMP_OFFSET   0x02
#define	IOAT_DCA_COMP_V1   0x1
#define	IOAT_FSB_CAPABILITY_OFFSET   0x04
#define	IOAT_FSB_CAPABILITY_PREFETCH   0x1
#define	IOAT_PCI_CAPABILITY_OFFSET   0x06
#define	IOAT_PCI_CAPABILITY_MEMWR   0x1
#define	IOAT_FSB_CAP_ENABLE_OFFSET   0x08
#define	IOAT_FSB_CAP_ENABLE_PREFETCH   0x1
#define	IOAT_PCI_CAP_ENABLE_OFFSET   0x0A
#define	IOAT_PCI_CAP_ENABLE_MEMWR   0x1
#define	IOAT_APICID_TAG_MAP_OFFSET   0x0C
#define	IOAT_APICID_TAG_MAP_TAG0   0x0000000F
#define	IOAT_APICID_TAG_MAP_TAG0_SHIFT   0
#define	IOAT_APICID_TAG_MAP_TAG1   0x000000F0
#define	IOAT_APICID_TAG_MAP_TAG1_SHIFT   4
#define	IOAT_APICID_TAG_MAP_TAG2   0x00000F00
#define	IOAT_APICID_TAG_MAP_TAG2_SHIFT   8
#define	IOAT_APICID_TAG_MAP_TAG3   0x0000F000
#define	IOAT_APICID_TAG_MAP_TAG3_SHIFT   12
#define	IOAT_APICID_TAG_MAP_TAG4   0x000F0000
#define	IOAT_APICID_TAG_MAP_TAG4_SHIFT   16
#define	IOAT_APICID_TAG_CB2_VALID   0x8080808080
#define	IOAT_DCA_GREQID_OFFSET   0x10
#define	IOAT_DCA_GREQID_SIZE   0x04
#define	IOAT_DCA_GREQID_MASK   0xFFFF
#define	IOAT_DCA_GREQID_IGNOREFUN   0x10000000
#define	IOAT_DCA_GREQID_VALID   0x20000000
#define	IOAT_DCA_GREQID_LASTID   0x80000000
#define	IOAT3_CSI_CAPABILITY_OFFSET   0x08
#define	IOAT3_CSI_CAPABILITY_PREFETCH   0x1
#define	IOAT3_PCI_CAPABILITY_OFFSET   0x0A
#define	IOAT3_PCI_CAPABILITY_MEMWR   0x1
#define	IOAT3_CSI_CONTROL_OFFSET   0x0C
#define	IOAT3_CSI_CONTROL_PREFETCH   0x1
#define	IOAT3_PCI_CONTROL_OFFSET   0x0E
#define	IOAT3_PCI_CONTROL_MEMWR   0x1
#define	IOAT3_APICID_TAG_MAP_OFFSET   0x10
#define	IOAT3_APICID_TAG_MAP_OFFSET_LOW   0x10
#define	IOAT3_APICID_TAG_MAP_OFFSET_HIGH   0x14
#define	IOAT3_DCA_GREQID_OFFSET   0x02
#define	IOAT1_CHAINADDR_OFFSET   0x0C /* 64-bit Descriptor Chain Address Register */
#define	IOAT2_CHAINADDR_OFFSET   0x10 /* 64-bit Descriptor Chain Address Register */
#define	IOAT_CHAINADDR_OFFSET(ver)
#define	IOAT1_CHAINADDR_OFFSET_LOW   0x0C
#define	IOAT2_CHAINADDR_OFFSET_LOW   0x10
#define	IOAT_CHAINADDR_OFFSET_LOW(ver)
#define	IOAT1_CHAINADDR_OFFSET_HIGH   0x10
#define	IOAT2_CHAINADDR_OFFSET_HIGH   0x14
#define	IOAT_CHAINADDR_OFFSET_HIGH(ver)
#define	IOAT1_CHANCMD_OFFSET   0x14 /* 8-bit DMA Channel Command Register */
#define	IOAT2_CHANCMD_OFFSET   0x04 /* 8-bit DMA Channel Command Register */
#define	IOAT_CHANCMD_OFFSET(ver)
#define	IOAT_CHANCMD_RESET   0x20
#define	IOAT_CHANCMD_RESUME   0x10
#define	IOAT_CHANCMD_ABORT   0x08
#define	IOAT_CHANCMD_SUSPEND   0x04
#define	IOAT_CHANCMD_APPEND   0x02
#define	IOAT_CHANCMD_START   0x01
#define	IOAT_CHANCMP_OFFSET   0x18 /* 64-bit Channel Completion Address Register */
#define	IOAT_CHANCMP_OFFSET_LOW   0x18
#define	IOAT_CHANCMP_OFFSET_HIGH   0x1C
#define	IOAT_CDAR_OFFSET   0x20 /* 64-bit Current Descriptor Address Register */
#define	IOAT_CDAR_OFFSET_LOW   0x20
#define	IOAT_CDAR_OFFSET_HIGH   0x24
#define	IOAT_CHANERR_OFFSET   0x28 /* 32-bit Channel Error Register */
#define	IOAT_CHANERR_SRC_ADDR_ERR   0x0001
#define	IOAT_CHANERR_DEST_ADDR_ERR   0x0002
#define	IOAT_CHANERR_NEXT_ADDR_ERR   0x0004
#define	IOAT_CHANERR_NEXT_DESC_ALIGN_ERR   0x0008
#define	IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR   0x0010
#define	IOAT_CHANERR_CHANCMD_ERR   0x0020
#define	IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0040
#define	IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0080
#define	IOAT_CHANERR_READ_DATA_ERR   0x0100
#define	IOAT_CHANERR_WRITE_DATA_ERR   0x0200
#define	IOAT_CHANERR_CONTROL_ERR   0x0400
#define	IOAT_CHANERR_LENGTH_ERR   0x0800
#define	IOAT_CHANERR_COMPLETION_ADDR_ERR   0x1000
#define	IOAT_CHANERR_INT_CONFIGURATION_ERR   0x2000
#define	IOAT_CHANERR_SOFT_ERR   0x4000
#define	IOAT_CHANERR_UNAFFILIATED_ERR   0x8000
#define	IOAT_CHANERR_XOR_P_OR_CRC_ERR   0x10000
#define	IOAT_CHANERR_XOR_Q_ERR   0x20000
#define	IOAT_CHANERR_DESCRIPTOR_COUNT_ERR   0x40000
#define	IOAT_CHANERR_HANDLE_MASK   (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
#define	IOAT_CHANERR_MASK_OFFSET   0x2C /* 32-bit Channel Error Register */

Macro Definition Documentation

#define GET_IOAT_VER_MAJOR

(

x

)

(((x) & IOAT_VER_MAJOR_MASK) >> 4)

Definition at line 57 of file registers.h.

#define GET_IOAT_VER_MINOR

(

x

)

((x) & IOAT_VER_MINOR_MASK)

Definition at line 58 of file registers.h.

#define IOAT1_CHAINADDR_OFFSET   0x0C /* 64-bit Descriptor Chain Address Register */

Definition at line 192 of file registers.h.

#define IOAT1_CHAINADDR_OFFSET_HIGH   0x10

Definition at line 200 of file registers.h.

#define IOAT1_CHAINADDR_OFFSET_LOW   0x0C

Definition at line 196 of file registers.h.

#define IOAT1_CHANCMD_OFFSET   0x14 /* 8-bit DMA Channel Command Register */

Definition at line 205 of file registers.h.

#define IOAT1_CHANSTS_OFFSET   0x04 /* 64-bit Channel Status Register */

Definition at line 103 of file registers.h.

#define IOAT1_CHANSTS_OFFSET_HIGH   0x08

Definition at line 111 of file registers.h.

#define IOAT1_CHANSTS_OFFSET_LOW   0x04

Definition at line 107 of file registers.h.

#define IOAT2_CHAINADDR_OFFSET   0x10 /* 64-bit Descriptor Chain Address Register */

Definition at line 193 of file registers.h.

#define IOAT2_CHAINADDR_OFFSET_HIGH   0x14

Definition at line 201 of file registers.h.

#define IOAT2_CHAINADDR_OFFSET_LOW   0x10

Definition at line 197 of file registers.h.

#define IOAT2_CHANCMD_OFFSET   0x04 /* 8-bit DMA Channel Command Register */

Definition at line 206 of file registers.h.

#define IOAT2_CHANSTS_OFFSET   0x08 /* 64-bit Channel Status Register */

Definition at line 104 of file registers.h.

#define IOAT2_CHANSTS_OFFSET_HIGH   0x0C

Definition at line 112 of file registers.h.

#define IOAT2_CHANSTS_OFFSET_LOW   0x08

Definition at line 108 of file registers.h.

#define IOAT3_APICID_TAG_MAP_OFFSET   0x10

Definition at line 186 of file registers.h.

#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH   0x14

Definition at line 188 of file registers.h.

#define IOAT3_APICID_TAG_MAP_OFFSET_LOW   0x10

Definition at line 187 of file registers.h.

#define IOAT3_CHANCTRL_COMPL_DCA_EN   0x0200

Definition at line 88 of file registers.h.

#define IOAT3_CSI_CAPABILITY_OFFSET   0x08

Definition at line 174 of file registers.h.

#define IOAT3_CSI_CAPABILITY_PREFETCH   0x1

Definition at line 175 of file registers.h.

#define IOAT3_CSI_CONTROL_OFFSET   0x0C

Definition at line 180 of file registers.h.

#define IOAT3_CSI_CONTROL_PREFETCH   0x1

Definition at line 181 of file registers.h.

#define IOAT3_DCA_GREQID_OFFSET   0x02

Definition at line 190 of file registers.h.

#define IOAT3_PCI_CAPABILITY_MEMWR   0x1

Definition at line 178 of file registers.h.

#define IOAT3_PCI_CAPABILITY_OFFSET   0x0A

Definition at line 177 of file registers.h.

#define IOAT3_PCI_CONTROL_MEMWR   0x1

Definition at line 184 of file registers.h.

#define IOAT3_PCI_CONTROL_OFFSET   0x0E

Definition at line 183 of file registers.h.

#define IOAT_APICID_TAG_CB2_VALID   0x8080808080

Definition at line 165 of file registers.h.

#define IOAT_APICID_TAG_MAP_OFFSET   0x0C

Definition at line 154 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG0   0x0000000F

Definition at line 155 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG0_SHIFT   0

Definition at line 156 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG1   0x000000F0

Definition at line 157 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG1_SHIFT   4

Definition at line 158 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG2   0x00000F00

Definition at line 159 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG2_SHIFT   8

Definition at line 160 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG3   0x0000F000

Definition at line 161 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG3_SHIFT   12

Definition at line 162 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG4   0x000F0000

Definition at line 163 of file registers.h.

#define IOAT_APICID_TAG_MAP_TAG4_SHIFT   16

Definition at line 164 of file registers.h.

#define IOAT_ATTNSTATUS_OFFSET   0x04 /* Each bit is a channel */

Definition at line 52 of file registers.h.

#define IOAT_CAP_APIC   0x00000080

Definition at line 79 of file registers.h.

#define IOAT_CAP_CRC   0x00000002

Definition at line 74 of file registers.h.

#define IOAT_CAP_CRC_MOVE   0x00000020

Definition at line 77 of file registers.h.

#define IOAT_CAP_DCA   0x00000010

Definition at line 76 of file registers.h.

#define IOAT_CAP_FILL_BLOCK   0x00000040

Definition at line 78 of file registers.h.

#define IOAT_CAP_PAGE_BREAK   0x00000001

Definition at line 73 of file registers.h.

#define IOAT_CAP_PQ   0x00000200

Definition at line 81 of file registers.h.

#define IOAT_CAP_SKIP_MARKER   0x00000004

Definition at line 75 of file registers.h.

#define IOAT_CAP_XOR   0x00000100

Definition at line 80 of file registers.h.

#define IOAT_CDAR_OFFSET   0x20 /* 64-bit Current Descriptor Address Register */

Definition at line 220 of file registers.h.

#define IOAT_CDAR_OFFSET_HIGH   0x24

Definition at line 222 of file registers.h.

#define IOAT_CDAR_OFFSET_LOW   0x20

Definition at line 221 of file registers.h.

#define IOAT_CHAINADDR_OFFSET

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)

Definition at line 194 of file registers.h.

#define IOAT_CHAINADDR_OFFSET_HIGH

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)

Definition at line 202 of file registers.h.

#define IOAT_CHAINADDR_OFFSET_LOW

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)

Definition at line 198 of file registers.h.

#define IOAT_CHAN_DMACOUNT_OFFSET   0x06 /* 16-bit DMA Count register */

Definition at line 126 of file registers.h.

#define IOAT_CHANCMD_ABORT   0x08

Definition at line 211 of file registers.h.

#define IOAT_CHANCMD_APPEND   0x02

Definition at line 213 of file registers.h.

#define IOAT_CHANCMD_OFFSET

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)

Definition at line 207 of file registers.h.

#define IOAT_CHANCMD_RESET   0x20

Definition at line 209 of file registers.h.

#define IOAT_CHANCMD_RESUME   0x10

Definition at line 210 of file registers.h.

#define IOAT_CHANCMD_START   0x01

Definition at line 214 of file registers.h.

#define IOAT_CHANCMD_SUSPEND   0x04

Definition at line 212 of file registers.h.

#define IOAT_CHANCMP_OFFSET   0x18 /* 64-bit Channel Completion Address Register */

Definition at line 216 of file registers.h.

#define IOAT_CHANCMP_OFFSET_HIGH   0x1C

Definition at line 218 of file registers.h.

#define IOAT_CHANCMP_OFFSET_LOW   0x18

Definition at line 217 of file registers.h.

#define IOAT_CHANCNT_OFFSET   0x00 /* 8-bit */

Definition at line 34 of file registers.h.

#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN   0x0008

Definition at line 92 of file registers.h.

#define IOAT_CHANCTRL_CHANNEL_IN_USE   0x0100

Definition at line 89 of file registers.h.

#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK   0xF000

Definition at line 87 of file registers.h.

#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL   0x0020

Definition at line 90 of file registers.h.

#define IOAT_CHANCTRL_ERR_COMPLETION_EN   0x0004

Definition at line 93 of file registers.h.

#define IOAT_CHANCTRL_ERR_INT_EN   0x0010

Definition at line 91 of file registers.h.

#define IOAT_CHANCTRL_INT_REARM   0x0001

Definition at line 94 of file registers.h.

#define IOAT_CHANCTRL_OFFSET   0x00 /* 16-bit Channel Control Register */

Definition at line 86 of file registers.h.

#define IOAT_CHANCTRL_RUN

Value:

(IOAT_CHANCTRL_INT_REARM |\
                         IOAT_CHANCTRL_ANY_ERR_ABORT_EN)

Definition at line 95 of file registers.h.

#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR   0x0010

Definition at line 229 of file registers.h.

#define IOAT_CHANERR_CHANCMD_ERR   0x0020

Definition at line 230 of file registers.h.

#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0040

Definition at line 231 of file registers.h.

#define IOAT_CHANERR_COMPLETION_ADDR_ERR   0x1000

Definition at line 237 of file registers.h.

#define IOAT_CHANERR_CONTROL_ERR   0x0400

Definition at line 235 of file registers.h.

#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR   0x40000

Definition at line 243 of file registers.h.

#define IOAT_CHANERR_DEST_ADDR_ERR   0x0002

Definition at line 226 of file registers.h.

#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0080

Definition at line 232 of file registers.h.

#define IOAT_CHANERR_HANDLE_MASK   (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)

Definition at line 245 of file registers.h.

#define IOAT_CHANERR_INT_CONFIGURATION_ERR   0x2000

Definition at line 238 of file registers.h.

#define IOAT_CHANERR_LENGTH_ERR   0x0800

Definition at line 236 of file registers.h.

#define IOAT_CHANERR_MASK_OFFSET   0x2C /* 32-bit Channel Error Register */

Definition at line 247 of file registers.h.

#define IOAT_CHANERR_NEXT_ADDR_ERR   0x0004

Definition at line 227 of file registers.h.

#define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR   0x0008

Definition at line 228 of file registers.h.

#define IOAT_CHANERR_OFFSET   0x28 /* 32-bit Channel Error Register */

Definition at line 224 of file registers.h.

#define IOAT_CHANERR_READ_DATA_ERR   0x0100

Definition at line 233 of file registers.h.

#define IOAT_CHANERR_SOFT_ERR   0x4000

Definition at line 239 of file registers.h.

#define IOAT_CHANERR_SRC_ADDR_ERR   0x0001

Definition at line 225 of file registers.h.

#define IOAT_CHANERR_UNAFFILIATED_ERR   0x8000

Definition at line 240 of file registers.h.

#define IOAT_CHANERR_WRITE_DATA_ERR   0x0200

Definition at line 234 of file registers.h.

#define IOAT_CHANERR_XOR_P_OR_CRC_ERR   0x10000

Definition at line 241 of file registers.h.

#define IOAT_CHANERR_XOR_Q_ERR   0x20000

Definition at line 242 of file registers.h.

#define IOAT_CHANNEL_MMIO_SIZE   0x80 /* Each Channel MMIO space is this size */

Definition at line 83 of file registers.h.

#define IOAT_CHANSTS_ACTIVE   0x0

Definition at line 119 of file registers.h.

#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR   (~0x3fULL)

Definition at line 115 of file registers.h.

#define IOAT_CHANSTS_DONE   0x1

Definition at line 120 of file registers.h.

#define IOAT_CHANSTS_HALTED   0x3

Definition at line 122 of file registers.h.

#define IOAT_CHANSTS_OFFSET

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)

Definition at line 105 of file registers.h.

#define IOAT_CHANSTS_OFFSET_HIGH

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)

Definition at line 113 of file registers.h.

#define IOAT_CHANSTS_OFFSET_LOW

(

ver

)

Value:

((ver) < IOAT_VER_2_0 \
                        ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)

Definition at line 109 of file registers.h.

#define IOAT_CHANSTS_SOFT_ERR   0x10ULL

Definition at line 116 of file registers.h.

#define IOAT_CHANSTS_STATUS   0x7ULL

Definition at line 118 of file registers.h.

#define IOAT_CHANSTS_SUSPENDED   0x2

Definition at line 121 of file registers.h.

#define IOAT_CHANSTS_UNAFFILIATED_ERR   0x8ULL

Definition at line 117 of file registers.h.

#define IOAT_DCA_COMP_OFFSET   0x02

Definition at line 139 of file registers.h.

#define IOAT_DCA_COMP_V1   0x1

Definition at line 140 of file registers.h.

#define IOAT_DCA_GREQID_IGNOREFUN   0x10000000

Definition at line 170 of file registers.h.

#define IOAT_DCA_GREQID_LASTID   0x80000000

Definition at line 172 of file registers.h.

#define IOAT_DCA_GREQID_MASK   0xFFFF

Definition at line 169 of file registers.h.

#define IOAT_DCA_GREQID_OFFSET   0x10

Definition at line 167 of file registers.h.

#define IOAT_DCA_GREQID_SIZE   0x04

Definition at line 168 of file registers.h.

#define IOAT_DCA_GREQID_VALID   0x20000000

Definition at line 171 of file registers.h.

#define IOAT_DCA_VER_MAJOR_MASK   0xF0

Definition at line 136 of file registers.h.

#define IOAT_DCA_VER_MINOR_MASK   0x0F

Definition at line 137 of file registers.h.

#define IOAT_DCA_VER_OFFSET   0x00

Definition at line 135 of file registers.h.

#define IOAT_DCACTRL_CMPL_WRITE_ENABLE   0x10000

Definition at line 129 of file registers.h.

#define IOAT_DCACTRL_OFFSET   0x30 /* 32 bit Direct Cache Access Control Register */

Definition at line 128 of file registers.h.

#define IOAT_DCACTRL_TARGET_CPU_MASK   0xFFFF /* APIC ID */

Definition at line 130 of file registers.h.

#define IOAT_DCAOFFSET_OFFSET   0x14

Definition at line 133 of file registers.h.

#define IOAT_DEVICE_ADDRESS_REMAPPING   0x0008

Definition at line 70 of file registers.h.

#define IOAT_DEVICE_MEMORY_BYPASS   0x0004

Definition at line 69 of file registers.h.

#define IOAT_DEVICE_MMIO_RESTRICTED   0x0002

Definition at line 68 of file registers.h.

#define IOAT_DEVICE_STATUS_DEGRADED_MODE   0x0001

Definition at line 67 of file registers.h.

#define IOAT_DEVICE_STATUS_OFFSET   0x0E /* 16-bit */

Definition at line 66 of file registers.h.

#define IOAT_DMA_CAP_OFFSET   0x10 /* 32-bit */

Definition at line 72 of file registers.h.

#define IOAT_DMA_COMP_OFFSET   0x02 /* 16-bit DMA channel compatibility */

Definition at line 98 of file registers.h.

#define IOAT_DMA_COMP_V1   0x0001 /* Compatibility with DMA version 1 */

Definition at line 99 of file registers.h.

#define IOAT_DMA_COMP_V2   0x0002 /* Compatibility with DMA version 2 */

Definition at line 100 of file registers.h.

#define IOAT_FSB_CAP_ENABLE_OFFSET   0x08

Definition at line 148 of file registers.h.

#define IOAT_FSB_CAP_ENABLE_PREFETCH   0x1

Definition at line 149 of file registers.h.

#define IOAT_FSB_CAPABILITY_OFFSET   0x04

Definition at line 142 of file registers.h.

#define IOAT_FSB_CAPABILITY_PREFETCH   0x1

Definition at line 143 of file registers.h.

#define IOAT_GENCTRL_DEBUG_EN   0x01

Definition at line 44 of file registers.h.

#define IOAT_GENCTRL_OFFSET   0x02 /* 8-bit */

Definition at line 43 of file registers.h.

#define IOAT_INTRCTRL_INT   0x04 /* INT_STATUS -and- MASTER_INT_EN */

Definition at line 49 of file registers.h.

#define IOAT_INTRCTRL_INT_STATUS   0x02 /* ATTNSTATUS -or- Channel Int */

Definition at line 48 of file registers.h.

#define IOAT_INTRCTRL_MASTER_INT_EN   0x01 /* Master Interrupt Enable */

Definition at line 47 of file registers.h.

#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL   0x08 /* Enable all MSI-X vectors */

Definition at line 50 of file registers.h.

#define IOAT_INTRCTRL_OFFSET   0x03 /* 8-bit */

Definition at line 46 of file registers.h.

#define IOAT_INTRDELAY_COALESE_SUPPORT   0x8000 /* Interrupt Coalescing Supported */

Definition at line 64 of file registers.h.

#define IOAT_INTRDELAY_MASK   0x3FFF /* Interrupt Delay Time */

Definition at line 63 of file registers.h.

#define IOAT_INTRDELAY_OFFSET   0x0C /* 16-bit */

Definition at line 62 of file registers.h.

#define IOAT_PCI_CAP_ENABLE_MEMWR   0x1

Definition at line 152 of file registers.h.

#define IOAT_PCI_CAP_ENABLE_OFFSET   0x0A

Definition at line 151 of file registers.h.

#define IOAT_PCI_CAPABILITY_MEMWR   0x1

Definition at line 146 of file registers.h.

#define IOAT_PCI_CAPABILITY_OFFSET   0x06

Definition at line 145 of file registers.h.

#define IOAT_PCI_CHANERR_INT_OFFSET   0x180

Definition at line 30 of file registers.h.

#define IOAT_PCI_CHANERRMASK_INT_OFFSET   0x184

Definition at line 31 of file registers.h.

#define IOAT_PCI_DEVICE_ID_OFFSET   0x02

Definition at line 28 of file registers.h.

#define IOAT_PCI_DMACTRL_DMA_EN   0x00000001

Definition at line 25 of file registers.h.

#define IOAT_PCI_DMACTRL_MSI_EN   0x00000002

Definition at line 26 of file registers.h.

#define IOAT_PCI_DMACTRL_OFFSET   0x48

Definition at line 24 of file registers.h.

#define IOAT_PCI_DMAUNCERRSTS_OFFSET   0x148

Definition at line 29 of file registers.h.

#define IOAT_PERPORTOFFSET_OFFSET   0x0A /* 16-bit */

Definition at line 60 of file registers.h.

#define IOAT_VER_MAJOR_MASK   0xF0

Definition at line 55 of file registers.h.

#define IOAT_VER_MINOR_MASK   0x0F

Definition at line 56 of file registers.h.

#define IOAT_VER_OFFSET   0x08 /* 8-bit */

Definition at line 54 of file registers.h.

#define IOAT_XFERCAP_16KB   14

Definition at line 39 of file registers.h.

#define IOAT_XFERCAP_32GB   0

Definition at line 41 of file registers.h.

#define IOAT_XFERCAP_32KB   15

Definition at line 40 of file registers.h.

#define IOAT_XFERCAP_4KB   12

Definition at line 37 of file registers.h.

#define IOAT_XFERCAP_8KB   13

Definition at line 38 of file registers.h.

#define IOAT_XFERCAP_OFFSET   0x01 /* 8-bit */

Definition at line 36 of file registers.h.