Macros
#define	REG_SYS_ISO_CTRL 0x0000

#define	REG_SYS_FUNC_EN 0x0002

#define	PMC_FSM 0x0004

#define	SYS_CLKR 0x0008

#define	EPROM_CMD 0x000A

#define	EE_VPD 0x000C

#define	AFE_MISC 0x0010

#define	SPS0_CTRL 0x0011

#define	SPS1_CTRL 0x0018

#define	RF_CTRL 0x001F

#define	LDOA15_CTRL 0x0020

#define	LDOV12D_CTRL 0x0021

#define	LDOHCI12_CTRL 0x0022

#define	LDO_USB_SDIO 0x0023

#define	LPLDO_CTRL 0x0024

#define	AFE_XTAL_CTRL 0x0026

#define	AFE_PLL_CTRL 0x0028

#define	REG_EFUSE_CTRL 0x0030

#define	REG_EFUSE_TEST 0x0034

#define	PWR_DATA 0x0038

#define	DBG_PORT 0x003A

#define	DPS_TIMER 0x003C

#define	RCLK_MON 0x003E

#define	CMDR 0x0040

#define	TXPAUSE 0x0042

#define	LBKMD_SEL 0x0043

#define	TCR 0x0044

#define	RCR 0x0048

#define	MSR 0x004C

#define	SYSF_CFG 0x004D

#define	RX_PKY_LIMIT 0x004E

#define	MBIDCTRL 0x004F

#define	MACIDR 0x0050

#define	MACIDR0 0x0050

#define	MACIDR4 0x0054

#define	BSSIDR 0x0058

#define	HWVID 0x005E

#define	MAR 0x0060

#define	MBIDCAMCONTENT 0x0068

#define	MBIDCAMCFG 0x0070

#define	BUILDTIME 0x0074

#define	BUILDUSER 0x0078

#define	IDR0 MACIDR0

#define	IDR4 MACIDR4

#define	TSFR 0x0080

#define	SLOT_TIME 0x0089

#define	USTIME 0x008A

#define	SIFS_CCK 0x008C

#define	SIFS_OFDM 0x008E

#define	PIFS_TIME 0x0090

#define	ACK_TIMEOUT 0x0091

#define	EIFSTR 0x0092

#define	BCN_INTERVAL 0x0094

#define	ATIMWND 0x0096

#define	BCN_DRV_EARLY_INT 0x0098

#define	BCN_DMATIME 0x009A

#define	BCN_ERR_THRESH 0x009C

#define	MLT 0x009D

#define	RSVD_MAC_TUNE_US 0x009E

#define	RQPN 0x00A0

#define	RQPN1 0x00A0

#define	RQPN2 0x00A1

#define	RQPN3 0x00A2

#define	RQPN4 0x00A3

#define	RQPN5 0x00A4

#define	RQPN6 0x00A5

#define	RQPN7 0x00A6

#define	RQPN8 0x00A7

#define	RQPN9 0x00A8

#define	RQPN10 0x00A9

#define	LD_RQPN 0x00AB

#define	RXFF_BNDY 0x00AC

#define	RXRPT_BNDY 0x00B0

#define	TXPKTBUF_PGBNDY 0x00B4

#define	PBP 0x00B5

#define	RXDRVINFO_SZ 0x00B6

#define	TXFF_STATUS 0x00B7

#define	RXFF_STATUS 0x00B8

#define	TXFF_EMPTY_TH 0x00B9

#define	SDIO_RX_BLKSZ 0x00BC

#define	RXDMA 0x00BD

#define	RXPKT_NUM 0x00BE

#define	C2HCMD_UDT_SIZE 0x00C0

#define	C2HCMD_UDT_ADDR 0x00C2

#define	FIFOPAGE1 0x00C4

#define	FIFOPAGE2 0x00C8

#define	FIFOPAGE3 0x00CC

#define	FIFOPAGE4 0x00D0

#define	FIFOPAGE5 0x00D4

#define	FW_RSVD_PG_CRTL 0x00D8

#define	RXDMA_AGG_PG_TH 0x00D9

#define	TXDESC_MSK 0x00DC

#define	TXRPTFF_RDPTR 0x00E0

#define	TXRPTFF_WTPTR 0x00E4

#define	C2HFF_RDPTR 0x00E8

#define	C2HFF_WTPTR 0x00EC

#define	RXFF0_RDPTR 0x00F0

#define	RXFF0_WTPTR 0x00F4

#define	RXFF1_RDPTR 0x00F8

#define	RXFF1_WTPTR 0x00FC

#define	RXRPT0_RDPTR 0x0100

#define	RXRPT0_WTPTR 0x0104

#define	RXRPT1_RDPTR 0x0108

#define	RXRPT1_WTPTR 0x010C

#define	RX0_UDT_SIZE 0x0110

#define	RX1PKTNUM 0x0114

#define	RXFILTERMAP 0x0116

#define	RXFILTERMAP_GP1 0x0118

#define	RXFILTERMAP_GP2 0x011A

#define	RXFILTERMAP_GP3 0x011C

#define	BCNQ_CTRL 0x0120

#define	MGTQ_CTRL 0x0124

#define	HIQ_CTRL 0x0128

#define	VOTID7_CTRL 0x012c

#define	VOTID6_CTRL 0x0130

#define	VITID5_CTRL 0x0134

#define	VITID4_CTRL 0x0138

#define	BETID3_CTRL 0x013c

#define	BETID0_CTRL 0x0140

#define	BKTID2_CTRL 0x0144

#define	BKTID1_CTRL 0x0148

#define	CMDQ_CTRL 0x014c

#define	TXPKT_NUM_CTRL 0x0150

#define	TXQ_PGADD 0x0152

#define	TXFF_PG_NUM 0x0154

#define	TRXDMA_STATUS 0x0156

#define	INIMCS_SEL 0x0160

#define	TX_RATE_REG INIMCS_SEL

#define	INIRTSMCS_SEL 0x0180

#define	RRSR 0x0181

#define	ARFR0 0x0184

#define	ARFR1 0x0188

#define	ARFR2 0x018C

#define	ARFR3 0x0190

#define	ARFR4 0x0194

#define	ARFR5 0x0198

#define	ARFR6 0x019C

#define	ARFR7 0x01A0

#define	AGGLEN_LMT_H 0x01A7

#define	AGGLEN_LMT_L 0x01A8

#define	DARFRC 0x01B0

#define	RARFRC 0x01B8

#define	MCS_TXAGC 0x01C0

#define	CCK_TXAGC 0x01C8

#define	EDCAPARA_VO 0x01D0

#define	EDCAPARA_VI 0x01D4

#define	EDCAPARA_BE 0x01D8

#define	EDCAPARA_BK 0x01DC

#define	BCNTCFG 0x01E0

#define	CWRR 0x01E2

#define	ACMAVG 0x01E4

#define	AcmHwCtrl 0x01E7

#define	VO_ADMTM 0x01E8

#define	VI_ADMTM 0x01EC

#define	BE_ADMTM 0x01F0

#define	RETRY_LIMIT 0x01F4

#define	SG_RATE 0x01F6

#define	NAV_CTRL 0x0200

#define	BW_OPMODE 0x0203

#define	BACAMCMD 0x0204

#define	BACAMCONTENT 0x0208

#define	LBDLY 0x0210

#define	FWDLY 0x0211

#define	HWPC_RX_CTRL 0x0218

#define	MQIR 0x0220

#define	MAIR 0x0222

#define	MSIR 0x0224

#define	CLM_RESULT 0x0227

#define	NHM_RPI_CNT 0x0228

#define	RXERR_RPT 0x0230

#define	NAV_PROT_LEN 0x0234

#define	CFEND_TH 0x0236

#define	AMPDU_MIN_SPACE 0x0237

#define	TXOP_STALL_CTRL 0x0238

#define	REG_RWCAM 0x0240

#define	REG_WCAMI 0x0244

#define	REG_RCAMO 0x0248

#define	REG_CAMDBG 0x024C

#define	REG_SECR 0x0250

#define	WOW_CTRL 0x0260

#define	PSSTATUS 0x0261

#define	PSSWITCH 0x0262

#define	MIMOPS_WAIT_PERIOD 0x0263

#define	LPNAV_CTRL 0x0264

#define	WFM0 0x0270

#define	WFM1 0x0280

#define	WFM2 0x0290

#define	WFM3 0x02A0

#define	WFM4 0x02B0

#define	WFM5 0x02C0

#define	WFCRC 0x02D0

#define	FW_RPT_REG 0x02c4

#define	PSTIME 0x02E0

#define	TIMER0 0x02E4

#define	TIMER1 0x02E8

#define	GPIO_IN_SE 0x02EC

#define	GPIO_IO_SEL 0x02EE

#define	MAC_PINMUX_CFG 0x02F1

#define	LEDCFG 0x02F2

#define	PHY_REG 0x02F3

#define	PHY_REG_DATA 0x02F4

#define	REG_EFUSE_CLK 0x02F8

#define	INTA_MASK 0x0300

#define	ISR 0x0308

#define	DBG_PORT_SWITCH 0x003A

#define	BIST 0x0310

#define	DBS 0x0314

#define	CPUINST 0x0318

#define	CPUCAUSE 0x031C

#define	LBUS_ERR_ADDR 0x0320

#define	LBUS_ERR_CMD 0x0324

#define	LBUS_ERR_DATA_L 0x0328

#define	LBUS_ERR_DATA_H 0x032C

#define	LX_EXCEPTION_ADDR 0x0330

#define	WDG_CTRL 0x0334

#define	INTMTU 0x0338

#define	INTM 0x033A

#define	FDLOCKTURN0 0x033C

#define	FDLOCKTURN1 0x033D

#define	TRXPKTBUF_DBG_DATA 0x0340

#define	TRXPKTBUF_DBG_CTRL 0x0348

#define	DPLL 0x034A

#define	CBUS_ERR_ADDR 0x0350

#define	CBUS_ERR_CMD 0x0354

#define	CBUS_ERR_DATA_L 0x0358

#define	CBUS_ERR_DATA_H 0x035C

#define	USB_SIE_INTF_ADDR 0x0360

#define	USB_SIE_INTF_WD 0x0361

#define	USB_SIE_INTF_RD 0x0362

#define	USB_SIE_INTF_CTRL 0x0363

#define	LBUS_MON_ADDR 0x0364

#define	LBUS_ADDR_MASK 0x0368

#define	TP_POLL 0x0500

#define	PM_CTRL 0x0502

#define	PCIF 0x0503

#define	THPDA 0x0514

#define	TMDA 0x0518

#define	TCDA 0x051C

#define	HDA 0x0520

#define	TVODA 0x0524

#define	TVIDA 0x0528

#define	TBEDA 0x052C

#define	TBKDA 0x0530

#define	TBDA 0x0534

#define	RCDA 0x0538

#define	RDQDA 0x053C

#define	DBI_WDATA 0x0540

#define	DBI_RDATA 0x0544

#define	DBI_CTRL 0x0548

#define	MDIO_DATA 0x0550

#define	MDIO_CTRL 0x0554

#define	PCI_RPWM 0x0561

#define	PCI_CPWM 0x0563

#define	PHY_CCA 0x803

#define	MAX_MSS_DENSITY_2T 0x13

#define	MAX_MSS_DENSITY_1T 0x0A

#define	RXDMA_AGG_EN BIT(7)

#define	RPWM PCI_RPWM

#define	ISO_MD2PP BIT(0)

#define	ISO_PA2PCIE BIT(3)

#define	ISO_PLL2MD BIT(4)

#define	ISO_PWC_DV2RP BIT(11)

#define	ISO_PWC_RV2RP BIT(12)

#define	FEN_MREGEN BIT(15)

#define	FEN_DCORE BIT(11)

#define	FEN_CPUEN BIT(10)

#define	PAD_HWPD_IDN BIT(22)

#define	SYS_CLKSEL_80M BIT(0)

#define	SYS_PS_CLKSEL BIT(1)

#define	SYS_CPU_CLKSEL BIT(2)

#define	SYS_MAC_CLK_EN BIT(11)

#define	SYS_SWHW_SEL BIT(14)

#define	SYS_FWHW_SEL BIT(15)

#define	CmdEEPROM_En BIT(5)

#define	CmdEERPOMSEL BIT(4)

#define	Cmd9346CR_9356SEL BIT(4)

#define	AFE_MBEN BIT(1)

#define	AFE_BGEN BIT(0)

#define	SPS1_SWEN BIT(1)

#define	SPS1_LDEN BIT(0)

#define	RF_EN BIT(0)

#define	RF_RSTB BIT(1)

#define	RF_SDMRSTB BIT(2)

#define	LDA15_EN BIT(0)

#define	LDV12_EN BIT(0)

#define	LDV12_SDBY BIT(1)

#define	XTAL_GATE_AFE BIT(10)

#define	APLL_EN BIT(0)

#define	AFR_CardBEn BIT(0)

#define	AFR_CLKRUN_SEL BIT(1)

#define	AFR_FuncRegEn BIT(2)

#define	APSDOFF_STATUS BIT(15)

#define	APSDOFF BIT(14)

#define	BBRSTN BIT(13)

#define	BB_GLB_RSTN BIT(12)

#define	SCHEDULE_EN BIT(10)

#define	MACRXEN BIT(9)

#define	MACTXEN BIT(8)

#define	DDMA_EN BIT(7)

#define	FW2HW_EN BIT(6)

#define	RXDMA_EN BIT(5)

#define	TXDMA_EN BIT(4)

#define	HCI_RXDMA_EN BIT(3)

#define	HCI_TXDMA_EN BIT(2)

#define	StopHCCA BIT(6)

#define	StopHigh BIT(5)

#define	StopMgt BIT(4)

#define	StopVO BIT(3)

#define	StopVI BIT(2)

#define	StopBE BIT(1)

#define	StopBK BIT(0)

#define	LBK_NORMAL 0x00

#define	LBK_MAC_LB (BIT(0) \| BIT(1) \| BIT(3))

#define	LBK_MAC_DLB (BIT(0) \| BIT(1))

#define	LBK_DMA_LB (BIT(0) \| BIT(1) \| BIT(2))

#define	TCP_OFDL_EN BIT(25)

#define	HWPC_TX_EN BIT(24)

#define	TXDMAPRE2FULL BIT(23)

#define	DISCW BIT(20)

#define	TCRICV BIT(19)

#define	CfendForm BIT(17)

#define	TCRCRC BIT(16)

#define	FAKE_IMEM_EN BIT(15)

#define	TSFRST BIT(9)

#define	TSFEN BIT(8)

#define	FWALLRDY

#define	FWRDY BIT(7)

#define	BASECHG BIT(6)

#define	IMEM BIT(5)

#define	DMEM_CODE_DONE BIT(4)

#define	EXT_IMEM_CHK_RPT BIT(3)

#define	EXT_IMEM_CODE_DONE BIT(2)

#define	IMEM_CHK_RPT BIT(1)

#define	IMEM_CODE_DONE BIT(0)

#define	IMEM_CODE_DONE BIT(0)

#define	IMEM_CHK_RPT BIT(1)

#define	EMEM_CODE_DONE BIT(2)

#define	EMEM_CHK_RPT BIT(3)

#define	DMEM_CODE_DONE BIT(4)

#define	IMEM_RDY BIT(5)

#define	BASECHG BIT(6)

#define	FWRDY BIT(7)

#define	LOAD_FW_READY

#define	TCR_TSFEN BIT(8)

#define	TCR_TSFRST BIT(9)

#define	TCR_FAKE_IMEM_EN BIT(15)

#define	TCR_CRC BIT(16)

#define	TCR_ICV BIT(19)

#define	TCR_DISCW BIT(20)

#define	TCR_HWPC_TX_EN BIT(24)

#define	TCR_TCP_OFDL_EN BIT(25)

#define	TXDMA_INIT_VALUE

#define	RCR_APPFCS BIT(31)

#define	RCR_DIS_ENC_2BYTE BIT(30)

#define	RCR_DIS_AES_2BYTE BIT(29)

#define	RCR_HTC_LOC_CTRL BIT(28)

#define	RCR_ENMBID BIT(27)

#define	RCR_RX_TCPOFDL_EN BIT(26)

#define	RCR_APP_PHYST_RXFF BIT(25)

#define	RCR_APP_PHYST_STAFF BIT(24)

#define	RCR_CBSSID BIT(23)

#define	RCR_APWRMGT BIT(22)

#define	RCR_ADD3 BIT(21)

#define	RCR_AMF BIT(20)

#define	RCR_ACF BIT(19)

#define	RCR_ADF BIT(18)

#define	RCR_APP_MIC BIT(17)

#define	RCR_APP_ICV BIT(16)

#define	RCR_RXFTH BIT(13)

#define	RCR_AICV BIT(12)

#define	RCR_RXDESC_LK_EN BIT(11)

#define	RCR_APP_BA_SSN BIT(6)

#define	RCR_ACRC32 BIT(5)

#define	RCR_RXSHFT_EN BIT(4)

#define	RCR_AB BIT(3)

#define	RCR_AM BIT(2)

#define	RCR_APM BIT(1)

#define	RCR_AAP BIT(0)

#define	RCR_MXDMA_OFFSET 8

#define	RCR_FIFO_OFFSET 13

#define	MSR_LINK_MASK ((1 << 0) \| (1 << 1))

#define	MSR_LINK_MANAGED 2

#define	MSR_LINK_NONE 0

#define	MSR_LINK_SHIFT 0

#define	MSR_LINK_ADHOC 1

#define	MSR_LINK_MASTER 3

#define	MSR_NOLINK 0x00

#define	MSR_ADHOC 0x01

#define	MSR_INFRA 0x02

#define	MSR_AP 0x03

#define	ENUART BIT(7)

#define	ENJTAG BIT(3)

#define	BTMODE (BIT(2) \| BIT(1))

#define	ENBT BIT(0)

#define	ENMBID BIT(7)

#define	BCNUM (BIT(6) \| BIT(5) \| BIT(4))

#define	USTIME_EDCA 0xFF00

#define	USTIME_TSF 0x00FF

#define	SIFS_TRX 0xFF00

#define	SIFS_CTX 0x00FF

#define	ENSWBCN BIT(15)

#define	DRVERLY_TU 0x0FF0

#define	DRVERLY_US 0x000F

#define	BCN_TCFG_CW_SHIFT 8

#define	BCN_TCFG_IFS 0

#define	RRSR_RSC_OFFSET 21

#define	RRSR_SHORT_OFFSET 23

#define	RRSR_RSC_BW_40M 0x600000

#define	RRSR_RSC_UPSUBCHNL 0x400000

#define	RRSR_RSC_LOWSUBCHNL 0x200000

#define	RRSR_SHORT 0x800000

#define	RRSR_1M BIT(0)

#define	RRSR_2M BIT(1)

#define	RRSR_5_5M BIT(2)

#define	RRSR_11M BIT(3)

#define	RRSR_6M BIT(4)

#define	RRSR_9M BIT(5)

#define	RRSR_12M BIT(6)

#define	RRSR_18M BIT(7)

#define	RRSR_24M BIT(8)

#define	RRSR_36M BIT(9)

#define	RRSR_48M BIT(10)

#define	RRSR_54M BIT(11)

#define	RRSR_MCS0 BIT(12)

#define	RRSR_MCS1 BIT(13)

#define	RRSR_MCS2 BIT(14)

#define	RRSR_MCS3 BIT(15)

#define	RRSR_MCS4 BIT(16)

#define	RRSR_MCS5 BIT(17)

#define	RRSR_MCS6 BIT(18)

#define	RRSR_MCS7 BIT(19)

#define	BRSR_AckShortPmb BIT(23)

#define	RATR_1M 0x00000001

#define	RATR_2M 0x00000002

#define	RATR_55M 0x00000004

#define	RATR_11M 0x00000008

#define	RATR_6M 0x00000010

#define	RATR_9M 0x00000020

#define	RATR_12M 0x00000040

#define	RATR_18M 0x00000080

#define	RATR_24M 0x00000100

#define	RATR_36M 0x00000200

#define	RATR_48M 0x00000400

#define	RATR_54M 0x00000800

#define	RATR_MCS0 0x00001000

#define	RATR_MCS1 0x00002000

#define	RATR_MCS2 0x00004000

#define	RATR_MCS3 0x00008000

#define	RATR_MCS4 0x00010000

#define	RATR_MCS5 0x00020000

#define	RATR_MCS6 0x00040000

#define	RATR_MCS7 0x00080000

#define	RATR_MCS8 0x00100000

#define	RATR_MCS9 0x00200000

#define	RATR_MCS10 0x00400000

#define	RATR_MCS11 0x00800000

#define	RATR_MCS12 0x01000000

#define	RATR_MCS13 0x02000000

#define	RATR_MCS14 0x04000000

#define	RATR_MCS15 0x08000000

#define	RATE_ALL_CCK

#define	RATE_ALL_OFDM_AG

#define	RATE_ALL_OFDM_1SS

#define	RATE_ALL_OFDM_2SS

#define	AC_PARAM_TXOP_LIMIT_OFFSET 16

#define	AC_PARAM_ECW_MAX_OFFSET 12

#define	AC_PARAM_ECW_MIN_OFFSET 8

#define	AC_PARAM_AIFS_OFFSET 0

#define	AcmHw_HwEn BIT(0)

#define	AcmHw_BeqEn BIT(1)

#define	AcmHw_ViqEn BIT(2)

#define	AcmHw_VoqEn BIT(3)

#define	AcmHw_BeqStatus BIT(4)

#define	AcmHw_ViqStatus BIT(5)

#define	AcmHw_VoqStatus BIT(6)

#define	RETRY_LIMIT_SHORT_SHIFT 8

#define	RETRY_LIMIT_LONG_SHIFT 0

#define	NAV_UPPER_EN BIT(16)

#define	NAV_UPPER 0xFF00

#define	NAV_RTSRST 0xFF

#define	BW_OPMODE_20MHZ BIT(2)

#define	BW_OPMODE_5G BIT(1)

#define	BW_OPMODE_11J BIT(0)

#define	RXERR_RPT_RST BIT(27)

#define	RXERR_OFDM_PPDU 0

#define	RXERR_OFDM_FALSE_ALARM 1

#define	RXERR_OFDM_MPDU_OK 2

#define	RXERR_OFDM_MPDU_FAIL 3

#define	RXERR_CCK_PPDU 4

#define	RXERR_CCK_FALSE_ALARM 5

#define	RXERR_CCK_MPDU_OK 6

#define	RXERR_CCK_MPDU_FAIL 7

#define	RXERR_HT_PPDU 8

#define	RXERR_HT_FALSE_ALARM 9

#define	RXERR_HT_MPDU_TOTAL 10

#define	RXERR_HT_MPDU_OK 11

#define	RXERR_HT_MPDU_FAIL 12

#define	RXERR_RX_FULL_DROP 15

#define	SCR_TXUSEDK BIT(0)

#define	SCR_RXUSEDK BIT(1)

#define	SCR_TXENCENABLE BIT(2)

#define	SCR_RXENCENABLE BIT(3)

#define	SCR_SKBYA2 BIT(4)

#define	SCR_NOSKMC BIT(5)

#define	CAM_VALID BIT(15)

#define	CAM_NOTVALID 0x0000

#define	CAM_USEDK BIT(5)

#define	CAM_NONE 0x0

#define	CAM_WEP40 0x01

#define	CAM_TKIP 0x02

#define	CAM_AES 0x04

#define	CAM_WEP104 0x05

#define	TOTAL_CAM_ENTRY 32

#define	HALF_CAM_ENTRY 16

#define	CAM_WRITE BIT(16)

#define	CAM_READ 0x00000000

#define	CAM_POLLINIG BIT(31)

#define	WOW_PMEN BIT(0)

#define	WOW_WOMEN BIT(1)

#define	WOW_MAGIC BIT(2)

#define	WOW_UWF BIT(3)

#define	GPIOMUX_EN BIT(3)

#define	GPIOSEL_GPIO 0

#define	GPIOSEL_PHYDBG 1

#define	GPIOSEL_BT 2

#define	GPIOSEL_WLANDBG 3

#define	GPIOSEL_GPIO_MASK (~(BIT(0)\|BIT(1)))

#define	HST_RDBUSY BIT(0)

#define	CPU_WTBUSY BIT(1)

#define	IMR8190_DISABLED 0x0

#define	IMR_CPUERR BIT(5)

#define	IMR_ATIMEND BIT(4)

#define	IMR_TBDOK BIT(3)

#define	IMR_TBDER BIT(2)

#define	IMR_BCNDMAINT8 BIT(1)

#define	IMR_BCNDMAINT7 BIT(0)

#define	IMR_BCNDMAINT6 BIT(31)

#define	IMR_BCNDMAINT5 BIT(30)

#define	IMR_BCNDMAINT4 BIT(29)

#define	IMR_BCNDMAINT3 BIT(28)

#define	IMR_BCNDMAINT2 BIT(27)

#define	IMR_BCNDMAINT1 BIT(26)

#define	IMR_BCNDOK8 BIT(25)

#define	IMR_BCNDOK7 BIT(24)

#define	IMR_BCNDOK6 BIT(23)

#define	IMR_BCNDOK5 BIT(22)

#define	IMR_BCNDOK4 BIT(21)

#define	IMR_BCNDOK3 BIT(20)

#define	IMR_BCNDOK2 BIT(19)

#define	IMR_BCNDOK1 BIT(18)

#define	IMR_TIMEOUT2 BIT(17)

#define	IMR_TIMEOUT1 BIT(16)

#define	IMR_TXFOVW BIT(15)

#define	IMR_PSTIMEOUT BIT(14)

#define	IMR_BCNINT BIT(13)

#define	IMR_RXFOVW BIT(12)

#define	IMR_RDU BIT(11)

#define	IMR_RXCMDOK BIT(10)

#define	IMR_BDOK BIT(9)

#define	IMR_HIGHDOK BIT(8)

#define	IMR_COMDOK BIT(7)

#define	IMR_MGNTDOK BIT(6)

#define	IMR_HCCADOK BIT(5)

#define	IMR_BKDOK BIT(4)

#define	IMR_BEDOK BIT(3)

#define	IMR_VIDOK BIT(2)

#define	IMR_VODOK BIT(1)

#define	IMR_ROK BIT(0)

#define	TPPOLL_BKQ BIT(0)

#define	TPPOLL_BEQ BIT(1)

#define	TPPOLL_VIQ BIT(2)

#define	TPPOLL_VOQ BIT(3)

#define	TPPOLL_BQ BIT(4)

#define	TPPOLL_CQ BIT(5)

#define	TPPOLL_MQ BIT(6)

#define	TPPOLL_HQ BIT(7)

#define	TPPOLL_HCCAQ BIT(8)

#define	TPPOLL_STOPBK BIT(9)

#define	TPPOLL_STOPBE BIT(10)

#define	TPPOLL_STOPVI BIT(11)

#define	TPPOLL_STOPVO BIT(12)

#define	TPPOLL_STOPMGT BIT(13)

#define	TPPOLL_STOPHIGH BIT(14)

#define	TPPOLL_STOPHCCA BIT(15)

#define	TPPOLL_SHIFT 8

#define	CCX_CMD_CLM_ENABLE BIT(0)

#define	CCX_CMD_NHM_ENABLE BIT(1)

#define	CCX_CMD_FUNCTION_ENABLE BIT(8)

#define	CCX_CMD_IGNORE_CCA BIT(9)

#define	CCX_CMD_IGNORE_TXON BIT(10)

#define	CCX_CLM_RESULT_READY BIT(16)

#define	CCX_NHM_RESULT_READY BIT(16)

#define	CCX_CMD_RESET 0x0

#define	HWSET_MAX_SIZE_92S 128

#define	EFUSE_MAX_SECTION 16

#define	EFUSE_REAL_CONTENT_LEN 512

#define	EFUSE_OOB_PROTECT_BYTES 15

#define	RTL8190_EEPROM_ID 0x8129

#define	EEPROM_HPON 0x02

#define	EEPROM_CLK 0x06

#define	EEPROM_TESTR 0x08

#define	EEPROM_VID 0x0A

#define	EEPROM_DID 0x0C

#define	EEPROM_SVID 0x0E

#define	EEPROM_SMID 0x10

#define	EEPROM_MAC_ADDR 0x12

#define	EEPROM_NODE_ADDRESS_BYTE_0 0x12

#define	EEPROM_PWDIFF 0x54

#define	EEPROM_TXPOWERBASE 0x50

#define	EEPROM_TX_PWR_INDEX_RANGE 28

#define	EEPROM_TX_PWR_HT20_DIFF 0x62

#define	DEFAULT_HT20_TXPWR_DIFF 2

#define	EEPROM_TX_PWR_OFDM_DIFF 0x65

#define	EEPROM_TXPWRGROUP 0x67

#define	EEPROM_REGULATORY 0x6D

#define	TX_PWR_SAFETY_CHK 0x6D

#define	EEPROM_TXPWINDEX_CCK_24G 0x5D

#define	EEPROM_TXPWINDEX_OFDM_24G 0x6B

#define	EEPROM_HT2T_CH1_A 0x6c

#define	EEPROM_HT2T_CH7_A 0x6d

#define	EEPROM_HT2T_CH13_A 0x6e

#define	EEPROM_HT2T_CH1_B 0x6f

#define	EEPROM_HT2T_CH7_B 0x70

#define	EEPROM_HT2T_CH13_B 0x71

#define	EEPROM_TSSI_A 0x74

#define	EEPROM_TSSI_B 0x75

#define	EEPROM_RFIND_POWERDIFF 0x76

#define	EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3

#define	EEPROM_THERMALMETER 0x77

#define	EEPROM_BLUETOOTH_COEXIST 0x78

#define	EEPROM_BLUETOOTH_TYPE 0x4f

#define	EEPROM_OPTIONAL 0x78

#define	EEPROM_WOWLAN 0x78

#define	EEPROM_CRYSTALCAP 0x79

#define	EEPROM_CHANNELPLAN 0x7B

#define	EEPROM_VERSION 0x7C

#define	EEPROM_CUSTOMID 0x7A

#define	EEPROM_BOARDTYPE 0x7E

#define	EEPROM_CHANNEL_PLAN_FCC 0x0

#define	EEPROM_CHANNEL_PLAN_IC 0x1

#define	EEPROM_CHANNEL_PLAN_ETSI 0x2

#define	EEPROM_CHANNEL_PLAN_SPAIN 0x3

#define	EEPROM_CHANNEL_PLAN_FRANCE 0x4

#define	EEPROM_CHANNEL_PLAN_MKK 0x5

#define	EEPROM_CHANNEL_PLAN_MKK1 0x6

#define	EEPROM_CHANNEL_PLAN_ISRAEL 0x7

#define	EEPROM_CHANNEL_PLAN_TELEC 0x8

#define	EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9

#define	EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA

#define	EEPROM_CHANNEL_PLAN_NCC 0xB

#define	EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80

#define	FW_DIG_DISABLE 0xfd00cc00

#define	FW_DIG_ENABLE 0xfd000000

#define	FW_DIG_HALT 0xfd000001

#define	FW_DIG_RESUME 0xfd000002

#define	FW_HIGH_PWR_DISABLE 0xfd000008

#define	FW_HIGH_PWR_ENABLE 0xfd000009

#define	FW_ADD_A2_ENTRY 0xfd000016

#define	FW_TXPWR_TRACK_ENABLE 0xfd000017

#define	FW_TXPWR_TRACK_DISABLE 0xfd000018

#define	FW_TXPWR_TRACK_THERMAL 0xfd000019

#define	FW_TXANT_SWITCH_ENABLE 0xfd000023

#define	FW_TXANT_SWITCH_DISABLE 0xfd000024

#define	FW_RA_INIT 0xfd000026

#define	FW_CTRL_DM_BY_DRIVER 0Xfd00002a

#define	FW_RA_IOT_BG_COMB 0xfd000030

#define	FW_RA_IOT_N_COMB 0xfd000031

#define	FW_RA_REFRESH 0xfd0000a0

#define	FW_RA_UPDATE_MASK 0xfd0000a2

#define	FW_RA_DISABLE 0xfd0000a4

#define	FW_RA_ACTIVE 0xfd0000a6

#define	FW_RA_DISABLE_RSSI_MASK 0xfd0000ac

#define	FW_RA_ENABLE_RSSI_MASK 0xfd0000ad

#define	FW_RA_RESET 0xfd0000af

#define	FW_DM_DISABLE 0xfd00aa00

#define	FW_IQK_ENABLE 0xf0000020

#define	FW_IQK_SUCCESS 0x0000dddd

#define	FW_IQK_FAIL 0x0000ffff

#define	FW_OP_FAILURE 0xffffffff

#define	FW_TX_FEEDBACK_NONE 0xfb000000

#define	FW_TX_FEEDBACK_DTM_ENABLE (FW_TX_FEEDBACK_NONE \| 0x1)

#define	FW_TX_FEEDBACK_CCX_ENABL (FW_TX_FEEDBACK_NONE \| 0x2)

#define	FW_BB_RESET_ENABLE 0xff00000d

#define	FW_BB_RESET_DISABLE 0xff00000e

#define	FW_CCA_CHK_ENABLE 0xff000011

#define	FW_CCK_RESET_CNT 0xff000013

#define	FW_LPS_ENTER 0xfe000010

#define	FW_LPS_LEAVE 0xfe000011

#define	FW_INDIRECT_READ 0xf2000000

#define	FW_INDIRECT_WRITE 0xf2000001

#define	FW_CHAN_SET 0xf3000001

#define	RFPC 0x5F

#define	RCR_9356SEL BIT(6)

#define	TCR_LRL_OFFSET 0

#define	TCR_SRL_OFFSET 8

#define	TCR_MXDMA_OFFSET 21

#define	TCR_SAT BIT(24)

#define	RCR_MXDMA_OFFSET 8

#define	RCR_FIFO_OFFSET 13

#define	RCR_OnlyErlPkt BIT(31)

#define	CWR 0xDC

#define	RETRYCTR 0xDE

#define	CPU_GEN_SYSTEM_RESET 0x00000001

#define	CCX_COMMAND_REG 0x890

#define	CLM_PERIOD_REG 0x894

#define	NHM_PERIOD_REG 0x896

#define	NHM_THRESHOLD0 0x898

#define	NHM_THRESHOLD1 0x899

#define	NHM_THRESHOLD2 0x89A

#define	NHM_THRESHOLD3 0x89B

#define	NHM_THRESHOLD4 0x89C

#define	NHM_THRESHOLD5 0x89D

#define	NHM_THRESHOLD6 0x89E

#define	CLM_RESULT_REG 0x8D0

#define	NHM_RESULT_REG 0x8D4

#define	NHM_RPI_COUNTER0 0x8D8

#define	NHM_RPI_COUNTER1 0x8D9

#define	NHM_RPI_COUNTER2 0x8DA

#define	NHM_RPI_COUNTER3 0x8DB

#define	NHM_RPI_COUNTER4 0x8DC

#define	NHM_RPI_COUNTER5 0x8DD

#define	NHM_RPI_COUNTER6 0x8DE

#define	NHM_RPI_COUNTER7 0x8DF

#define	HAL_8192S_HW_GPIO_OFF_BIT BIT(3)

#define	HAL_8192S_HW_GPIO_OFF_MASK 0xF7

#define	HAL_8192S_HW_GPIO_WPS_BIT BIT(4)

#define	RPMAC_RESET 0x100

#define	RPMAC_TXSTART 0x104

#define	RPMAC_TXLEGACYSIG 0x108

#define	RPMAC_TXHTSIG1 0x10c

#define	RPMAC_TXHTSIG2 0x110

#define	RPMAC_PHYDEBUG 0x114

#define	RPMAC_TXPACKETNNM 0x118

#define	RPMAC_TXIDLE 0x11c

#define	RPMAC_TXMACHEADER0 0x120

#define	RPMAC_TXMACHEADER1 0x124

#define	RPMAC_TXMACHEADER2 0x128

#define	RPMAC_TXMACHEADER3 0x12c

#define	RPMAC_TXMACHEADER4 0x130

#define	RPMAC_TXMACHEADER5 0x134

#define	RPMAC_TXDATATYPE 0x138

#define	RPMAC_TXRANDOMSEED 0x13c

#define	RPMAC_CCKPLCPPREAMBLE 0x140

#define	RPMAC_CCKPLCPHEADER 0x144

#define	RPMAC_CCKCRC16 0x148

#define	RPMAC_OFDMRXCRC32OK 0x170

#define	RPMAC_OFDMRXCRC32ER 0x174

#define	RPMAC_OFDMRXPARITYER 0x178

#define	RPMAC_OFDMRXCRC8ER 0x17c

#define	RPMAC_CCKCRXRC16ER 0x180

#define	RPMAC_CCKCRXRC32ER 0x184

#define	RPMAC_CCKCRXRC32OK 0x188

#define	RPMAC_TXSTATUS 0x18c

#define	RF_BB_CMD_ADDR 0x02c0

#define	RF_BB_CMD_DATA 0x02c4

#define	RFPGA0_RFMOD 0x800

#define	RFPGA0_TXINFO 0x804

#define	RFPGA0_PSDFUNCTION 0x808

#define	RFPGA0_TXGAINSTAGE 0x80c

#define	RFPGA0_RFTIMING1 0x810

#define	RFPGA0_RFTIMING2 0x814

#define	RFPGA0_XA_HSSIPARAMETER1 0x820

#define	RFPGA0_XA_HSSIPARAMETER2 0x824

#define	RFPGA0_XB_HSSIPARAMETER1 0x828

#define	RFPGA0_XB_HSSIPARAMETER2 0x82c

#define	RFPGA0_XC_HSSIPARAMETER1 0x830

#define	RFPGA0_XC_HSSIPARAMETER2 0x834

#define	RFPGA0_XD_HSSIPARAMETER1 0x838

#define	RFPGA0_XD_HSSIPARAMETER2 0x83c

#define	RFPGA0_XA_LSSIPARAMETER 0x840

#define	RFPGA0_XB_LSSIPARAMETER 0x844

#define	RFPGA0_XC_LSSIPARAMETER 0x848

#define	RFPGA0_XD_LSSIPARAMETER 0x84c

#define	RFPGA0_RFWAKEUP_PARAMETER 0x850

#define	RFPGA0_RFSLEEPUP_PARAMETER 0x854

#define	RFPGA0_XAB_SWITCHCONTROL 0x858

#define	RFPGA0_XCD_SWITCHCONTROL 0x85c

#define	RFPGA0_XA_RFINTERFACEOE 0x860

#define	RFPGA0_XB_RFINTERFACEOE 0x864

#define	RFPGA0_XC_RFINTERFACEOE 0x868

#define	RFPGA0_XD_RFINTERFACEOE 0x86c

#define	RFPGA0_XAB_RFINTERFACESW 0x870

#define	RFPGA0_XCD_RFINTERFACESW 0x874

#define	RFPGA0_XAB_RFPARAMETER 0x878

#define	RFPGA0_XCD_RFPARAMETER 0x87c

#define	RFPGA0_ANALOGPARAMETER1 0x880

#define	RFPGA0_ANALOGPARAMETER2 0x884

#define	RFPGA0_ANALOGPARAMETER3 0x888

#define	RFPGA0_ANALOGPARAMETER4 0x88c

#define	RFPGA0_XA_LSSIREADBACK 0x8a0

#define	RFPGA0_XB_LSSIREADBACK 0x8a4

#define	RFPGA0_XC_LSSIREADBACK 0x8a8

#define	RFPGA0_XD_LSSIREADBACK 0x8ac

#define	RFPGA0_PSDREPORT 0x8b4

#define	TRANSCEIVERA_HSPI_READBACK 0x8b8

#define	TRANSCEIVERB_HSPI_READBACK 0x8bc

#define	RFPGA0_XAB_RFINTERFACERB 0x8e0

#define	RFPGA0_XCD_RFINTERFACERB 0x8e4

#define	RFPGA1_RFMOD 0x900

#define	RFPGA1_TXBLOCK 0x904

#define	RFPGA1_DEBUGSELECT 0x908

#define	RFPGA1_TXINFO 0x90c

#define	RCCK0_SYSTEM 0xa00

#define	RCCK0_AFESETTING 0xa04

#define	RCCK0_CCA 0xa08

#define	RCCK0_RXAGC1 0xa0c

#define	RCCK0_RXAGC2 0xa10

#define	RCCK0_RXHP 0xa14

#define	RCCK0_DSPPARAMETER1 0xa18

#define	RCCK0_DSPPARAMETER2 0xa1c

#define	RCCK0_TXFILTER1 0xa20

#define	RCCK0_TXFILTER2 0xa24

#define	RCCK0_DEBUGPORT 0xa28

#define	RCCK0_FALSEALARMREPORT 0xa2c

#define	RCCK0_TRSSIREPORT 0xa50

#define	RCCK0_RXREPORT 0xa54

#define	RCCK0_FACOUNTERLOWER 0xa5c

#define	RCCK0_FACOUNTERUPPER 0xa58

#define	ROFDM0_LSTF 0xc00

#define	ROFDM0_TRXPATHENABLE 0xc04

#define	ROFDM0_TRMUXPAR 0xc08

#define	ROFDM0_TRSWISOLATION 0xc0c

#define	ROFDM0_XARXAFE 0xc10

#define	ROFDM0_XARXIQIMBALANCE 0xc14

#define	ROFDM0_XBRXAFE 0xc18

#define	ROFDM0_XBRXIQIMBALANCE 0xc1c

#define	ROFDM0_XCRXAFE 0xc20

#define	ROFDM0_XCRXIQIMBALANCE 0xc24

#define	ROFDM0_XDRXAFE 0xc28

#define	ROFDM0_XDRXIQIMBALANCE 0xc2c

#define	ROFDM0_RXDETECTOR1 0xc30

#define	ROFDM0_RXDETECTOR2 0xc34

#define	ROFDM0_RXDETECTOR3 0xc38

#define	ROFDM0_RXDETECTOR4 0xc3c

#define	ROFDM0_RXDSP 0xc40

#define	ROFDM0_CFO_AND_DAGC 0xc44

#define	ROFDM0_CCADROP_THRESHOLD 0xc48

#define	ROFDM0_ECCA_THRESHOLD 0xc4c

#define	ROFDM0_XAAGCCORE1 0xc50

#define	ROFDM0_XAAGCCORE2 0xc54

#define	ROFDM0_XBAGCCORE1 0xc58

#define	ROFDM0_XBAGCCORE2 0xc5c

#define	ROFDM0_XCAGCCORE1 0xc60

#define	ROFDM0_XCAGCCORE2 0xc64

#define	ROFDM0_XDAGCCORE1 0xc68

#define	ROFDM0_XDAGCCORE2 0xc6c

#define	ROFDM0_AGCPARAMETER1 0xc70

#define	ROFDM0_AGCPARAMETER2 0xc74

#define	ROFDM0_AGCRSSITABLE 0xc78

#define	ROFDM0_HTSTFAGC 0xc7c

#define	ROFDM0_XATXIQIMBALANCE 0xc80

#define	ROFDM0_XATXAFE 0xc84

#define	ROFDM0_XBTXIQIMBALANCE 0xc88

#define	ROFDM0_XBTXAFE 0xc8c

#define	ROFDM0_XCTXIQIMBALANCE 0xc90

#define	ROFDM0_XCTXAFE 0xc94

#define	ROFDM0_XDTXIQIMBALANCE 0xc98

#define	ROFDM0_XDTXAFE 0xc9c

#define	ROFDM0_RXHP_PARAMETER 0xce0

#define	ROFDM0_TXPSEUDO_NOISE_WGT 0xce4

#define	ROFDM0_FRAME_SYNC 0xcf0

#define	ROFDM0_DFSREPORT 0xcf4

#define	ROFDM0_TXCOEFF1 0xca4

#define	ROFDM0_TXCOEFF2 0xca8

#define	ROFDM0_TXCOEFF3 0xcac

#define	ROFDM0_TXCOEFF4 0xcb0

#define	ROFDM0_TXCOEFF5 0xcb4

#define	ROFDM0_TXCOEFF6 0xcb8

#define	ROFDM1_LSTF 0xd00

#define	ROFDM1_TRXPATHENABLE 0xd04

#define	ROFDM1_CFO 0xd08

#define	ROFDM1_CSI1 0xd10

#define	ROFDM1_SBD 0xd14

#define	ROFDM1_CSI2 0xd18

#define	ROFDM1_CFOTRACKING 0xd2c

#define	ROFDM1_TRXMESAURE1 0xd34

#define	ROFDM1_INTF_DET 0xd3c

#define	ROFDM1_PSEUDO_NOISESTATEAB 0xd50

#define	ROFDM1_PSEUDO_NOISESTATECD 0xd54

#define	ROFDM1_RX_PSEUDO_NOISE_WGT 0xd58

#define	ROFDM_PHYCOUNTER1 0xda0

#define	ROFDM_PHYCOUNTER2 0xda4

#define	ROFDM_PHYCOUNTER3 0xda8

#define	ROFDM_SHORT_CFOAB 0xdac

#define	ROFDM_SHORT_CFOCD 0xdb0

#define	ROFDM_LONG_CFOAB 0xdb4

#define	ROFDM_LONG_CFOCD 0xdb8

#define	ROFDM_TAIL_CFOAB 0xdbc

#define	ROFDM_TAIL_CFOCD 0xdc0

#define	ROFDM_PW_MEASURE1 0xdc4

#define	ROFDM_PW_MEASURE2 0xdc8

#define	ROFDM_BW_REPORT 0xdcc

#define	ROFDM_AGC_REPORT 0xdd0

#define	ROFDM_RXSNR 0xdd4

#define	ROFDM_RXEVMCSI 0xdd8

#define	ROFDM_SIG_REPORT 0xddc

#define	RTXAGC_RATE18_06 0xe00

#define	RTXAGC_RATE54_24 0xe04

#define	RTXAGC_CCK_MCS32 0xe08

#define	RTXAGC_MCS03_MCS00 0xe10

#define	RTXAGC_MCS07_MCS04 0xe14

#define	RTXAGC_MCS11_MCS08 0xe18

#define	RTXAGC_MCS15_MCS12 0xe1c

#define	RF_AC 0x00

#define	RF_IQADJ_G1 0x01

#define	RF_IQADJ_G2 0x02

#define	RF_POW_TRSW 0x05

#define	RF_GAIN_RX 0x06

#define	RF_GAIN_TX 0x07

#define	RF_TXM_IDAC 0x08

#define	RF_BS_IQGEN 0x0F

#define	RF_MODE1 0x10

#define	RF_MODE2 0x11

#define	RF_RX_AGC_HP 0x12

#define	RF_TX_AGC 0x13

#define	RF_BIAS 0x14

#define	RF_IPA 0x15

#define	RF_POW_ABILITY 0x17

#define	RF_MODE_AG 0x18

#define	RF_CHANNEL 0x18

#define	RF_CHNLBW 0x18

#define	RF_TOP 0x19

#define	RF_RX_G1 0x1A

#define	RF_RX_G2 0x1B

#define	RF_RX_BB2 0x1C

#define	RF_RX_BB1 0x1D

#define	RF_RCK1 0x1E

#define	RF_RCK2 0x1F

#define	RF_TX_G1 0x20

#define	RF_TX_G2 0x21

#define	RF_TX_G3 0x22

#define	RF_TX_BB1 0x23

#define	RF_T_METER 0x24

#define	RF_SYN_G1 0x25

#define	RF_SYN_G2 0x26

#define	RF_SYN_G3 0x27

#define	RF_SYN_G4 0x28

#define	RF_SYN_G5 0x29

#define	RF_SYN_G6 0x2A

#define	RF_SYN_G7 0x2B

#define	RF_SYN_G8 0x2C

#define	RF_RCK_OS 0x30

#define	RF_TXPA_G1 0x31

#define	RF_TXPA_G2 0x32

#define	RF_TXPA_G3 0x33

#define	BRFMOD 0x1

#define	BCCKEN 0x1000000

#define	BOFDMEN 0x2000000

#define	BXBTXAGC 0xf00

#define	BXCTXAGC 0xf000

#define	BXDTXAGC 0xf0000

#define	B3WIRE_DATALENGTH 0x800

#define	B3WIRE_ADDRESSLENGTH 0x400

#define	BRFSI_RFENV 0x10

#define	BLSSI_READADDRESS 0x7f800000

#define	BLSSI_READEDGE 0x80000000

#define	BLSSI_READBACK_DATA 0xfffff

#define	BADCLKPHASE 0x4000000

#define	BCCK_SIDEBAND 0x10

#define	BTX_AGCRATECCK 0x7f00

#define	MASKBYTE0 0xff

#define	MASKBYTE1 0xff00

#define	MASKBYTE2 0xff0000

#define	MASKBYTE3 0xff000000

#define	MASKHWORD 0xffff0000

#define	MASKLWORD 0x0000ffff

#define	MASKDWORD 0xffffffff

#define	MAKS12BITS 0xfffff

#define	MASK20BITS 0xfffff

#define	RFREG_OFFSET_MASK 0xfffff

Macro Definition Documentation

#define AC_PARAM_AIFS_OFFSET 0

Definition at line 591 of file reg.h.

#define AC_PARAM_ECW_MAX_OFFSET 12

Definition at line 589 of file reg.h.

#define AC_PARAM_ECW_MIN_OFFSET 8

Definition at line 590 of file reg.h.

#define AC_PARAM_TXOP_LIMIT_OFFSET 16

Definition at line 588 of file reg.h.

#define ACK_TIMEOUT 0x0091

Definition at line 90 of file reg.h.

#define ACMAVG 0x01E4

Definition at line 196 of file reg.h.

#define AcmHw_BeqEn BIT(1)

Definition at line 594 of file reg.h.

#define AcmHw_BeqStatus BIT(4)

Definition at line 597 of file reg.h.

#define AcmHw_HwEn BIT(0)

Definition at line 593 of file reg.h.

#define AcmHw_ViqEn BIT(2)

Definition at line 595 of file reg.h.

#define AcmHw_ViqStatus BIT(5)

Definition at line 598 of file reg.h.

#define AcmHw_VoqEn BIT(3)

Definition at line 596 of file reg.h.

#define AcmHw_VoqStatus BIT(6)

Definition at line 599 of file reg.h.

#define AcmHwCtrl 0x01E7

Definition at line 197 of file reg.h.

#define AFE_BGEN BIT(0)

Definition at line 358 of file reg.h.

#define AFE_MBEN BIT(1)

Definition at line 357 of file reg.h.

#define AFE_MISC 0x0010

Definition at line 39 of file reg.h.

#define AFE_PLL_CTRL 0x0028

Definition at line 49 of file reg.h.

#define AFE_XTAL_CTRL 0x0026

Definition at line 48 of file reg.h.

#define AFR_CardBEn BIT(0)

Definition at line 376 of file reg.h.

#define AFR_CLKRUN_SEL BIT(1)

Definition at line 377 of file reg.h.

#define AFR_FuncRegEn BIT(2)

Definition at line 378 of file reg.h.

#define AGGLEN_LMT_H 0x01A7

Definition at line 182 of file reg.h.

#define AGGLEN_LMT_L 0x01A8

Definition at line 183 of file reg.h.

#define AMPDU_MIN_SPACE 0x0237

Definition at line 222 of file reg.h.

#define APLL_EN BIT(0)

Definition at line 374 of file reg.h.

#define APSDOFF BIT(14)

Definition at line 381 of file reg.h.

#define APSDOFF_STATUS BIT(15)

Definition at line 380 of file reg.h.

#define ARFR0 0x0184

Definition at line 174 of file reg.h.

#define ARFR1 0x0188

Definition at line 175 of file reg.h.

#define ARFR2 0x018C

Definition at line 176 of file reg.h.

#define ARFR3 0x0190

Definition at line 177 of file reg.h.

#define ARFR4 0x0194

Definition at line 178 of file reg.h.

#define ARFR5 0x0198

Definition at line 179 of file reg.h.

#define ARFR6 0x019C

Definition at line 180 of file reg.h.

#define ARFR7 0x01A0

Definition at line 181 of file reg.h.

#define ATIMWND 0x0096

Definition at line 93 of file reg.h.

#define B3WIRE_ADDRESSLENGTH 0x400

Definition at line 1159 of file reg.h.

#define B3WIRE_DATALENGTH 0x800

Definition at line 1158 of file reg.h.

#define BACAMCMD 0x0204

Definition at line 207 of file reg.h.

#define BACAMCONTENT 0x0208

Definition at line 208 of file reg.h.

#define BADCLKPHASE 0x4000000

Definition at line 1167 of file reg.h.

#define BASECHG BIT(6)

Definition at line 434 of file reg.h.

#define BASECHG BIT(6)

Definition at line 434 of file reg.h.

#define BB_GLB_RSTN BIT(12)

Definition at line 383 of file reg.h.

#define BBRSTN BIT(13)

Definition at line 382 of file reg.h.

#define BCCK_SIDEBAND 0x10

Definition at line 1169 of file reg.h.

#define BCCKEN 0x1000000

Definition at line 1151 of file reg.h.

#define BCN_DMATIME 0x009A

Definition at line 95 of file reg.h.

#define BCN_DRV_EARLY_INT 0x0098

Definition at line 94 of file reg.h.

#define BCN_ERR_THRESH 0x009C

Definition at line 96 of file reg.h.

#define BCN_INTERVAL 0x0094

Definition at line 92 of file reg.h.

#define BCN_TCFG_CW_SHIFT 8

Definition at line 513 of file reg.h.

#define BCN_TCFG_IFS 0

Definition at line 514 of file reg.h.

#define BCNQ_CTRL 0x0120

Definition at line 152 of file reg.h.

#define BCNTCFG 0x01E0

Definition at line 194 of file reg.h.

#define BCNUM (BIT(6) | BIT(5) | BIT(4))

Definition at line 502 of file reg.h.

#define BE_ADMTM 0x01F0

Definition at line 200 of file reg.h.

#define BETID0_CTRL 0x0140

Definition at line 160 of file reg.h.

#define BETID3_CTRL 0x013c

Definition at line 159 of file reg.h.

#define BIST 0x0310

Definition at line 265 of file reg.h.

#define BKTID1_CTRL 0x0148

Definition at line 162 of file reg.h.

#define BKTID2_CTRL 0x0144

Definition at line 161 of file reg.h.

#define BLSSI_READADDRESS 0x7f800000

Definition at line 1163 of file reg.h.

#define BLSSI_READBACK_DATA 0xfffff

Definition at line 1165 of file reg.h.

#define BLSSI_READEDGE 0x80000000

Definition at line 1164 of file reg.h.

#define BOFDMEN 0x2000000

Definition at line 1152 of file reg.h.

#define BRFMOD 0x1

Definition at line 1150 of file reg.h.

#define BRFSI_RFENV 0x10

Definition at line 1161 of file reg.h.

#define BRSR_AckShortPmb BIT(23)

Definition at line 542 of file reg.h.

#define BSSIDR 0x0058

Definition at line 72 of file reg.h.

#define BTMODE (BIT(2) | BIT(1))

Definition at line 498 of file reg.h.

#define BTX_AGCRATECCK 0x7f00

Definition at line 1171 of file reg.h.

#define BUILDTIME 0x0074

Definition at line 77 of file reg.h.

#define BUILDUSER 0x0078

Definition at line 78 of file reg.h.

#define BW_OPMODE 0x0203

Definition at line 206 of file reg.h.

#define BW_OPMODE_11J BIT(0)

Definition at line 610 of file reg.h.

#define BW_OPMODE_20MHZ BIT(2)

Definition at line 608 of file reg.h.

#define BW_OPMODE_5G BIT(1)

Definition at line 609 of file reg.h.

#define BXBTXAGC 0xf00

Definition at line 1154 of file reg.h.

#define BXCTXAGC 0xf000

Definition at line 1155 of file reg.h.

#define BXDTXAGC 0xf0000

Definition at line 1156 of file reg.h.

#define C2HCMD_UDT_ADDR 0x00C2

Definition at line 125 of file reg.h.

#define C2HCMD_UDT_SIZE 0x00C0

Definition at line 124 of file reg.h.

#define C2HFF_RDPTR 0x00E8

Definition at line 136 of file reg.h.

#define C2HFF_WTPTR 0x00EC

Definition at line 137 of file reg.h.

#define CAM_AES 0x04

Definition at line 642 of file reg.h.

#define CAM_NONE 0x0

Definition at line 639 of file reg.h.

#define CAM_NOTVALID 0x0000

Definition at line 636 of file reg.h.

#define CAM_POLLINIG BIT(31)

Definition at line 650 of file reg.h.

#define CAM_READ 0x00000000

Definition at line 649 of file reg.h.

#define CAM_TKIP 0x02

Definition at line 641 of file reg.h.

#define CAM_USEDK BIT(5)

Definition at line 637 of file reg.h.

#define CAM_VALID BIT(15)

Definition at line 635 of file reg.h.

#define CAM_WEP104 0x05

Definition at line 643 of file reg.h.

#define CAM_WEP40 0x01

Definition at line 640 of file reg.h.

#define CAM_WRITE BIT(16)

Definition at line 648 of file reg.h.

#define CBUS_ERR_ADDR 0x0350

Definition at line 282 of file reg.h.

#define CBUS_ERR_CMD 0x0354

Definition at line 283 of file reg.h.

#define CBUS_ERR_DATA_H 0x035C

Definition at line 285 of file reg.h.

#define CBUS_ERR_DATA_L 0x0358

Definition at line 284 of file reg.h.

#define CCK_TXAGC 0x01C8

Definition at line 187 of file reg.h.

#define CCX_CLM_RESULT_READY BIT(16)

Definition at line 730 of file reg.h.

#define CCX_CMD_CLM_ENABLE BIT(0)

Definition at line 725 of file reg.h.

#define CCX_CMD_FUNCTION_ENABLE BIT(8)

Definition at line 727 of file reg.h.

#define CCX_CMD_IGNORE_CCA BIT(9)

Definition at line 728 of file reg.h.

#define CCX_CMD_IGNORE_TXON BIT(10)

Definition at line 729 of file reg.h.

#define CCX_CMD_NHM_ENABLE BIT(1)

Definition at line 726 of file reg.h.

#define CCX_CMD_RESET 0x0

Definition at line 732 of file reg.h.

#define CCX_COMMAND_REG 0x890

Definition at line 863 of file reg.h.

#define CCX_NHM_RESULT_READY BIT(16)

Definition at line 731 of file reg.h.

#define CFEND_TH 0x0236

Definition at line 221 of file reg.h.

#define CfendForm BIT(17)

Definition at line 412 of file reg.h.

#define CLM_PERIOD_REG 0x894

Definition at line 864 of file reg.h.

#define CLM_RESULT 0x0227

Definition at line 217 of file reg.h.

#define CLM_RESULT_REG 0x8D0

Definition at line 874 of file reg.h.

#define Cmd9346CR_9356SEL BIT(4)

Definition at line 355 of file reg.h.

#define CmdEEPROM_En BIT(5)

Definition at line 353 of file reg.h.

#define CmdEERPOMSEL BIT(4)

Definition at line 354 of file reg.h.

#define CMDQ_CTRL 0x014c

Definition at line 163 of file reg.h.

#define CMDR 0x0040

Definition at line 58 of file reg.h.

#define CPU_GEN_SYSTEM_RESET 0x00000001

Definition at line 861 of file reg.h.

#define CPU_WTBUSY BIT(1)

Definition at line 665 of file reg.h.

#define CPUCAUSE 0x031C

Definition at line 268 of file reg.h.

#define CPUINST 0x0318

Definition at line 267 of file reg.h.

#define CWR 0xDC

Definition at line 858 of file reg.h.

#define CWRR 0x01E2

Definition at line 195 of file reg.h.

#define DARFRC 0x01B0

Definition at line 184 of file reg.h.

#define DBG_PORT 0x003A

Definition at line 53 of file reg.h.

#define DBG_PORT_SWITCH 0x003A

Definition at line 264 of file reg.h.

#define DBI_CTRL 0x0548

Definition at line 313 of file reg.h.

#define DBI_RDATA 0x0544

Definition at line 312 of file reg.h.

#define DBI_WDATA 0x0540

Definition at line 311 of file reg.h.

#define DBS 0x0314

Definition at line 266 of file reg.h.

#define DDMA_EN BIT(7)

Definition at line 387 of file reg.h.

#define DEFAULT_HT20_TXPWR_DIFF 2

Definition at line 759 of file reg.h.

#define DISCW BIT(20)

Definition at line 410 of file reg.h.

#define DMEM_CODE_DONE BIT(4)

Definition at line 432 of file reg.h.

#define DMEM_CODE_DONE BIT(4)

Definition at line 432 of file reg.h.

#define DPLL 0x034A

Definition at line 281 of file reg.h.

#define DPS_TIMER 0x003C

Definition at line 54 of file reg.h.

#define DRVERLY_TU 0x0FF0

Definition at line 511 of file reg.h.

#define DRVERLY_US 0x000F

Definition at line 512 of file reg.h.

#define EDCAPARA_BE 0x01D8

Definition at line 192 of file reg.h.

#define EDCAPARA_BK 0x01DC

Definition at line 193 of file reg.h.

#define EDCAPARA_VI 0x01D4

Definition at line 191 of file reg.h.

#define EDCAPARA_VO 0x01D0

Definition at line 190 of file reg.h.

#define EE_VPD 0x000C

Definition at line 38 of file reg.h.

#define EEPROM_BLUETOOTH_COEXIST 0x78

Definition at line 782 of file reg.h.

#define EEPROM_BLUETOOTH_TYPE 0x4f

Definition at line 783 of file reg.h.

#define EEPROM_BOARDTYPE 0x7E

Definition at line 792 of file reg.h.

#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80

Definition at line 806 of file reg.h.

#define EEPROM_CHANNEL_PLAN_ETSI 0x2

Definition at line 796 of file reg.h.

#define EEPROM_CHANNEL_PLAN_FCC 0x0

Definition at line 794 of file reg.h.

#define EEPROM_CHANNEL_PLAN_FRANCE 0x4

Definition at line 798 of file reg.h.

#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9

Definition at line 803 of file reg.h.

#define EEPROM_CHANNEL_PLAN_IC 0x1

Definition at line 795 of file reg.h.

#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7

Definition at line 801 of file reg.h.

#define EEPROM_CHANNEL_PLAN_MKK 0x5

Definition at line 799 of file reg.h.

#define EEPROM_CHANNEL_PLAN_MKK1 0x6

Definition at line 800 of file reg.h.

#define EEPROM_CHANNEL_PLAN_NCC 0xB

Definition at line 805 of file reg.h.

#define EEPROM_CHANNEL_PLAN_SPAIN 0x3

Definition at line 797 of file reg.h.

#define EEPROM_CHANNEL_PLAN_TELEC 0x8

Definition at line 802 of file reg.h.

#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA

Definition at line 804 of file reg.h.

#define EEPROM_CHANNELPLAN 0x7B

Definition at line 789 of file reg.h.

#define EEPROM_CLK 0x06

Definition at line 742 of file reg.h.

#define EEPROM_CRYSTALCAP 0x79

Definition at line 788 of file reg.h.

#define EEPROM_CUSTOMID 0x7A

Definition at line 791 of file reg.h.

#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3

Definition at line 779 of file reg.h.

#define EEPROM_DID 0x0C

Definition at line 746 of file reg.h.

#define EEPROM_HPON 0x02

Definition at line 741 of file reg.h.

#define EEPROM_HT2T_CH13_A 0x6e

Definition at line 770 of file reg.h.

#define EEPROM_HT2T_CH13_B 0x71

Definition at line 773 of file reg.h.

#define EEPROM_HT2T_CH1_A 0x6c

Definition at line 768 of file reg.h.

#define EEPROM_HT2T_CH1_B 0x6f

Definition at line 771 of file reg.h.

#define EEPROM_HT2T_CH7_A 0x6d

Definition at line 769 of file reg.h.

#define EEPROM_HT2T_CH7_B 0x70

Definition at line 772 of file reg.h.

#define EEPROM_MAC_ADDR 0x12

Definition at line 750 of file reg.h.

#define EEPROM_NODE_ADDRESS_BYTE_0 0x12

Definition at line 751 of file reg.h.

#define EEPROM_OPTIONAL 0x78

Definition at line 785 of file reg.h.

#define EEPROM_PWDIFF 0x54

Definition at line 753 of file reg.h.

#define EEPROM_REGULATORY 0x6D

Definition at line 763 of file reg.h.

#define EEPROM_RFIND_POWERDIFF 0x76

Definition at line 778 of file reg.h.

#define EEPROM_SMID 0x10

Definition at line 748 of file reg.h.

#define EEPROM_SVID 0x0E

Definition at line 747 of file reg.h.

#define EEPROM_TESTR 0x08

Definition at line 743 of file reg.h.

#define EEPROM_THERMALMETER 0x77

Definition at line 781 of file reg.h.

#define EEPROM_TSSI_A 0x74

Definition at line 775 of file reg.h.

#define EEPROM_TSSI_B 0x75

Definition at line 776 of file reg.h.

#define EEPROM_TX_PWR_HT20_DIFF 0x62

Definition at line 758 of file reg.h.

#define EEPROM_TX_PWR_INDEX_RANGE 28

Definition at line 756 of file reg.h.

#define EEPROM_TX_PWR_OFDM_DIFF 0x65

Definition at line 760 of file reg.h.

#define EEPROM_TXPOWERBASE 0x50

Definition at line 755 of file reg.h.

#define EEPROM_TXPWINDEX_CCK_24G 0x5D

Definition at line 766 of file reg.h.

#define EEPROM_TXPWINDEX_OFDM_24G 0x6B

Definition at line 767 of file reg.h.

#define EEPROM_TXPWRGROUP 0x67

Definition at line 762 of file reg.h.

#define EEPROM_VERSION 0x7C

Definition at line 790 of file reg.h.

#define EEPROM_VID 0x0A

Definition at line 745 of file reg.h.

#define EEPROM_WOWLAN 0x78

Definition at line 786 of file reg.h.

#define EFUSE_MAX_SECTION 16

Definition at line 736 of file reg.h.

#define EFUSE_OOB_PROTECT_BYTES 15

Definition at line 738 of file reg.h.

#define EFUSE_REAL_CONTENT_LEN 512

Definition at line 737 of file reg.h.

#define EIFSTR 0x0092

Definition at line 91 of file reg.h.

#define EMEM_CHK_RPT BIT(3)

Definition at line 431 of file reg.h.

#define EMEM_CODE_DONE BIT(2)

Definition at line 430 of file reg.h.

#define ENBT BIT(0)

Definition at line 499 of file reg.h.

#define ENJTAG BIT(3)

Definition at line 497 of file reg.h.

#define ENMBID BIT(7)

Definition at line 501 of file reg.h.

#define ENSWBCN BIT(15)

Definition at line 510 of file reg.h.

#define ENUART BIT(7)

Definition at line 496 of file reg.h.

#define EPROM_CMD 0x000A

Definition at line 37 of file reg.h.

#define EXT_IMEM_CHK_RPT BIT(3)

Definition at line 424 of file reg.h.

#define EXT_IMEM_CODE_DONE BIT(2)

Definition at line 425 of file reg.h.

#define FAKE_IMEM_EN BIT(15)

Definition at line 414 of file reg.h.

#define FDLOCKTURN0 0x033C

Definition at line 277 of file reg.h.

#define FDLOCKTURN1 0x033D

Definition at line 278 of file reg.h.

#define FEN_CPUEN BIT(10)

Definition at line 342 of file reg.h.

#define FEN_DCORE BIT(11)

Definition at line 341 of file reg.h.

#define FEN_MREGEN BIT(15)

Definition at line 340 of file reg.h.

#define FIFOPAGE1 0x00C4

Definition at line 126 of file reg.h.

#define FIFOPAGE2 0x00C8

Definition at line 127 of file reg.h.

#define FIFOPAGE3 0x00CC

Definition at line 128 of file reg.h.

#define FIFOPAGE4 0x00D0

Definition at line 129 of file reg.h.

#define FIFOPAGE5 0x00D4

Definition at line 130 of file reg.h.

#define FW2HW_EN BIT(6)

Definition at line 388 of file reg.h.

#define FW_ADD_A2_ENTRY 0xfd000016

Definition at line 814 of file reg.h.

#define FW_BB_RESET_DISABLE 0xff00000e

Definition at line 840 of file reg.h.

#define FW_BB_RESET_ENABLE 0xff00000d

Definition at line 839 of file reg.h.

#define FW_CCA_CHK_ENABLE 0xff000011

Definition at line 841 of file reg.h.

#define FW_CCK_RESET_CNT 0xff000013

Definition at line 842 of file reg.h.

#define FW_CHAN_SET 0xf3000001

Definition at line 847 of file reg.h.

#define FW_CTRL_DM_BY_DRIVER 0Xfd00002a

Definition at line 821 of file reg.h.

#define FW_DIG_DISABLE 0xfd00cc00

Definition at line 808 of file reg.h.

#define FW_DIG_ENABLE 0xfd000000

Definition at line 809 of file reg.h.

#define FW_DIG_HALT 0xfd000001

Definition at line 810 of file reg.h.

#define FW_DIG_RESUME 0xfd000002

Definition at line 811 of file reg.h.

#define FW_DM_DISABLE 0xfd00aa00

Definition at line 831 of file reg.h.

#define FW_HIGH_PWR_DISABLE 0xfd000008

Definition at line 812 of file reg.h.

#define FW_HIGH_PWR_ENABLE 0xfd000009

Definition at line 813 of file reg.h.

#define FW_INDIRECT_READ 0xf2000000

Definition at line 845 of file reg.h.

#define FW_INDIRECT_WRITE 0xf2000001

Definition at line 846 of file reg.h.

#define FW_IQK_ENABLE 0xf0000020

Definition at line 832 of file reg.h.

#define FW_IQK_FAIL 0x0000ffff

Definition at line 834 of file reg.h.

#define FW_IQK_SUCCESS 0x0000dddd

Definition at line 833 of file reg.h.

#define FW_LPS_ENTER 0xfe000010

Definition at line 843 of file reg.h.

#define FW_LPS_LEAVE 0xfe000011

Definition at line 844 of file reg.h.

#define FW_OP_FAILURE 0xffffffff

Definition at line 835 of file reg.h.

#define FW_RA_ACTIVE 0xfd0000a6

Definition at line 827 of file reg.h.

#define FW_RA_DISABLE 0xfd0000a4

Definition at line 826 of file reg.h.

#define FW_RA_DISABLE_RSSI_MASK 0xfd0000ac

Definition at line 828 of file reg.h.

#define FW_RA_ENABLE_RSSI_MASK 0xfd0000ad

Definition at line 829 of file reg.h.

#define FW_RA_INIT 0xfd000026

Definition at line 820 of file reg.h.

#define FW_RA_IOT_BG_COMB 0xfd000030

Definition at line 822 of file reg.h.

#define FW_RA_IOT_N_COMB 0xfd000031

Definition at line 823 of file reg.h.

#define FW_RA_REFRESH 0xfd0000a0

Definition at line 824 of file reg.h.

#define FW_RA_RESET 0xfd0000af

Definition at line 830 of file reg.h.

#define FW_RA_UPDATE_MASK 0xfd0000a2

Definition at line 825 of file reg.h.

#define FW_RPT_REG 0x02c4

Definition at line 245 of file reg.h.

#define FW_RSVD_PG_CRTL 0x00D8

Definition at line 131 of file reg.h.

#define FW_TX_FEEDBACK_CCX_ENABL (FW_TX_FEEDBACK_NONE | 0x2)

Definition at line 838 of file reg.h.

#define FW_TX_FEEDBACK_DTM_ENABLE (FW_TX_FEEDBACK_NONE | 0x1)

Definition at line 837 of file reg.h.

#define FW_TX_FEEDBACK_NONE 0xfb000000

Definition at line 836 of file reg.h.

#define FW_TXANT_SWITCH_DISABLE 0xfd000024

Definition at line 819 of file reg.h.

#define FW_TXANT_SWITCH_ENABLE 0xfd000023

Definition at line 818 of file reg.h.

#define FW_TXPWR_TRACK_DISABLE 0xfd000018

Definition at line 816 of file reg.h.

#define FW_TXPWR_TRACK_ENABLE 0xfd000017

Definition at line 815 of file reg.h.

#define FW_TXPWR_TRACK_THERMAL 0xfd000019

Definition at line 817 of file reg.h.

#define FWALLRDY

Value:

(BIT(0) | BIT(1) | BIT(2) | \
                        BIT(3) | BIT(4) | BIT(5) | \
                        BIT(6) | BIT(7))

Definition at line 417 of file reg.h.

#define FWDLY 0x0211

Definition at line 212 of file reg.h.

#define FWRDY BIT(7)

Definition at line 435 of file reg.h.

#define FWRDY BIT(7)

Definition at line 435 of file reg.h.

#define GPIO_IN_SE 0x02EC

Definition at line 251 of file reg.h.

#define GPIO_IO_SEL 0x02EE

Definition at line 252 of file reg.h.

#define GPIOMUX_EN BIT(3)

Definition at line 657 of file reg.h.

#define GPIOSEL_BT 2

Definition at line 660 of file reg.h.

#define GPIOSEL_GPIO 0

Definition at line 658 of file reg.h.

#define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))

Definition at line 662 of file reg.h.

#define GPIOSEL_PHYDBG 1

Definition at line 659 of file reg.h.

#define GPIOSEL_WLANDBG 3

Definition at line 661 of file reg.h.

#define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)

Definition at line 885 of file reg.h.

#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7

Definition at line 886 of file reg.h.

#define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)

Definition at line 887 of file reg.h.

#define HALF_CAM_ENTRY 16

Definition at line 646 of file reg.h.

#define HCI_RXDMA_EN BIT(3)

Definition at line 391 of file reg.h.

#define HCI_TXDMA_EN BIT(2)

Definition at line 392 of file reg.h.

#define HDA 0x0520

Definition at line 303 of file reg.h.

#define HIQ_CTRL 0x0128

Definition at line 154 of file reg.h.

#define HST_RDBUSY BIT(0)

Definition at line 664 of file reg.h.

#define HWPC_RX_CTRL 0x0218

Definition at line 213 of file reg.h.

#define HWPC_TX_EN BIT(24)

Definition at line 408 of file reg.h.

#define HWSET_MAX_SIZE_92S 128

Definition at line 735 of file reg.h.

#define HWVID 0x005E

Definition at line 73 of file reg.h.

#define IDR0 MACIDR0

Definition at line 80 of file reg.h.

#define IDR4 MACIDR4

Definition at line 81 of file reg.h.

#define IMEM BIT(5)

Definition at line 422 of file reg.h.

#define IMEM_CHK_RPT BIT(1)

Definition at line 429 of file reg.h.

#define IMEM_CHK_RPT BIT(1)

Definition at line 429 of file reg.h.

#define IMEM_CODE_DONE BIT(0)

Definition at line 428 of file reg.h.

#define IMEM_CODE_DONE BIT(0)

Definition at line 428 of file reg.h.

#define IMEM_RDY BIT(5)

Definition at line 433 of file reg.h.

#define IMR8190_DISABLED 0x0

Definition at line 667 of file reg.h.

#define IMR_ATIMEND BIT(4)

Definition at line 669 of file reg.h.

#define IMR_BCNDMAINT1 BIT(26)

Definition at line 679 of file reg.h.

#define IMR_BCNDMAINT2 BIT(27)

Definition at line 678 of file reg.h.

#define IMR_BCNDMAINT3 BIT(28)

Definition at line 677 of file reg.h.

#define IMR_BCNDMAINT4 BIT(29)

Definition at line 676 of file reg.h.

#define IMR_BCNDMAINT5 BIT(30)

Definition at line 675 of file reg.h.

#define IMR_BCNDMAINT6 BIT(31)

Definition at line 674 of file reg.h.

#define IMR_BCNDMAINT7 BIT(0)

Definition at line 673 of file reg.h.

#define IMR_BCNDMAINT8 BIT(1)

Definition at line 672 of file reg.h.

#define IMR_BCNDOK1 BIT(18)

Definition at line 687 of file reg.h.

#define IMR_BCNDOK2 BIT(19)

Definition at line 686 of file reg.h.

#define IMR_BCNDOK3 BIT(20)

Definition at line 685 of file reg.h.

#define IMR_BCNDOK4 BIT(21)

Definition at line 684 of file reg.h.

#define IMR_BCNDOK5 BIT(22)

Definition at line 683 of file reg.h.

#define IMR_BCNDOK6 BIT(23)

Definition at line 682 of file reg.h.

#define IMR_BCNDOK7 BIT(24)

Definition at line 681 of file reg.h.

#define IMR_BCNDOK8 BIT(25)

Definition at line 680 of file reg.h.

#define IMR_BCNINT BIT(13)

Definition at line 692 of file reg.h.

#define IMR_BDOK BIT(9)

Definition at line 696 of file reg.h.

#define IMR_BEDOK BIT(3)

Definition at line 702 of file reg.h.

#define IMR_BKDOK BIT(4)

Definition at line 701 of file reg.h.

#define IMR_COMDOK BIT(7)

Definition at line 698 of file reg.h.

#define IMR_CPUERR BIT(5)

Definition at line 668 of file reg.h.

#define IMR_HCCADOK BIT(5)

Definition at line 700 of file reg.h.

#define IMR_HIGHDOK BIT(8)

Definition at line 697 of file reg.h.

#define IMR_MGNTDOK BIT(6)

Definition at line 699 of file reg.h.

#define IMR_PSTIMEOUT BIT(14)

Definition at line 691 of file reg.h.

#define IMR_RDU BIT(11)

Definition at line 694 of file reg.h.

#define IMR_ROK BIT(0)

Definition at line 705 of file reg.h.

#define IMR_RXCMDOK BIT(10)

Definition at line 695 of file reg.h.

#define IMR_RXFOVW BIT(12)

Definition at line 693 of file reg.h.

#define IMR_TBDER BIT(2)

Definition at line 671 of file reg.h.

#define IMR_TBDOK BIT(3)

Definition at line 670 of file reg.h.

#define IMR_TIMEOUT1 BIT(16)

Definition at line 689 of file reg.h.

#define IMR_TIMEOUT2 BIT(17)

Definition at line 688 of file reg.h.

#define IMR_TXFOVW BIT(15)

Definition at line 690 of file reg.h.

#define IMR_VIDOK BIT(2)

Definition at line 703 of file reg.h.

#define IMR_VODOK BIT(1)

Definition at line 704 of file reg.h.

#define INIMCS_SEL 0x0160

Definition at line 170 of file reg.h.

#define INIRTSMCS_SEL 0x0180

Definition at line 172 of file reg.h.

#define INTA_MASK 0x0300

Definition at line 260 of file reg.h.

#define INTM 0x033A

Definition at line 276 of file reg.h.

#define INTMTU 0x0338

Definition at line 275 of file reg.h.

#define ISO_MD2PP BIT(0)

Definition at line 333 of file reg.h.

#define ISO_PA2PCIE BIT(3)

Definition at line 334 of file reg.h.

#define ISO_PLL2MD BIT(4)

Definition at line 335 of file reg.h.

#define ISO_PWC_DV2RP BIT(11)

Definition at line 336 of file reg.h.

#define ISO_PWC_RV2RP BIT(12)

Definition at line 337 of file reg.h.

#define ISR 0x0308

Definition at line 261 of file reg.h.

#define LBDLY 0x0210

Definition at line 211 of file reg.h.

#define LBK_DMA_LB (BIT(0) | BIT(1) | BIT(2))

Definition at line 405 of file reg.h.

#define LBK_MAC_DLB (BIT(0) | BIT(1))

Definition at line 404 of file reg.h.

#define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3))

Definition at line 403 of file reg.h.

#define LBK_NORMAL 0x00

Definition at line 402 of file reg.h.

#define LBKMD_SEL 0x0043

Definition at line 60 of file reg.h.

#define LBUS_ADDR_MASK 0x0368

Definition at line 291 of file reg.h.

#define LBUS_ERR_ADDR 0x0320

Definition at line 269 of file reg.h.

#define LBUS_ERR_CMD 0x0324

Definition at line 270 of file reg.h.

#define LBUS_ERR_DATA_H 0x032C

Definition at line 272 of file reg.h.

#define LBUS_ERR_DATA_L 0x0328

Definition at line 271 of file reg.h.

#define LBUS_MON_ADDR 0x0364

Definition at line 290 of file reg.h.

#define LD_RQPN 0x00AB

Definition at line 112 of file reg.h.

#define LDA15_EN BIT(0)

Definition at line 367 of file reg.h.

#define LDO_USB_SDIO 0x0023

Definition at line 46 of file reg.h.

#define LDOA15_CTRL 0x0020

Definition at line 43 of file reg.h.

#define LDOHCI12_CTRL 0x0022

Definition at line 45 of file reg.h.

#define LDOV12D_CTRL 0x0021

Definition at line 44 of file reg.h.

#define LDV12_EN BIT(0)

Definition at line 369 of file reg.h.

#define LDV12_SDBY BIT(1)

Definition at line 370 of file reg.h.

#define LEDCFG 0x02F2

Definition at line 254 of file reg.h.

#define LOAD_FW_READY

Value:

(IMEM_CODE_DONE | \
                        IMEM_CHK_RPT | \
                        EMEM_CODE_DONE | \
                        EMEM_CHK_RPT | \
                        DMEM_CODE_DONE | \
                        IMEM_RDY | \
                        BASECHG | \
                        FWRDY)

Definition at line 436 of file reg.h.

#define LPLDO_CTRL 0x0024

Definition at line 47 of file reg.h.

#define LPNAV_CTRL 0x0264

Definition at line 237 of file reg.h.

#define LX_EXCEPTION_ADDR 0x0330

Definition at line 273 of file reg.h.

#define MAC_PINMUX_CFG 0x02F1

Definition at line 253 of file reg.h.

#define MACIDR 0x0050

Definition at line 69 of file reg.h.

#define MACIDR0 0x0050

Definition at line 70 of file reg.h.

#define MACIDR4 0x0054

Definition at line 71 of file reg.h.

#define MACRXEN BIT(9)

Definition at line 385 of file reg.h.

#define MACTXEN BIT(8)

Definition at line 386 of file reg.h.

#define MAIR 0x0222

Definition at line 215 of file reg.h.

#define MAKS12BITS 0xfffff

Definition at line 1181 of file reg.h.

#define MAR 0x0060

Definition at line 74 of file reg.h.

#define MASK20BITS 0xfffff

Definition at line 1182 of file reg.h.

#define MASKBYTE0 0xff

Definition at line 1173 of file reg.h.

#define MASKBYTE1 0xff00

Definition at line 1174 of file reg.h.

#define MASKBYTE2 0xff0000

Definition at line 1175 of file reg.h.

#define MASKBYTE3 0xff000000

Definition at line 1176 of file reg.h.

#define MASKDWORD 0xffffffff

Definition at line 1179 of file reg.h.

#define MASKHWORD 0xffff0000

Definition at line 1177 of file reg.h.

#define MASKLWORD 0x0000ffff

Definition at line 1178 of file reg.h.

#define MAX_MSS_DENSITY_1T 0x0A

Definition at line 324 of file reg.h.

#define MAX_MSS_DENSITY_2T 0x13

Definition at line 323 of file reg.h.

#define MBIDCAMCFG 0x0070

Definition at line 76 of file reg.h.

#define MBIDCAMCONTENT 0x0068

Definition at line 75 of file reg.h.

#define MBIDCTRL 0x004F

Definition at line 66 of file reg.h.

#define MCS_TXAGC 0x01C0

Definition at line 186 of file reg.h.

#define MDIO_CTRL 0x0554

Definition at line 315 of file reg.h.

#define MDIO_DATA 0x0550

Definition at line 314 of file reg.h.

#define MGTQ_CTRL 0x0124

Definition at line 153 of file reg.h.

#define MIMOPS_WAIT_PERIOD 0x0263

Definition at line 236 of file reg.h.

#define MLT 0x009D

Definition at line 97 of file reg.h.

#define MQIR 0x0220

Definition at line 214 of file reg.h.

#define MSIR 0x0224

Definition at line 216 of file reg.h.

#define MSR 0x004C

Definition at line 63 of file reg.h.

#define MSR_ADHOC 0x01

Definition at line 492 of file reg.h.

#define MSR_AP 0x03

Definition at line 494 of file reg.h.

#define MSR_INFRA 0x02

Definition at line 493 of file reg.h.

#define MSR_LINK_ADHOC 1

Definition at line 489 of file reg.h.

#define MSR_LINK_MANAGED 2

Definition at line 486 of file reg.h.

#define MSR_LINK_MASK ((1 << 0) | (1 << 1))

Definition at line 485 of file reg.h.

#define MSR_LINK_MASTER 3

Definition at line 490 of file reg.h.

#define MSR_LINK_NONE 0

Definition at line 487 of file reg.h.

#define MSR_LINK_SHIFT 0

Definition at line 488 of file reg.h.

#define MSR_NOLINK 0x00

Definition at line 491 of file reg.h.

#define NAV_CTRL 0x0200

Definition at line 205 of file reg.h.

#define NAV_PROT_LEN 0x0234

Definition at line 220 of file reg.h.

#define NAV_RTSRST 0xFF

Definition at line 606 of file reg.h.

#define NAV_UPPER 0xFF00

Definition at line 605 of file reg.h.

#define NAV_UPPER_EN BIT(16)

Definition at line 604 of file reg.h.

#define NHM_PERIOD_REG 0x896

Definition at line 865 of file reg.h.

#define NHM_RESULT_REG 0x8D4

Definition at line 875 of file reg.h.

#define NHM_RPI_CNT 0x0228

Definition at line 218 of file reg.h.

#define NHM_RPI_COUNTER0 0x8D8

Definition at line 876 of file reg.h.

#define NHM_RPI_COUNTER1 0x8D9

Definition at line 877 of file reg.h.

#define NHM_RPI_COUNTER2 0x8DA

Definition at line 878 of file reg.h.

#define NHM_RPI_COUNTER3 0x8DB

Definition at line 879 of file reg.h.

#define NHM_RPI_COUNTER4 0x8DC

Definition at line 880 of file reg.h.

#define NHM_RPI_COUNTER5 0x8DD

Definition at line 881 of file reg.h.

#define NHM_RPI_COUNTER6 0x8DE

Definition at line 882 of file reg.h.

#define NHM_RPI_COUNTER7 0x8DF

Definition at line 883 of file reg.h.

#define NHM_THRESHOLD0 0x898

Definition at line 867 of file reg.h.

#define NHM_THRESHOLD1 0x899

Definition at line 868 of file reg.h.

#define NHM_THRESHOLD2 0x89A

Definition at line 869 of file reg.h.

#define NHM_THRESHOLD3 0x89B

Definition at line 870 of file reg.h.

#define NHM_THRESHOLD4 0x89C

Definition at line 871 of file reg.h.

#define NHM_THRESHOLD5 0x89D

Definition at line 872 of file reg.h.

#define NHM_THRESHOLD6 0x89E

Definition at line 873 of file reg.h.

#define PAD_HWPD_IDN BIT(22)

Definition at line 344 of file reg.h.

#define PBP 0x00B5

Definition at line 116 of file reg.h.

#define PCI_CPWM 0x0563

Definition at line 317 of file reg.h.

#define PCI_RPWM 0x0561

Definition at line 316 of file reg.h.

#define PCIF 0x0503

Definition at line 298 of file reg.h.

#define PHY_CCA 0x803

Definition at line 320 of file reg.h.

#define PHY_REG 0x02F3

Definition at line 255 of file reg.h.

#define PHY_REG_DATA 0x02F4

Definition at line 256 of file reg.h.

#define PIFS_TIME 0x0090

Definition at line 89 of file reg.h.

#define PM_CTRL 0x0502

Definition at line 297 of file reg.h.

#define PMC_FSM 0x0004

Definition at line 35 of file reg.h.

#define PSSTATUS 0x0261

Definition at line 234 of file reg.h.

#define PSSWITCH 0x0262

Definition at line 235 of file reg.h.

#define PSTIME 0x02E0

Definition at line 248 of file reg.h.

#define PWR_DATA 0x0038

Definition at line 52 of file reg.h.

#define RARFRC 0x01B8

Definition at line 185 of file reg.h.

#define RATE_ALL_CCK

Value:

(RATR_1M | RATR_2M | \

RATR_55M | RATR_11M)

Definition at line 573 of file reg.h.

#define RATE_ALL_OFDM_1SS

Value:

(RATR_MCS0 | RATR_MCS1 | \
                        RATR_MCS2 | RATR_MCS3 | \
                        RATR_MCS4 | RATR_MCS5 | \
                        RATR_MCS6 | RATR_MCS7)

Definition at line 579 of file reg.h.

#define RATE_ALL_OFDM_2SS

Value:

(RATR_MCS8 | RATR_MCS9 | \
                        RATR_MCS10 | RATR_MCS11 | \
                        RATR_MCS12 | RATR_MCS13 | \
                        RATR_MCS14 | RATR_MCS15)

Definition at line 583 of file reg.h.

#define RATE_ALL_OFDM_AG

Value:

(RATR_6M | RATR_9M | \
                        RATR_12M | RATR_18M | \
                        RATR_24M | RATR_36M | \
                        RATR_48M | RATR_54M)

Definition at line 575 of file reg.h.

#define RATR_11M 0x00000008

Definition at line 547 of file reg.h.

#define RATR_12M 0x00000040

Definition at line 550 of file reg.h.

#define RATR_18M 0x00000080

Definition at line 551 of file reg.h.

#define RATR_1M 0x00000001

Definition at line 544 of file reg.h.

#define RATR_24M 0x00000100

Definition at line 552 of file reg.h.

#define RATR_2M 0x00000002

Definition at line 545 of file reg.h.

#define RATR_36M 0x00000200

Definition at line 553 of file reg.h.

#define RATR_48M 0x00000400

Definition at line 554 of file reg.h.

#define RATR_54M 0x00000800

Definition at line 555 of file reg.h.

#define RATR_55M 0x00000004

Definition at line 546 of file reg.h.

#define RATR_6M 0x00000010

Definition at line 548 of file reg.h.

#define RATR_9M 0x00000020

Definition at line 549 of file reg.h.

#define RATR_MCS0 0x00001000

Definition at line 556 of file reg.h.

#define RATR_MCS1 0x00002000

Definition at line 557 of file reg.h.

#define RATR_MCS10 0x00400000

Definition at line 566 of file reg.h.

#define RATR_MCS11 0x00800000

Definition at line 567 of file reg.h.

#define RATR_MCS12 0x01000000

Definition at line 568 of file reg.h.

#define RATR_MCS13 0x02000000

Definition at line 569 of file reg.h.

#define RATR_MCS14 0x04000000

Definition at line 570 of file reg.h.

#define RATR_MCS15 0x08000000

Definition at line 571 of file reg.h.

#define RATR_MCS2 0x00004000

Definition at line 558 of file reg.h.

#define RATR_MCS3 0x00008000

Definition at line 559 of file reg.h.

#define RATR_MCS4 0x00010000

Definition at line 560 of file reg.h.

#define RATR_MCS5 0x00020000

Definition at line 561 of file reg.h.

#define RATR_MCS6 0x00040000

Definition at line 562 of file reg.h.

#define RATR_MCS7 0x00080000

Definition at line 563 of file reg.h.

#define RATR_MCS8 0x00100000

Definition at line 564 of file reg.h.

#define RATR_MCS9 0x00200000

Definition at line 565 of file reg.h.

#define RCCK0_AFESETTING 0xa04

Definition at line 982 of file reg.h.

#define RCCK0_CCA 0xa08

Definition at line 983 of file reg.h.

#define RCCK0_DEBUGPORT 0xa28

Definition at line 995 of file reg.h.

#define RCCK0_DSPPARAMETER1 0xa18

Definition at line 990 of file reg.h.

#define RCCK0_DSPPARAMETER2 0xa1c

Definition at line 991 of file reg.h.

#define RCCK0_FACOUNTERLOWER 0xa5c

Definition at line 999 of file reg.h.

#define RCCK0_FACOUNTERUPPER 0xa58

Definition at line 1000 of file reg.h.

#define RCCK0_FALSEALARMREPORT 0xa2c

Definition at line 996 of file reg.h.

#define RCCK0_RXAGC1 0xa0c

Definition at line 985 of file reg.h.

#define RCCK0_RXAGC2 0xa10

Definition at line 986 of file reg.h.

#define RCCK0_RXHP 0xa14

Definition at line 988 of file reg.h.

#define RCCK0_RXREPORT 0xa54

Definition at line 998 of file reg.h.

#define RCCK0_SYSTEM 0xa00

Definition at line 980 of file reg.h.

#define RCCK0_TRSSIREPORT 0xa50

Definition at line 997 of file reg.h.

#define RCCK0_TXFILTER1 0xa20

Definition at line 993 of file reg.h.

#define RCCK0_TXFILTER2 0xa24

Definition at line 994 of file reg.h.

#define RCDA 0x0538

Definition at line 309 of file reg.h.

#define RCLK_MON 0x003E

Definition at line 55 of file reg.h.

#define RCR 0x0048

Definition at line 62 of file reg.h.

#define RCR_9356SEL BIT(6)

Definition at line 850 of file reg.h.

#define RCR_AAP BIT(0)

Definition at line 480 of file reg.h.

#define RCR_AB BIT(3)

Definition at line 477 of file reg.h.

#define RCR_ACF BIT(19)

Definition at line 467 of file reg.h.

#define RCR_ACRC32 BIT(5)

Definition at line 475 of file reg.h.

#define RCR_ADD3 BIT(21)

Definition at line 465 of file reg.h.

#define RCR_ADF BIT(18)

Definition at line 468 of file reg.h.

#define RCR_AICV BIT(12)

Definition at line 472 of file reg.h.

#define RCR_AM BIT(2)

Definition at line 478 of file reg.h.

#define RCR_AMF BIT(20)

Definition at line 466 of file reg.h.

#define RCR_APM BIT(1)

Definition at line 479 of file reg.h.

#define RCR_APP_BA_SSN BIT(6)

Definition at line 474 of file reg.h.

#define RCR_APP_ICV BIT(16)

Definition at line 470 of file reg.h.

#define RCR_APP_MIC BIT(17)

Definition at line 469 of file reg.h.

#define RCR_APP_PHYST_RXFF BIT(25)

Definition at line 461 of file reg.h.

#define RCR_APP_PHYST_STAFF BIT(24)

Definition at line 462 of file reg.h.

#define RCR_APPFCS BIT(31)

Definition at line 455 of file reg.h.

#define RCR_APWRMGT BIT(22)

Definition at line 464 of file reg.h.

#define RCR_CBSSID BIT(23)

Definition at line 463 of file reg.h.

#define RCR_DIS_AES_2BYTE BIT(29)

Definition at line 457 of file reg.h.

#define RCR_DIS_ENC_2BYTE BIT(30)

Definition at line 456 of file reg.h.

#define RCR_ENMBID BIT(27)

Definition at line 459 of file reg.h.

#define RCR_FIFO_OFFSET 13

Definition at line 856 of file reg.h.

#define RCR_FIFO_OFFSET 13

Definition at line 856 of file reg.h.

#define RCR_HTC_LOC_CTRL BIT(28)

Definition at line 458 of file reg.h.

#define RCR_MXDMA_OFFSET 8

Definition at line 855 of file reg.h.

#define RCR_MXDMA_OFFSET 8

Definition at line 855 of file reg.h.

#define RCR_OnlyErlPkt BIT(31)

Definition at line 857 of file reg.h.

#define RCR_RX_TCPOFDL_EN BIT(26)

Definition at line 460 of file reg.h.

#define RCR_RXDESC_LK_EN BIT(11)

Definition at line 473 of file reg.h.

#define RCR_RXFTH BIT(13)

Definition at line 471 of file reg.h.

#define RCR_RXSHFT_EN BIT(4)

Definition at line 476 of file reg.h.

#define RDQDA 0x053C

Definition at line 310 of file reg.h.

#define REG_CAMDBG 0x024C

Definition at line 229 of file reg.h.

#define REG_EFUSE_CLK 0x02F8

Definition at line 257 of file reg.h.

#define REG_EFUSE_CTRL 0x0030

Definition at line 50 of file reg.h.

#define REG_EFUSE_TEST 0x0034

Definition at line 51 of file reg.h.

#define REG_RCAMO 0x0248

Definition at line 228 of file reg.h.

#define REG_RWCAM 0x0240

Definition at line 226 of file reg.h.

#define REG_SECR 0x0250

Definition at line 230 of file reg.h.

#define REG_SYS_FUNC_EN 0x0002

Definition at line 34 of file reg.h.

#define REG_SYS_ISO_CTRL 0x0000

Definition at line 33 of file reg.h.

#define REG_WCAMI 0x0244

Definition at line 227 of file reg.h.

#define RETRY_LIMIT 0x01F4

Definition at line 201 of file reg.h.

#define RETRY_LIMIT_LONG_SHIFT 0

Definition at line 602 of file reg.h.

#define RETRY_LIMIT_SHORT_SHIFT 8

Definition at line 601 of file reg.h.

#define RETRYCTR 0xDE

Definition at line 859 of file reg.h.

#define RF_AC 0x00

Definition at line 1104 of file reg.h.

#define RF_BB_CMD_ADDR 0x02c0

Definition at line 917 of file reg.h.

#define RF_BB_CMD_DATA 0x02c4

Definition at line 918 of file reg.h.

#define RF_BIAS 0x14

Definition at line 1117 of file reg.h.

#define RF_BS_IQGEN 0x0F

Definition at line 1111 of file reg.h.

#define RF_CHANNEL 0x18

Definition at line 1121 of file reg.h.

#define RF_CHNLBW 0x18

Definition at line 1122 of file reg.h.

#define RF_CTRL 0x001F

Definition at line 42 of file reg.h.

#define RF_EN BIT(0)

Definition at line 363 of file reg.h.

#define RF_GAIN_RX 0x06

Definition at line 1108 of file reg.h.

#define RF_GAIN_TX 0x07

Definition at line 1109 of file reg.h.

#define RF_IPA 0x15

Definition at line 1118 of file reg.h.

#define RF_IQADJ_G1 0x01

Definition at line 1105 of file reg.h.

#define RF_IQADJ_G2 0x02

Definition at line 1106 of file reg.h.

#define RF_MODE1 0x10

Definition at line 1113 of file reg.h.

#define RF_MODE2 0x11

Definition at line 1114 of file reg.h.

#define RF_MODE_AG 0x18

Definition at line 1120 of file reg.h.

#define RF_POW_ABILITY 0x17

Definition at line 1119 of file reg.h.

#define RF_POW_TRSW 0x05

Definition at line 1107 of file reg.h.

#define RF_RCK1 0x1E

Definition at line 1128 of file reg.h.

#define RF_RCK2 0x1F

Definition at line 1129 of file reg.h.

#define RF_RCK_OS 0x30

Definition at line 1145 of file reg.h.

#define RF_RSTB BIT(1)

Definition at line 364 of file reg.h.

#define RF_RX_AGC_HP 0x12

Definition at line 1115 of file reg.h.

#define RF_RX_BB1 0x1D

Definition at line 1127 of file reg.h.

#define RF_RX_BB2 0x1C

Definition at line 1126 of file reg.h.

#define RF_RX_G1 0x1A

Definition at line 1124 of file reg.h.

#define RF_RX_G2 0x1B

Definition at line 1125 of file reg.h.

#define RF_SDMRSTB BIT(2)

Definition at line 365 of file reg.h.

#define RF_SYN_G1 0x25

Definition at line 1136 of file reg.h.

#define RF_SYN_G2 0x26

Definition at line 1137 of file reg.h.

#define RF_SYN_G3 0x27

Definition at line 1138 of file reg.h.

#define RF_SYN_G4 0x28

Definition at line 1139 of file reg.h.

#define RF_SYN_G5 0x29

Definition at line 1140 of file reg.h.

#define RF_SYN_G6 0x2A

Definition at line 1141 of file reg.h.

#define RF_SYN_G7 0x2B

Definition at line 1142 of file reg.h.

#define RF_SYN_G8 0x2C

Definition at line 1143 of file reg.h.

#define RF_T_METER 0x24

Definition at line 1135 of file reg.h.

#define RF_TOP 0x19

Definition at line 1123 of file reg.h.

#define RF_TX_AGC 0x13

Definition at line 1116 of file reg.h.

#define RF_TX_BB1 0x23

Definition at line 1134 of file reg.h.

#define RF_TX_G1 0x20

Definition at line 1131 of file reg.h.

#define RF_TX_G2 0x21

Definition at line 1132 of file reg.h.

#define RF_TX_G3 0x22

Definition at line 1133 of file reg.h.

#define RF_TXM_IDAC 0x08

Definition at line 1110 of file reg.h.

#define RF_TXPA_G1 0x31

Definition at line 1146 of file reg.h.

#define RF_TXPA_G2 0x32

Definition at line 1147 of file reg.h.

#define RF_TXPA_G3 0x33

Definition at line 1148 of file reg.h.

#define RFPC 0x5F

Definition at line 849 of file reg.h.

#define RFPGA0_ANALOGPARAMETER1 0x880

Definition at line 959 of file reg.h.

#define RFPGA0_ANALOGPARAMETER2 0x884

Definition at line 960 of file reg.h.

#define RFPGA0_ANALOGPARAMETER3 0x888

Definition at line 961 of file reg.h.

#define RFPGA0_ANALOGPARAMETER4 0x88c

Definition at line 962 of file reg.h.

#define RFPGA0_PSDFUNCTION 0x808

Definition at line 923 of file reg.h.

#define RFPGA0_PSDREPORT 0x8b4

Definition at line 969 of file reg.h.

#define RFPGA0_RFMOD 0x800

Definition at line 920 of file reg.h.

#define RFPGA0_RFSLEEPUP_PARAMETER 0x854

Definition at line 943 of file reg.h.

#define RFPGA0_RFTIMING1 0x810

Definition at line 927 of file reg.h.

#define RFPGA0_RFTIMING2 0x814

Definition at line 928 of file reg.h.

#define RFPGA0_RFWAKEUP_PARAMETER 0x850

Definition at line 942 of file reg.h.

#define RFPGA0_TXGAINSTAGE 0x80c

Definition at line 925 of file reg.h.

#define RFPGA0_TXINFO 0x804

Definition at line 922 of file reg.h.

#define RFPGA0_XA_HSSIPARAMETER1 0x820

Definition at line 929 of file reg.h.

#define RFPGA0_XA_HSSIPARAMETER2 0x824

Definition at line 930 of file reg.h.

#define RFPGA0_XA_LSSIPARAMETER 0x840

Definition at line 937 of file reg.h.

#define RFPGA0_XA_LSSIREADBACK 0x8a0

Definition at line 964 of file reg.h.

#define RFPGA0_XA_RFINTERFACEOE 0x860

Definition at line 948 of file reg.h.

#define RFPGA0_XAB_RFINTERFACERB 0x8e0

Definition at line 972 of file reg.h.

#define RFPGA0_XAB_RFINTERFACESW 0x870

Definition at line 953 of file reg.h.

#define RFPGA0_XAB_RFPARAMETER 0x878

Definition at line 956 of file reg.h.

#define RFPGA0_XAB_SWITCHCONTROL 0x858

Definition at line 945 of file reg.h.

#define RFPGA0_XB_HSSIPARAMETER1 0x828

Definition at line 931 of file reg.h.

#define RFPGA0_XB_HSSIPARAMETER2 0x82c

Definition at line 932 of file reg.h.

#define RFPGA0_XB_LSSIPARAMETER 0x844

Definition at line 938 of file reg.h.

#define RFPGA0_XB_LSSIREADBACK 0x8a4

Definition at line 965 of file reg.h.

#define RFPGA0_XB_RFINTERFACEOE 0x864

Definition at line 949 of file reg.h.

#define RFPGA0_XC_HSSIPARAMETER1 0x830

Definition at line 933 of file reg.h.

#define RFPGA0_XC_HSSIPARAMETER2 0x834

Definition at line 934 of file reg.h.

#define RFPGA0_XC_LSSIPARAMETER 0x848

Definition at line 939 of file reg.h.

#define RFPGA0_XC_LSSIREADBACK 0x8a8

Definition at line 966 of file reg.h.

#define RFPGA0_XC_RFINTERFACEOE 0x868

Definition at line 950 of file reg.h.

#define RFPGA0_XCD_RFINTERFACERB 0x8e4

Definition at line 973 of file reg.h.

#define RFPGA0_XCD_RFINTERFACESW 0x874

Definition at line 954 of file reg.h.

#define RFPGA0_XCD_RFPARAMETER 0x87c

Definition at line 957 of file reg.h.

#define RFPGA0_XCD_SWITCHCONTROL 0x85c

Definition at line 946 of file reg.h.

#define RFPGA0_XD_HSSIPARAMETER1 0x838

Definition at line 935 of file reg.h.

#define RFPGA0_XD_HSSIPARAMETER2 0x83c

Definition at line 936 of file reg.h.

#define RFPGA0_XD_LSSIPARAMETER 0x84c

Definition at line 940 of file reg.h.

#define RFPGA0_XD_LSSIREADBACK 0x8ac

Definition at line 967 of file reg.h.

#define RFPGA0_XD_RFINTERFACEOE 0x86c

Definition at line 951 of file reg.h.

#define RFPGA1_DEBUGSELECT 0x908

Definition at line 977 of file reg.h.

#define RFPGA1_RFMOD 0x900

Definition at line 974 of file reg.h.

#define RFPGA1_TXBLOCK 0x904

Definition at line 976 of file reg.h.

#define RFPGA1_TXINFO 0x90c

Definition at line 978 of file reg.h.

#define RFREG_OFFSET_MASK 0xfffff

Definition at line 1183 of file reg.h.

#define ROFDM0_AGCPARAMETER1 0xc70

Definition at line 1036 of file reg.h.

#define ROFDM0_AGCPARAMETER2 0xc74

Definition at line 1037 of file reg.h.

#define ROFDM0_AGCRSSITABLE 0xc78

Definition at line 1038 of file reg.h.

#define ROFDM0_CCADROP_THRESHOLD 0xc48

Definition at line 1024 of file reg.h.

#define ROFDM0_CFO_AND_DAGC 0xc44

Definition at line 1023 of file reg.h.

#define ROFDM0_DFSREPORT 0xcf4

Definition at line 1053 of file reg.h.

#define ROFDM0_ECCA_THRESHOLD 0xc4c

Definition at line 1025 of file reg.h.

#define ROFDM0_FRAME_SYNC 0xcf0

Definition at line 1052 of file reg.h.

#define ROFDM0_HTSTFAGC 0xc7c

Definition at line 1039 of file reg.h.

#define ROFDM0_LSTF 0xc00

Definition at line 1002 of file reg.h.

#define ROFDM0_RXDETECTOR1 0xc30

Definition at line 1017 of file reg.h.

#define ROFDM0_RXDETECTOR2 0xc34

Definition at line 1018 of file reg.h.

#define ROFDM0_RXDETECTOR3 0xc38

Definition at line 1019 of file reg.h.

#define ROFDM0_RXDETECTOR4 0xc3c

Definition at line 1020 of file reg.h.

#define ROFDM0_RXDSP 0xc40

Definition at line 1022 of file reg.h.

#define ROFDM0_RXHP_PARAMETER 0xce0

Definition at line 1050 of file reg.h.

#define ROFDM0_TRMUXPAR 0xc08

Definition at line 1005 of file reg.h.

#define ROFDM0_TRSWISOLATION 0xc0c

Definition at line 1006 of file reg.h.

#define ROFDM0_TRXPATHENABLE 0xc04

Definition at line 1004 of file reg.h.

#define ROFDM0_TXCOEFF1 0xca4

Definition at line 1054 of file reg.h.

#define ROFDM0_TXCOEFF2 0xca8

Definition at line 1055 of file reg.h.

#define ROFDM0_TXCOEFF3 0xcac

Definition at line 1056 of file reg.h.

#define ROFDM0_TXCOEFF4 0xcb0

Definition at line 1057 of file reg.h.

#define ROFDM0_TXCOEFF5 0xcb4

Definition at line 1058 of file reg.h.

#define ROFDM0_TXCOEFF6 0xcb8

Definition at line 1059 of file reg.h.

#define ROFDM0_TXPSEUDO_NOISE_WGT 0xce4

Definition at line 1051 of file reg.h.

#define ROFDM0_XAAGCCORE1 0xc50

Definition at line 1027 of file reg.h.

#define ROFDM0_XAAGCCORE2 0xc54

Definition at line 1028 of file reg.h.

#define ROFDM0_XARXAFE 0xc10

Definition at line 1008 of file reg.h.

#define ROFDM0_XARXIQIMBALANCE 0xc14

Definition at line 1009 of file reg.h.

#define ROFDM0_XATXAFE 0xc84

Definition at line 1042 of file reg.h.

#define ROFDM0_XATXIQIMBALANCE 0xc80

Definition at line 1041 of file reg.h.

#define ROFDM0_XBAGCCORE1 0xc58

Definition at line 1029 of file reg.h.

#define ROFDM0_XBAGCCORE2 0xc5c

Definition at line 1030 of file reg.h.

#define ROFDM0_XBRXAFE 0xc18

Definition at line 1010 of file reg.h.

#define ROFDM0_XBRXIQIMBALANCE 0xc1c

Definition at line 1011 of file reg.h.

#define ROFDM0_XBTXAFE 0xc8c

Definition at line 1044 of file reg.h.

#define ROFDM0_XBTXIQIMBALANCE 0xc88

Definition at line 1043 of file reg.h.

#define ROFDM0_XCAGCCORE1 0xc60

Definition at line 1031 of file reg.h.

#define ROFDM0_XCAGCCORE2 0xc64

Definition at line 1032 of file reg.h.

#define ROFDM0_XCRXAFE 0xc20

Definition at line 1012 of file reg.h.

#define ROFDM0_XCRXIQIMBALANCE 0xc24

Definition at line 1013 of file reg.h.

#define ROFDM0_XCTXAFE 0xc94

Definition at line 1046 of file reg.h.

#define ROFDM0_XCTXIQIMBALANCE 0xc90

Definition at line 1045 of file reg.h.

#define ROFDM0_XDAGCCORE1 0xc68

Definition at line 1033 of file reg.h.

#define ROFDM0_XDAGCCORE2 0xc6c

Definition at line 1034 of file reg.h.

#define ROFDM0_XDRXAFE 0xc28

Definition at line 1014 of file reg.h.

#define ROFDM0_XDRXIQIMBALANCE 0xc2c

Definition at line 1015 of file reg.h.

#define ROFDM0_XDTXAFE 0xc9c

Definition at line 1048 of file reg.h.

#define ROFDM0_XDTXIQIMBALANCE 0xc98

Definition at line 1047 of file reg.h.

#define ROFDM1_CFO 0xd08

Definition at line 1065 of file reg.h.

#define ROFDM1_CFOTRACKING 0xd2c

Definition at line 1069 of file reg.h.

#define ROFDM1_CSI1 0xd10

Definition at line 1066 of file reg.h.

#define ROFDM1_CSI2 0xd18

Definition at line 1068 of file reg.h.

#define ROFDM1_INTF_DET 0xd3c

Definition at line 1071 of file reg.h.

#define ROFDM1_LSTF 0xd00

Definition at line 1062 of file reg.h.

#define ROFDM1_PSEUDO_NOISESTATEAB 0xd50

Definition at line 1072 of file reg.h.

#define ROFDM1_PSEUDO_NOISESTATECD 0xd54

Definition at line 1073 of file reg.h.

#define ROFDM1_RX_PSEUDO_NOISE_WGT 0xd58

Definition at line 1074 of file reg.h.

#define ROFDM1_SBD 0xd14

Definition at line 1067 of file reg.h.

#define ROFDM1_TRXMESAURE1 0xd34

Definition at line 1070 of file reg.h.

#define ROFDM1_TRXPATHENABLE 0xd04

Definition at line 1063 of file reg.h.

#define ROFDM_AGC_REPORT 0xdd0

Definition at line 1089 of file reg.h.

#define ROFDM_BW_REPORT 0xdcc

Definition at line 1088 of file reg.h.

#define ROFDM_LONG_CFOAB 0xdb4

Definition at line 1082 of file reg.h.

#define ROFDM_LONG_CFOCD 0xdb8

Definition at line 1083 of file reg.h.

#define ROFDM_PHYCOUNTER1 0xda0

Definition at line 1076 of file reg.h.

#define ROFDM_PHYCOUNTER2 0xda4

Definition at line 1077 of file reg.h.

#define ROFDM_PHYCOUNTER3 0xda8

Definition at line 1078 of file reg.h.

#define ROFDM_PW_MEASURE1 0xdc4

Definition at line 1086 of file reg.h.

#define ROFDM_PW_MEASURE2 0xdc8

Definition at line 1087 of file reg.h.

#define ROFDM_RXEVMCSI 0xdd8

Definition at line 1091 of file reg.h.

#define ROFDM_RXSNR 0xdd4

Definition at line 1090 of file reg.h.

#define ROFDM_SHORT_CFOAB 0xdac

Definition at line 1080 of file reg.h.

#define ROFDM_SHORT_CFOCD 0xdb0

Definition at line 1081 of file reg.h.

#define ROFDM_SIG_REPORT 0xddc

Definition at line 1092 of file reg.h.

#define ROFDM_TAIL_CFOAB 0xdbc

Definition at line 1084 of file reg.h.

#define ROFDM_TAIL_CFOCD 0xdc0

Definition at line 1085 of file reg.h.

#define RPMAC_CCKCRC16 0x148

Definition at line 907 of file reg.h.

#define RPMAC_CCKCRXRC16ER 0x180

Definition at line 912 of file reg.h.

#define RPMAC_CCKCRXRC32ER 0x184

Definition at line 913 of file reg.h.

#define RPMAC_CCKCRXRC32OK 0x188

Definition at line 914 of file reg.h.

#define RPMAC_CCKPLCPHEADER 0x144

Definition at line 906 of file reg.h.

#define RPMAC_CCKPLCPPREAMBLE 0x140

Definition at line 905 of file reg.h.

#define RPMAC_OFDMRXCRC32ER 0x174

Definition at line 909 of file reg.h.

#define RPMAC_OFDMRXCRC32OK 0x170

Definition at line 908 of file reg.h.

#define RPMAC_OFDMRXCRC8ER 0x17c

Definition at line 911 of file reg.h.

#define RPMAC_OFDMRXPARITYER 0x178

Definition at line 910 of file reg.h.

#define RPMAC_PHYDEBUG 0x114

Definition at line 894 of file reg.h.

#define RPMAC_RESET 0x100

Definition at line 889 of file reg.h.

#define RPMAC_TXDATATYPE 0x138

Definition at line 903 of file reg.h.

#define RPMAC_TXHTSIG1 0x10c

Definition at line 892 of file reg.h.

#define RPMAC_TXHTSIG2 0x110

Definition at line 893 of file reg.h.

#define RPMAC_TXIDLE 0x11c

Definition at line 896 of file reg.h.

#define RPMAC_TXLEGACYSIG 0x108

Definition at line 891 of file reg.h.

#define RPMAC_TXMACHEADER0 0x120

Definition at line 897 of file reg.h.

#define RPMAC_TXMACHEADER1 0x124

Definition at line 898 of file reg.h.

#define RPMAC_TXMACHEADER2 0x128

Definition at line 899 of file reg.h.

#define RPMAC_TXMACHEADER3 0x12c

Definition at line 900 of file reg.h.

#define RPMAC_TXMACHEADER4 0x130

Definition at line 901 of file reg.h.

#define RPMAC_TXMACHEADER5 0x134

Definition at line 902 of file reg.h.

#define RPMAC_TXPACKETNNM 0x118

Definition at line 895 of file reg.h.

#define RPMAC_TXRANDOMSEED 0x13c

Definition at line 904 of file reg.h.

#define RPMAC_TXSTART 0x104

Definition at line 890 of file reg.h.

#define RPMAC_TXSTATUS 0x18c

Definition at line 915 of file reg.h.

#define RPWM PCI_RPWM

Definition at line 329 of file reg.h.

#define RQPN 0x00A0

Definition at line 101 of file reg.h.

#define RQPN1 0x00A0

Definition at line 102 of file reg.h.

#define RQPN10 0x00A9

Definition at line 111 of file reg.h.

#define RQPN2 0x00A1

Definition at line 103 of file reg.h.

#define RQPN3 0x00A2

Definition at line 104 of file reg.h.

#define RQPN4 0x00A3

Definition at line 105 of file reg.h.

#define RQPN5 0x00A4

Definition at line 106 of file reg.h.

#define RQPN6 0x00A5

Definition at line 107 of file reg.h.

#define RQPN7 0x00A6

Definition at line 108 of file reg.h.

#define RQPN8 0x00A7

Definition at line 109 of file reg.h.

#define RQPN9 0x00A8

Definition at line 110 of file reg.h.

#define RRSR 0x0181

Definition at line 173 of file reg.h.

#define RRSR_11M BIT(3)

Definition at line 525 of file reg.h.

#define RRSR_12M BIT(6)

Definition at line 528 of file reg.h.

#define RRSR_18M BIT(7)

Definition at line 529 of file reg.h.

#define RRSR_1M BIT(0)

Definition at line 522 of file reg.h.

#define RRSR_24M BIT(8)

Definition at line 530 of file reg.h.

#define RRSR_2M BIT(1)

Definition at line 523 of file reg.h.

#define RRSR_36M BIT(9)

Definition at line 531 of file reg.h.

#define RRSR_48M BIT(10)

Definition at line 532 of file reg.h.

#define RRSR_54M BIT(11)

Definition at line 533 of file reg.h.

#define RRSR_5_5M BIT(2)

Definition at line 524 of file reg.h.

#define RRSR_6M BIT(4)

Definition at line 526 of file reg.h.

#define RRSR_9M BIT(5)

Definition at line 527 of file reg.h.

#define RRSR_MCS0 BIT(12)

Definition at line 534 of file reg.h.

#define RRSR_MCS1 BIT(13)

Definition at line 535 of file reg.h.

#define RRSR_MCS2 BIT(14)

Definition at line 536 of file reg.h.

#define RRSR_MCS3 BIT(15)

Definition at line 537 of file reg.h.

#define RRSR_MCS4 BIT(16)

Definition at line 538 of file reg.h.

#define RRSR_MCS5 BIT(17)

Definition at line 539 of file reg.h.

#define RRSR_MCS6 BIT(18)

Definition at line 540 of file reg.h.

#define RRSR_MCS7 BIT(19)

Definition at line 541 of file reg.h.

#define RRSR_RSC_BW_40M 0x600000

Definition at line 518 of file reg.h.

#define RRSR_RSC_LOWSUBCHNL 0x200000

Definition at line 520 of file reg.h.

#define RRSR_RSC_OFFSET 21

Definition at line 516 of file reg.h.

#define RRSR_RSC_UPSUBCHNL 0x400000

Definition at line 519 of file reg.h.

#define RRSR_SHORT 0x800000

Definition at line 521 of file reg.h.

#define RRSR_SHORT_OFFSET 23

Definition at line 517 of file reg.h.

#define RSVD_MAC_TUNE_US 0x009E

Definition at line 98 of file reg.h.

#define RTL8190_EEPROM_ID 0x8129

Definition at line 740 of file reg.h.

#define RTXAGC_CCK_MCS32 0xe08

Definition at line 1097 of file reg.h.

#define RTXAGC_MCS03_MCS00 0xe10

Definition at line 1098 of file reg.h.

#define RTXAGC_MCS07_MCS04 0xe14

Definition at line 1099 of file reg.h.

#define RTXAGC_MCS11_MCS08 0xe18

Definition at line 1100 of file reg.h.

#define RTXAGC_MCS15_MCS12 0xe1c

Definition at line 1101 of file reg.h.

#define RTXAGC_RATE18_06 0xe00

Definition at line 1095 of file reg.h.

#define RTXAGC_RATE54_24 0xe04

Definition at line 1096 of file reg.h.

#define RX0_UDT_SIZE 0x0110

Definition at line 146 of file reg.h.

#define RX1PKTNUM 0x0114

Definition at line 147 of file reg.h.

#define RX_PKY_LIMIT 0x004E

Definition at line 65 of file reg.h.

#define RXDMA 0x00BD

Definition at line 122 of file reg.h.

#define RXDMA_AGG_EN BIT(7)

Definition at line 327 of file reg.h.

#define RXDMA_AGG_PG_TH 0x00D9

Definition at line 132 of file reg.h.

#define RXDMA_EN BIT(5)

Definition at line 389 of file reg.h.

#define RXDRVINFO_SZ 0x00B6

Definition at line 117 of file reg.h.

#define RXERR_CCK_FALSE_ALARM 5

Definition at line 618 of file reg.h.

#define RXERR_CCK_MPDU_FAIL 7

Definition at line 620 of file reg.h.

#define RXERR_CCK_MPDU_OK 6

Definition at line 619 of file reg.h.

#define RXERR_CCK_PPDU 4

Definition at line 617 of file reg.h.

#define RXERR_HT_FALSE_ALARM 9

Definition at line 622 of file reg.h.

#define RXERR_HT_MPDU_FAIL 12

Definition at line 625 of file reg.h.

#define RXERR_HT_MPDU_OK 11

Definition at line 624 of file reg.h.

#define RXERR_HT_MPDU_TOTAL 10

Definition at line 623 of file reg.h.

#define RXERR_HT_PPDU 8

Definition at line 621 of file reg.h.

#define RXERR_OFDM_FALSE_ALARM 1

Definition at line 614 of file reg.h.

#define RXERR_OFDM_MPDU_FAIL 3

Definition at line 616 of file reg.h.

#define RXERR_OFDM_MPDU_OK 2

Definition at line 615 of file reg.h.

#define RXERR_OFDM_PPDU 0

Definition at line 613 of file reg.h.

#define RXERR_RPT 0x0230

Definition at line 219 of file reg.h.

#define RXERR_RPT_RST BIT(27)

Definition at line 612 of file reg.h.

#define RXERR_RX_FULL_DROP 15

Definition at line 626 of file reg.h.

#define RXFF0_RDPTR 0x00F0

Definition at line 138 of file reg.h.

#define RXFF0_WTPTR 0x00F4

Definition at line 139 of file reg.h.

#define RXFF1_RDPTR 0x00F8

Definition at line 140 of file reg.h.

#define RXFF1_WTPTR 0x00FC

Definition at line 141 of file reg.h.

#define RXFF_BNDY 0x00AC

Definition at line 113 of file reg.h.

#define RXFF_STATUS 0x00B8

Definition at line 119 of file reg.h.

#define RXFILTERMAP 0x0116

Definition at line 148 of file reg.h.

#define RXFILTERMAP_GP1 0x0118

Definition at line 149 of file reg.h.

#define RXFILTERMAP_GP2 0x011A

Definition at line 150 of file reg.h.

#define RXFILTERMAP_GP3 0x011C

Definition at line 151 of file reg.h.

#define RXPKT_NUM 0x00BE

Definition at line 123 of file reg.h.

#define RXRPT0_RDPTR 0x0100

Definition at line 142 of file reg.h.

#define RXRPT0_WTPTR 0x0104

Definition at line 143 of file reg.h.

#define RXRPT1_RDPTR 0x0108

Definition at line 144 of file reg.h.

#define RXRPT1_WTPTR 0x010C

Definition at line 145 of file reg.h.

#define RXRPT_BNDY 0x00B0

Definition at line 114 of file reg.h.

#define SCHEDULE_EN BIT(10)

Definition at line 384 of file reg.h.

#define SCR_NOSKMC BIT(5)

Definition at line 633 of file reg.h.

#define SCR_RXENCENABLE BIT(3)

Definition at line 631 of file reg.h.

#define SCR_RXUSEDK BIT(1)

Definition at line 629 of file reg.h.

#define SCR_SKBYA2 BIT(4)

Definition at line 632 of file reg.h.

#define SCR_TXENCENABLE BIT(2)

Definition at line 630 of file reg.h.

#define SCR_TXUSEDK BIT(0)

Definition at line 628 of file reg.h.

#define SDIO_RX_BLKSZ 0x00BC

Definition at line 121 of file reg.h.

#define SG_RATE 0x01F6

Definition at line 202 of file reg.h.

#define SIFS_CCK 0x008C

Definition at line 87 of file reg.h.

#define SIFS_CTX 0x00FF

Definition at line 508 of file reg.h.

#define SIFS_OFDM 0x008E

Definition at line 88 of file reg.h.

#define SIFS_TRX 0xFF00

Definition at line 507 of file reg.h.

#define SLOT_TIME 0x0089

Definition at line 85 of file reg.h.

#define SPS0_CTRL 0x0011

Definition at line 40 of file reg.h.

#define SPS1_CTRL 0x0018

Definition at line 41 of file reg.h.

#define SPS1_LDEN BIT(0)

Definition at line 361 of file reg.h.

#define SPS1_SWEN BIT(1)

Definition at line 360 of file reg.h.

#define StopBE BIT(1)

Definition at line 399 of file reg.h.

#define StopBK BIT(0)

Definition at line 400 of file reg.h.

#define StopHCCA BIT(6)

Definition at line 394 of file reg.h.

#define StopHigh BIT(5)

Definition at line 395 of file reg.h.

#define StopMgt BIT(4)

Definition at line 396 of file reg.h.

#define StopVI BIT(2)

Definition at line 398 of file reg.h.

#define StopVO BIT(3)

Definition at line 397 of file reg.h.

#define SYS_CLKR 0x0008

Definition at line 36 of file reg.h.

#define SYS_CLKSEL_80M BIT(0)

Definition at line 346 of file reg.h.

#define SYS_CPU_CLKSEL BIT(2)

Definition at line 348 of file reg.h.

#define SYS_FWHW_SEL BIT(15)

Definition at line 351 of file reg.h.

#define SYS_MAC_CLK_EN BIT(11)

Definition at line 349 of file reg.h.

#define SYS_PS_CLKSEL BIT(1)

Definition at line 347 of file reg.h.

#define SYS_SWHW_SEL BIT(14)

Definition at line 350 of file reg.h.

#define SYSF_CFG 0x004D

Definition at line 64 of file reg.h.

#define TBDA 0x0534

Definition at line 308 of file reg.h.

#define TBEDA 0x052C

Definition at line 306 of file reg.h.

#define TBKDA 0x0530

Definition at line 307 of file reg.h.

#define TCDA 0x051C

Definition at line 302 of file reg.h.

#define TCP_OFDL_EN BIT(25)

Definition at line 407 of file reg.h.

#define TCR 0x0044

Definition at line 61 of file reg.h.

#define TCR_CRC BIT(16)

Definition at line 447 of file reg.h.

#define TCR_DISCW BIT(20)

Definition at line 449 of file reg.h.

#define TCR_FAKE_IMEM_EN BIT(15)

Definition at line 446 of file reg.h.

#define TCR_HWPC_TX_EN BIT(24)

Definition at line 450 of file reg.h.

#define TCR_ICV BIT(19)

Definition at line 448 of file reg.h.

#define TCR_LRL_OFFSET 0

Definition at line 851 of file reg.h.

#define TCR_MXDMA_OFFSET 21

Definition at line 853 of file reg.h.

#define TCR_SAT BIT(24)

Definition at line 854 of file reg.h.

#define TCR_SRL_OFFSET 8

Definition at line 852 of file reg.h.

#define TCR_TCP_OFDL_EN BIT(25)

Definition at line 451 of file reg.h.

#define TCR_TSFEN BIT(8)

Definition at line 444 of file reg.h.

#define TCR_TSFRST BIT(9)

Definition at line 445 of file reg.h.

#define TCRCRC BIT(16)

Definition at line 413 of file reg.h.

#define TCRICV BIT(19)

Definition at line 411 of file reg.h.

#define THPDA 0x0514

Definition at line 300 of file reg.h.

#define TIMER0 0x02E4

Definition at line 249 of file reg.h.

#define TIMER1 0x02E8

Definition at line 250 of file reg.h.

#define TMDA 0x0518

Definition at line 301 of file reg.h.

#define TOTAL_CAM_ENTRY 32

Definition at line 645 of file reg.h.

#define TP_POLL 0x0500

Definition at line 296 of file reg.h.

#define TPPOLL_BEQ BIT(1)

Definition at line 708 of file reg.h.

#define TPPOLL_BKQ BIT(0)

Definition at line 707 of file reg.h.

#define TPPOLL_BQ BIT(4)

Definition at line 711 of file reg.h.

#define TPPOLL_CQ BIT(5)

Definition at line 712 of file reg.h.

#define TPPOLL_HCCAQ BIT(8)

Definition at line 715 of file reg.h.

#define TPPOLL_HQ BIT(7)

Definition at line 714 of file reg.h.

#define TPPOLL_MQ BIT(6)

Definition at line 713 of file reg.h.

#define TPPOLL_SHIFT 8

Definition at line 723 of file reg.h.

#define TPPOLL_STOPBE BIT(10)

Definition at line 717 of file reg.h.

#define TPPOLL_STOPBK BIT(9)

Definition at line 716 of file reg.h.

#define TPPOLL_STOPHCCA BIT(15)

Definition at line 722 of file reg.h.

#define TPPOLL_STOPHIGH BIT(14)

Definition at line 721 of file reg.h.

#define TPPOLL_STOPMGT BIT(13)

Definition at line 720 of file reg.h.

#define TPPOLL_STOPVI BIT(11)

Definition at line 718 of file reg.h.

#define TPPOLL_STOPVO BIT(12)

Definition at line 719 of file reg.h.

#define TPPOLL_VIQ BIT(2)

Definition at line 709 of file reg.h.

#define TPPOLL_VOQ BIT(3)

Definition at line 710 of file reg.h.

#define TRANSCEIVERA_HSPI_READBACK 0x8b8

Definition at line 970 of file reg.h.

#define TRANSCEIVERB_HSPI_READBACK 0x8bc

Definition at line 971 of file reg.h.

#define TRXDMA_STATUS 0x0156

Definition at line 167 of file reg.h.

#define TRXPKTBUF_DBG_CTRL 0x0348

Definition at line 280 of file reg.h.

#define TRXPKTBUF_DBG_DATA 0x0340

Definition at line 279 of file reg.h.

#define TSFEN BIT(8)

Definition at line 416 of file reg.h.

#define TSFR 0x0080

Definition at line 84 of file reg.h.

#define TSFRST BIT(9)

Definition at line 415 of file reg.h.

#define TVIDA 0x0528

Definition at line 305 of file reg.h.

#define TVODA 0x0524

Definition at line 304 of file reg.h.

#define TX_PWR_SAFETY_CHK 0x6D

Definition at line 765 of file reg.h.

#define TX_RATE_REG INIMCS_SEL

Definition at line 171 of file reg.h.

#define TXDESC_MSK 0x00DC

Definition at line 133 of file reg.h.

#define TXDMA_EN BIT(4)

Definition at line 390 of file reg.h.

#define TXDMA_INIT_VALUE

Value:

(IMEM_CHK_RPT | \

EXT_IMEM_CHK_RPT)

Definition at line 452 of file reg.h.

#define TXDMAPRE2FULL BIT(23)

Definition at line 409 of file reg.h.

#define TXFF_EMPTY_TH 0x00B9

Definition at line 120 of file reg.h.

#define TXFF_PG_NUM 0x0154

Definition at line 166 of file reg.h.

#define TXFF_STATUS 0x00B7

Definition at line 118 of file reg.h.

#define TXOP_STALL_CTRL 0x0238

Definition at line 223 of file reg.h.

#define TXPAUSE 0x0042

Definition at line 59 of file reg.h.

#define TXPKT_NUM_CTRL 0x0150

Definition at line 164 of file reg.h.

#define TXPKTBUF_PGBNDY 0x00B4

Definition at line 115 of file reg.h.

#define TXQ_PGADD 0x0152

Definition at line 165 of file reg.h.

#define TXRPTFF_RDPTR 0x00E0

Definition at line 134 of file reg.h.

#define TXRPTFF_WTPTR 0x00E4

Definition at line 135 of file reg.h.

#define USB_SIE_INTF_ADDR 0x0360

Definition at line 286 of file reg.h.

#define USB_SIE_INTF_CTRL 0x0363

Definition at line 289 of file reg.h.

#define USB_SIE_INTF_RD 0x0362

Definition at line 288 of file reg.h.

#define USB_SIE_INTF_WD 0x0361

Definition at line 287 of file reg.h.

#define USTIME 0x008A

Definition at line 86 of file reg.h.

#define USTIME_EDCA 0xFF00

Definition at line 504 of file reg.h.

#define USTIME_TSF 0x00FF

Definition at line 505 of file reg.h.

#define VI_ADMTM 0x01EC

Definition at line 199 of file reg.h.

#define VITID4_CTRL 0x0138

Definition at line 158 of file reg.h.

#define VITID5_CTRL 0x0134

Definition at line 157 of file reg.h.

#define VO_ADMTM 0x01E8

Definition at line 198 of file reg.h.

#define VOTID6_CTRL 0x0130

Definition at line 156 of file reg.h.

#define VOTID7_CTRL 0x012c

Definition at line 155 of file reg.h.

#define WDG_CTRL 0x0334

Definition at line 274 of file reg.h.

#define WFCRC 0x02D0

Definition at line 244 of file reg.h.

#define WFM0 0x0270

Definition at line 238 of file reg.h.

#define WFM1 0x0280

Definition at line 239 of file reg.h.

#define WFM2 0x0290

Definition at line 240 of file reg.h.

#define WFM3 0x02A0

Definition at line 241 of file reg.h.

#define WFM4 0x02B0

Definition at line 242 of file reg.h.

#define WFM5 0x02C0

Definition at line 243 of file reg.h.

#define WOW_CTRL 0x0260

Definition at line 233 of file reg.h.

#define WOW_MAGIC BIT(2)

Definition at line 654 of file reg.h.

#define WOW_PMEN BIT(0)

Definition at line 652 of file reg.h.

#define WOW_UWF BIT(3)

Definition at line 655 of file reg.h.

#define WOW_WOMEN BIT(1)

Definition at line 653 of file reg.h.

#define XTAL_GATE_AFE BIT(10)

Definition at line 372 of file reg.h.

Macros

Macro Definition Documentation