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28 #include <linux/bitops.h>
30 #define REGISTERS_BASE 0x00300000
31 #define DRPW_BASE 0x00310000
33 #define REGISTERS_DOWN_SIZE 0x00008800
34 #define REGISTERS_WORK_SIZE 0x0000b000
36 #define FW_STATUS_ADDR (0x14FC0 + 0xA000)
52 #define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
54 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
55 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
56 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
58 #define WL12XX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
59 #define WL12XX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
89 #define WL12XX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
99 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
109 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
120 #define WL12XX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
131 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
143 #define WL12XX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
145 #define WL12XX_REG_RX_DRIVER_COUNTER (REGISTERS_BASE + 0x0538)
148 #define SOR_CFG (REGISTERS_BASE + 0x0800)
170 #define WL12XX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
172 #define WL12XX_HI_CFG (REGISTERS_BASE + 0x0808)
189 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
191 #define WL12XX_OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
192 #define WL12XX_OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
193 #define WL12XX_OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
194 #define WL12XX_OCP_CMD (REGISTERS_BASE + 0x09C0)
196 #define WL12XX_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
198 #define WL12XX_CHIP_ID_B (REGISTERS_BASE + 0x5674)
200 #define WL12XX_ENABLE (REGISTERS_BASE + 0x5450)
203 #define WL12XX_ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
204 #define WL12XX_ELP_CMD (REGISTERS_BASE + 0x5808)
205 #define WL12XX_PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
206 #define WL12XX_CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
207 #define WL12XX_CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
209 #define WL12XX_CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
212 #define WL12XX_SCR_PAD0 (REGISTERS_BASE + 0x5608)
213 #define WL12XX_SCR_PAD1 (REGISTERS_BASE + 0x560C)
214 #define WL12XX_SCR_PAD2 (REGISTERS_BASE + 0x5610)
215 #define WL12XX_SCR_PAD3 (REGISTERS_BASE + 0x5614)
216 #define WL12XX_SCR_PAD4 (REGISTERS_BASE + 0x5618)
217 #define WL12XX_SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
218 #define WL12XX_SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
219 #define WL12XX_SCR_PAD5 (REGISTERS_BASE + 0x5624)
220 #define WL12XX_SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
221 #define WL12XX_SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
222 #define WL12XX_SCR_PAD6 (REGISTERS_BASE + 0x5630)
223 #define WL12XX_SCR_PAD7 (REGISTERS_BASE + 0x5634)
224 #define WL12XX_SCR_PAD8 (REGISTERS_BASE + 0x5638)
225 #define WL12XX_SCR_PAD9 (REGISTERS_BASE + 0x563C)
228 #define WL12XX_SPARE_A1 (REGISTERS_BASE + 0x0994)
229 #define WL12XX_SPARE_A2 (REGISTERS_BASE + 0x0998)
230 #define WL12XX_SPARE_A3 (REGISTERS_BASE + 0x099C)
231 #define WL12XX_SPARE_A4 (REGISTERS_BASE + 0x09A0)
232 #define WL12XX_SPARE_A5 (REGISTERS_BASE + 0x09A4)
233 #define WL12XX_SPARE_A6 (REGISTERS_BASE + 0x09A8)
234 #define WL12XX_SPARE_A7 (REGISTERS_BASE + 0x09AC)
235 #define WL12XX_SPARE_A8 (REGISTERS_BASE + 0x09B0)
236 #define WL12XX_SPARE_B1 (REGISTERS_BASE + 0x5420)
237 #define WL12XX_SPARE_B2 (REGISTERS_BASE + 0x5424)
238 #define WL12XX_SPARE_B3 (REGISTERS_BASE + 0x5428)
239 #define WL12XX_SPARE_B4 (REGISTERS_BASE + 0x542C)
240 #define WL12XX_SPARE_B5 (REGISTERS_BASE + 0x5430)
241 #define WL12XX_SPARE_B6 (REGISTERS_BASE + 0x5434)
242 #define WL12XX_SPARE_B7 (REGISTERS_BASE + 0x5438)
243 #define WL12XX_SPARE_B8 (REGISTERS_BASE + 0x543C)
245 #define WL12XX_PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
246 #define WL12XX_WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
247 #define WL12XX_WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
248 #define WL12XX_DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
250 #define WL12XX_CMD_MBOX_ADDRESS 0x407B4
252 #define ACX_REG_EEPROM_START_BIT BIT(1)
269 #define WL12XX_REG_COMMAND_MAILBOX_PTR (WL12XX_SCR_PAD0)
284 #define WL12XX_REG_EVENT_MAILBOX_PTR (WL12XX_SCR_PAD1)
301 #define ACX_EE_CTL_REG EE_CTL
302 #define EE_WRITE 0x00000001ul
303 #define EE_READ 0x00000002ul
311 #define ACX_EE_ADDR_REG EE_ADDR
320 #define ACX_EE_DATA_REG EE_DATA
331 #define ACX_EE_CFG EE_CFG
340 #define ACX_GPIO_OUT_REG GPIO_OUT
341 #define ACX_MAX_GPIO_LINES 15
351 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
352 #define ACX_CONT_WIND_MIN_MASK 0x0000007f
353 #define ACX_CONT_WIND_MAX 0x03ff0000
355 #define REF_FREQ_19_2 0
356 #define REF_FREQ_26_0 1
357 #define REF_FREQ_38_4 2
358 #define REF_FREQ_40_0 3
359 #define REF_FREQ_33_6 4
360 #define REF_FREQ_NUM 5
362 #define LUT_PARAM_INTEGER_DIVIDER 0
363 #define LUT_PARAM_FRACTIONAL_DIVIDER 1
364 #define LUT_PARAM_ATTN_BB 2
365 #define LUT_PARAM_ALPHA_BB 3
366 #define LUT_PARAM_STOP_TIME_BB 4
367 #define LUT_PARAM_BB_PLL_LOOP_FILTER 5
368 #define LUT_PARAM_NUM 6
370 #define WL12XX_EEPROMLESS_IND (WL12XX_SCR_PAD4)
372 #define NVS_DATA_BUNDARY_ALIGNMENT 4
375 #define FW_HDR_SIZE 8
383 #define SHORT_PREAMBLE_BIT BIT(0)
384 #define OFDM_RATE_BIT BIT(6)
385 #define PBCC_RATE_BIT BIT(7)
416 #define OCP_CMD_LOOP 32
417 #define OCP_CMD_WRITE 0x1
418 #define OCP_CMD_READ 0x2
419 #define OCP_READY_MASK BIT(18)
420 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
421 #define OCP_STATUS_NO_RESP 0x00000
422 #define OCP_STATUS_OK 0x10000
423 #define OCP_STATUS_REQ_FAILED 0x20000
424 #define OCP_STATUS_RESP_ERROR 0x30000
426 #define OCP_REG_POLARITY 0x0064
427 #define OCP_REG_CLK_TYPE 0x0448
428 #define OCP_REG_CLK_POLARITY 0x0cb2
429 #define OCP_REG_CLK_PULL 0x0cb4
431 #define POLARITY_LOW BIT(1)
432 #define NO_PULL (BIT(14) | BIT(15))
434 #define FREF_CLK_TYPE_BITS 0xfffffe7f
435 #define CLK_REQ_PRCM 0x100
436 #define FREF_CLK_POLARITY_BITS 0xfffff8ff
437 #define CLK_REQ_OUTN_SEL 0x700
439 #define WU_COUNTER_PAUSE_VAL 0x3FF
442 #define SYS_CLK_CFG_REG 0x2200
444 #define MCS_PLL_CLK_SEL_FREF BIT(0)
446 #define WL_CLK_REQ_TYPE_FREF BIT(3)
447 #define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2))
449 #define PRCM_CM_EN_MUX_WLAN_FREF BIT(4)
451 #define TCXO_ILOAD_INT_REG 0x2264
452 #define TCXO_CLK_DETECT_REG 0x2266
454 #define TCXO_DET_FAILED BIT(4)
456 #define FREF_ILOAD_INT_REG 0x2084
457 #define FREF_CLK_DETECT_REG 0x2086
458 #define FREF_CLK_DETECT_FAIL BIT(4)
461 #define WL_SPARE_REG 0x2320
462 #define WL_SPARE_VAL BIT(2)
464 #define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3))
466 #define PLL_LOCK_COUNTERS_REG 0xD8C
467 #define PLL_LOCK_COUNTERS_COEX 0x0F
468 #define PLL_LOCK_COUNTERS_MCS 0xF0
469 #define MCS_PLL_OVERRIDE_REG 0xD90
470 #define MCS_PLL_CONFIG_REG 0xD92
471 #define MCS_SEL_IN_FREQ_MASK 0x0070
472 #define MCS_SEL_IN_FREQ_SHIFT 4
473 #define MCS_PLL_CONFIG_REG_VAL 0x73
474 #define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1))
476 #define MCS_PLL_M_REG 0xD94
477 #define MCS_PLL_N_REG 0xD96
478 #define MCS_PLL_M_REG_VAL 0xC8
479 #define MCS_PLL_N_REG_VAL 0x07
481 #define SDIO_IO_DS 0xd14
499 #define WL12XX_INTR_TRIG_CMD BIT(0)
507 #define WL12XX_INTR_TRIG_EVENT_ACK BIT(1)
513 #define HI_CFG_UART_ENABLE 0x00000004
514 #define HI_CFG_RST232_ENABLE 0x00000008
515 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010
516 #define HI_CFG_HOST_INT_ENABLE 0x00000020
517 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
518 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
519 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
520 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
521 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
523 #define HI_CFG_DEF_VAL \
524 (HI_CFG_UART_ENABLE | \
525 HI_CFG_RST232_ENABLE | \
526 HI_CFG_CLOCK_REQ_SELECT | \
527 HI_CFG_HOST_INT_ENABLE)
529 #define WL127X_REG_FUSE_DATA_2_1 0x050a
530 #define WL128X_REG_FUSE_DATA_2_1 0x2152
531 #define PG_VER_MASK 0x3c
532 #define PG_VER_OFFSET 2
534 #define WL127X_PG_MAJOR_VER_MASK 0x3
535 #define WL127X_PG_MAJOR_VER_OFFSET 0x0
536 #define WL127X_PG_MINOR_VER_MASK 0xc
537 #define WL127X_PG_MINOR_VER_OFFSET 0x2
539 #define WL128X_PG_MAJOR_VER_MASK 0xc
540 #define WL128X_PG_MAJOR_VER_OFFSET 0x2
541 #define WL128X_PG_MINOR_VER_MASK 0x3
542 #define WL128X_PG_MINOR_VER_OFFSET 0x0
544 #define WL127X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL127X_PG_MAJOR_VER_MASK) >> \
545 WL127X_PG_MAJOR_VER_OFFSET)
546 #define WL127X_PG_GET_MINOR(pg_ver) ((pg_ver & WL127X_PG_MINOR_VER_MASK) >> \
547 WL127X_PG_MINOR_VER_OFFSET)
548 #define WL128X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL128X_PG_MAJOR_VER_MASK) >> \
549 WL128X_PG_MAJOR_VER_OFFSET)
550 #define WL128X_PG_GET_MINOR(pg_ver) ((pg_ver & WL128X_PG_MINOR_VER_MASK) >> \
551 WL128X_PG_MINOR_VER_OFFSET)
553 #define WL12XX_REG_FUSE_BD_ADDR_1 0x00310eb4
554 #define WL12XX_REG_FUSE_BD_ADDR_2 0x00310eb8