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reg.h
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1 /*
2  * This file is part of wl12xx
3  *
4  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5  * Copyright (C) 2009 Nokia Corporation
6  *
7  * Contact: Luciano Coelho <[email protected]>
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * version 2 as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21  * 02110-1301 USA
22  *
23  */
24 
25 #ifndef __REG_H__
26 #define __REG_H__
27 
28 #include <linux/bitops.h>
29 
30 #define REGISTERS_BASE 0x00300000
31 #define DRPW_BASE 0x00310000
32 
33 #define REGISTERS_DOWN_SIZE 0x00008800
34 #define REGISTERS_WORK_SIZE 0x0000b000
35 
36 #define FW_STATUS_ADDR (0x14FC0 + 0xA000)
37 
38 /*===============================================
39  Host Software Reset - 32bit RW
40  ------------------------------------------
41  [31:1] Reserved
42  0 SOFT_RESET Soft Reset - When this bit is set,
43  it holds the Wlan hardware in a soft reset state.
44  This reset disables all MAC and baseband processor
45  clocks except the CardBus/PCI interface clock.
46  It also initializes all MAC state machines except
47  the host interface. It does not reload the
48  contents of the EEPROM. When this bit is cleared
49  (not self-clearing), the Wlan hardware
50  exits the software reset state.
51 ===============================================*/
52 #define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
53 
54 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
55 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
56 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
57 
58 #define WL12XX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
59 #define WL12XX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
60 
61 /*=============================================
62  Host Interrupt Mask Register - 32bit (RW)
63  ------------------------------------------
64  Setting a bit in this register masks the
65  corresponding interrupt to the host.
66  0 - RX0 - Rx first dubble buffer Data Interrupt
67  1 - TXD - Tx Data Interrupt
68  2 - TXXFR - Tx Transfer Interrupt
69  3 - RX1 - Rx second dubble buffer Data Interrupt
70  4 - RXXFR - Rx Transfer Interrupt
71  5 - EVENT_A - Event Mailbox interrupt
72  6 - EVENT_B - Event Mailbox interrupt
73  7 - WNONHST - Wake On Host Interrupt
74  8 - TRACE_A - Debug Trace interrupt
75  9 - TRACE_B - Debug Trace interrupt
76  10 - CDCMP - Command Complete Interrupt
77  11 -
78  12 -
79  13 -
80  14 - ICOMP - Initialization Complete Interrupt
81  16 - SG SE - Soft Gemini - Sense enable interrupt
82  17 - SG SD - Soft Gemini - Sense disable interrupt
83  18 - -
84  19 - -
85  20 - -
86  21- -
87  Default: 0x0001
88 *==============================================*/
89 #define WL12XX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
90 
91 /*=============================================
92  Host Interrupt Mask Set 16bit, (Write only)
93  ------------------------------------------
94  Setting a bit in this register sets
95  the corresponding bin in ACX_HINT_MASK register
96  without effecting the mask
97  state of other bits (0 = no effect).
98 ==============================================*/
99 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
100 
101 /*=============================================
102  Host Interrupt Mask Clear 16bit,(Write only)
103  ------------------------------------------
104  Setting a bit in this register clears
105  the corresponding bin in ACX_HINT_MASK register
106  without effecting the mask
107  state of other bits (0 = no effect).
108 =============================================*/
109 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
110 
111 /*=============================================
112  Host Interrupt Status Nondestructive Read
113  16bit,(Read only)
114  ------------------------------------------
115  The host can read this register to determine
116  which interrupts are active.
117  Reading this register doesn't
118  effect its content.
119 =============================================*/
120 #define WL12XX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
121 
122 /*=============================================
123  Host Interrupt Status Clear on Read Register
124  16bit,(Read only)
125  ------------------------------------------
126  The host can read this register to determine
127  which interrupts are active.
128  Reading this register clears it,
129  thus making all interrupts inactive.
130 ==============================================*/
131 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
132 
133 /*=============================================
134  Host Interrupt Acknowledge Register
135  16bit,(Write only)
136  ------------------------------------------
137  The host can set individual bits in this
138  register to clear (acknowledge) the corresp.
139  interrupt status bits in the HINT_STS_CLR and
140  HINT_STS_ND registers, thus making the
141  assotiated interrupt inactive. (0-no effect)
142 ==============================================*/
143 #define WL12XX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
144 
145 #define WL12XX_REG_RX_DRIVER_COUNTER (REGISTERS_BASE + 0x0538)
146 
147 /* Device Configuration registers*/
148 #define SOR_CFG (REGISTERS_BASE + 0x0800)
149 
150 /* Embedded ARM CPU Control */
151 
152 /*===============================================
153  Halt eCPU - 32bit RW
154  ------------------------------------------
155  0 HALT_ECPU Halt Embedded CPU - This bit is the
156  compliment of bit 1 (MDATA2) in the SOR_CFG register.
157  During a hardware reset, this bit holds
158  the inverse of MDATA2.
159  When downloading firmware from the host,
160  set this bit (pull down MDATA2).
161  The host clears this bit after downloading the firmware into
162  zero-wait-state SSRAM.
163  When loading firmware from Flash, clear this bit (pull up MDATA2)
164  so that the eCPU can run the bootloader code in Flash
165  HALT_ECPU eCPU State
166  --------------------
167  1 halt eCPU
168  0 enable eCPU
169  ===============================================*/
170 #define WL12XX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
171 
172 #define WL12XX_HI_CFG (REGISTERS_BASE + 0x0808)
173 
174 /*===============================================
175  EEPROM Burst Read Start - 32bit RW
176  ------------------------------------------
177  [31:1] Reserved
178  0 ACX_EE_START - EEPROM Burst Read Start 0
179  Setting this bit starts a burst read from
180  the external EEPROM.
181  If this bit is set (after reset) before an EEPROM read/write,
182  the burst read starts at EEPROM address 0.
183  Otherwise, it starts at the address
184  following the address of the previous access.
185  TheWlan hardware hardware clears this bit automatically.
186 
187  Default: 0x00000000
188 *================================================*/
189 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
190 
191 #define WL12XX_OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
192 #define WL12XX_OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
193 #define WL12XX_OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
194 #define WL12XX_OCP_CMD (REGISTERS_BASE + 0x09C0)
195 
196 #define WL12XX_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
197 
198 #define WL12XX_CHIP_ID_B (REGISTERS_BASE + 0x5674)
199 
200 #define WL12XX_ENABLE (REGISTERS_BASE + 0x5450)
201 
202 /* Power Management registers */
203 #define WL12XX_ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
204 #define WL12XX_ELP_CMD (REGISTERS_BASE + 0x5808)
205 #define WL12XX_PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
206 #define WL12XX_CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
207 #define WL12XX_CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
208 
209 #define WL12XX_CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
210 
211 /* Scratch Pad registers*/
212 #define WL12XX_SCR_PAD0 (REGISTERS_BASE + 0x5608)
213 #define WL12XX_SCR_PAD1 (REGISTERS_BASE + 0x560C)
214 #define WL12XX_SCR_PAD2 (REGISTERS_BASE + 0x5610)
215 #define WL12XX_SCR_PAD3 (REGISTERS_BASE + 0x5614)
216 #define WL12XX_SCR_PAD4 (REGISTERS_BASE + 0x5618)
217 #define WL12XX_SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
218 #define WL12XX_SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
219 #define WL12XX_SCR_PAD5 (REGISTERS_BASE + 0x5624)
220 #define WL12XX_SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
221 #define WL12XX_SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
222 #define WL12XX_SCR_PAD6 (REGISTERS_BASE + 0x5630)
223 #define WL12XX_SCR_PAD7 (REGISTERS_BASE + 0x5634)
224 #define WL12XX_SCR_PAD8 (REGISTERS_BASE + 0x5638)
225 #define WL12XX_SCR_PAD9 (REGISTERS_BASE + 0x563C)
226 
227 /* Spare registers*/
228 #define WL12XX_SPARE_A1 (REGISTERS_BASE + 0x0994)
229 #define WL12XX_SPARE_A2 (REGISTERS_BASE + 0x0998)
230 #define WL12XX_SPARE_A3 (REGISTERS_BASE + 0x099C)
231 #define WL12XX_SPARE_A4 (REGISTERS_BASE + 0x09A0)
232 #define WL12XX_SPARE_A5 (REGISTERS_BASE + 0x09A4)
233 #define WL12XX_SPARE_A6 (REGISTERS_BASE + 0x09A8)
234 #define WL12XX_SPARE_A7 (REGISTERS_BASE + 0x09AC)
235 #define WL12XX_SPARE_A8 (REGISTERS_BASE + 0x09B0)
236 #define WL12XX_SPARE_B1 (REGISTERS_BASE + 0x5420)
237 #define WL12XX_SPARE_B2 (REGISTERS_BASE + 0x5424)
238 #define WL12XX_SPARE_B3 (REGISTERS_BASE + 0x5428)
239 #define WL12XX_SPARE_B4 (REGISTERS_BASE + 0x542C)
240 #define WL12XX_SPARE_B5 (REGISTERS_BASE + 0x5430)
241 #define WL12XX_SPARE_B6 (REGISTERS_BASE + 0x5434)
242 #define WL12XX_SPARE_B7 (REGISTERS_BASE + 0x5438)
243 #define WL12XX_SPARE_B8 (REGISTERS_BASE + 0x543C)
244 
245 #define WL12XX_PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
246 #define WL12XX_WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
247 #define WL12XX_WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
248 #define WL12XX_DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
249 
250 #define WL12XX_CMD_MBOX_ADDRESS 0x407B4
251 
252 #define ACX_REG_EEPROM_START_BIT BIT(1)
253 
254 /* Command/Information Mailbox Pointers */
255 
256 /*===============================================
257  Command Mailbox Pointer - 32bit RW
258  ------------------------------------------
259  This register holds the start address of
260  the command mailbox located in the Wlan hardware memory.
261  The host must read this pointer after a reset to
262  find the location of the command mailbox.
263  The Wlan hardware initializes the command mailbox
264  pointer with the default address of the command mailbox.
265  The command mailbox pointer is not valid until after
266  the host receives the Init Complete interrupt from
267  the Wlan hardware.
268  ===============================================*/
269 #define WL12XX_REG_COMMAND_MAILBOX_PTR (WL12XX_SCR_PAD0)
270 
271 /*===============================================
272  Information Mailbox Pointer - 32bit RW
273  ------------------------------------------
274  This register holds the start address of
275  the information mailbox located in the Wlan hardware memory.
276  The host must read this pointer after a reset to find
277  the location of the information mailbox.
278  The Wlan hardware initializes the information mailbox pointer
279  with the default address of the information mailbox.
280  The information mailbox pointer is not valid
281  until after the host receives the Init Complete interrupt from
282  the Wlan hardware.
283  ===============================================*/
284 #define WL12XX_REG_EVENT_MAILBOX_PTR (WL12XX_SCR_PAD1)
285 
286 /*===============================================
287  EEPROM Read/Write Request 32bit RW
288  ------------------------------------------
289  1 EE_READ - EEPROM Read Request 1 - Setting this bit
290  loads a single byte of data into the EE_DATA
291  register from the EEPROM location specified in
292  the EE_ADDR register.
293  The Wlan hardware hardware clears this bit automatically.
294  EE_DATA is valid when this bit is cleared.
295 
296  0 EE_WRITE - EEPROM Write Request - Setting this bit
297  writes a single byte of data from the EE_DATA register into the
298  EEPROM location specified in the EE_ADDR register.
299  The Wlan hardware hardware clears this bit automatically.
300 *===============================================*/
301 #define ACX_EE_CTL_REG EE_CTL
302 #define EE_WRITE 0x00000001ul
303 #define EE_READ 0x00000002ul
304 
305 /*===============================================
306  EEPROM Address - 32bit RW
307  ------------------------------------------
308  This register specifies the address
309  within the EEPROM from/to which to read/write data.
310  ===============================================*/
311 #define ACX_EE_ADDR_REG EE_ADDR
312 
313 /*===============================================
314  EEPROM Data - 32bit RW
315  ------------------------------------------
316  This register either holds the read 8 bits of
317  data from the EEPROM or the write data
318  to be written to the EEPROM.
319  ===============================================*/
320 #define ACX_EE_DATA_REG EE_DATA
321 
322 /*===============================================
323  EEPROM Base Address - 32bit RW
324  ------------------------------------------
325  This register holds the upper nine bits
326  [23:15] of the 24-bit Wlan hardware memory
327  address for burst reads from EEPROM accesses.
328  The EEPROM provides the lower 15 bits of this address.
329  The MSB of the address from the EEPROM is ignored.
330  ===============================================*/
331 #define ACX_EE_CFG EE_CFG
332 
333 /*===============================================
334  GPIO Output Values -32bit, RW
335  ------------------------------------------
336  [31:16] Reserved
337  [15: 0] Specify the output values (at the output driver inputs) for
338  GPIO[15:0], respectively.
339  ===============================================*/
340 #define ACX_GPIO_OUT_REG GPIO_OUT
341 #define ACX_MAX_GPIO_LINES 15
342 
343 /*===============================================
344  Contention window -32bit, RW
345  ------------------------------------------
346  [31:26] Reserved
347  [25:16] Max (0x3ff)
348  [15:07] Reserved
349  [06:00] Current contention window value - default is 0x1F
350  ===============================================*/
351 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
352 #define ACX_CONT_WIND_MIN_MASK 0x0000007f
353 #define ACX_CONT_WIND_MAX 0x03ff0000
354 
355 #define REF_FREQ_19_2 0
356 #define REF_FREQ_26_0 1
357 #define REF_FREQ_38_4 2
358 #define REF_FREQ_40_0 3
359 #define REF_FREQ_33_6 4
360 #define REF_FREQ_NUM 5
361 
362 #define LUT_PARAM_INTEGER_DIVIDER 0
363 #define LUT_PARAM_FRACTIONAL_DIVIDER 1
364 #define LUT_PARAM_ATTN_BB 2
365 #define LUT_PARAM_ALPHA_BB 3
366 #define LUT_PARAM_STOP_TIME_BB 4
367 #define LUT_PARAM_BB_PLL_LOOP_FILTER 5
368 #define LUT_PARAM_NUM 6
369 
370 #define WL12XX_EEPROMLESS_IND (WL12XX_SCR_PAD4)
371 #define USE_EEPROM 0
372 #define NVS_DATA_BUNDARY_ALIGNMENT 4
373 
374 /* Firmware image header size */
375 #define FW_HDR_SIZE 8
376 
377 /******************************************************************************
378 
379  CHANNELS, BAND & REG DOMAINS definitions
380 
381 ******************************************************************************/
382 
383 #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
384 #define OFDM_RATE_BIT BIT(6)
385 #define PBCC_RATE_BIT BIT(7)
386 
387 enum {
388  CCK_LONG = 0,
393 };
394 
395 /******************************************************************************
396 
397 Transmit-Descriptor RATE-SET field definitions...
398 
399 Define a new "Rate-Set" for TX path that incorporates the
400 Rate & Modulation info into a single 16-bit field.
401 
402 TxdRateSet_t:
403 b15 - Indicates Preamble type (1=SHORT, 0=LONG).
404  Notes:
405  Must be LONG (0) for 1Mbps rate.
406  Does not apply (set to 0) for RevG-OFDM rates.
407 b14 - Indicates PBCC encoding (1=PBCC, 0=not).
408  Notes:
409  Does not apply (set to 0) for rates 1 and 2 Mbps.
410  Does not apply (set to 0) for RevG-OFDM rates.
411 b13 - Unused (set to 0).
412 b12-b0 - Supported Rate indicator bits as defined below.
413 
414 ******************************************************************************/
415 
416 #define OCP_CMD_LOOP 32
417 #define OCP_CMD_WRITE 0x1
418 #define OCP_CMD_READ 0x2
419 #define OCP_READY_MASK BIT(18)
420 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
421 #define OCP_STATUS_NO_RESP 0x00000
422 #define OCP_STATUS_OK 0x10000
423 #define OCP_STATUS_REQ_FAILED 0x20000
424 #define OCP_STATUS_RESP_ERROR 0x30000
425 
426 #define OCP_REG_POLARITY 0x0064
427 #define OCP_REG_CLK_TYPE 0x0448
428 #define OCP_REG_CLK_POLARITY 0x0cb2
429 #define OCP_REG_CLK_PULL 0x0cb4
430 
431 #define POLARITY_LOW BIT(1)
432 #define NO_PULL (BIT(14) | BIT(15))
433 
434 #define FREF_CLK_TYPE_BITS 0xfffffe7f
435 #define CLK_REQ_PRCM 0x100
436 #define FREF_CLK_POLARITY_BITS 0xfffff8ff
437 #define CLK_REQ_OUTN_SEL 0x700
438 
439 #define WU_COUNTER_PAUSE_VAL 0x3FF
440 
441 /* PLL configuration algorithm for wl128x */
442 #define SYS_CLK_CFG_REG 0x2200
443 /* Bit[0] - 0-TCXO, 1-FREF */
444 #define MCS_PLL_CLK_SEL_FREF BIT(0)
445 /* Bit[3:2] - 01-TCXO, 10-FREF */
446 #define WL_CLK_REQ_TYPE_FREF BIT(3)
447 #define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2))
448 /* Bit[4] - 0-TCXO, 1-FREF */
449 #define PRCM_CM_EN_MUX_WLAN_FREF BIT(4)
450 
451 #define TCXO_ILOAD_INT_REG 0x2264
452 #define TCXO_CLK_DETECT_REG 0x2266
453 
454 #define TCXO_DET_FAILED BIT(4)
455 
456 #define FREF_ILOAD_INT_REG 0x2084
457 #define FREF_CLK_DETECT_REG 0x2086
458 #define FREF_CLK_DETECT_FAIL BIT(4)
459 
460 /* Use this reg for masking during driver access */
461 #define WL_SPARE_REG 0x2320
462 #define WL_SPARE_VAL BIT(2)
463 /* Bit[6:5:3] - mask wl write SYS_CLK_CFG[8:5:2:4] */
464 #define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3))
465 
466 #define PLL_LOCK_COUNTERS_REG 0xD8C
467 #define PLL_LOCK_COUNTERS_COEX 0x0F
468 #define PLL_LOCK_COUNTERS_MCS 0xF0
469 #define MCS_PLL_OVERRIDE_REG 0xD90
470 #define MCS_PLL_CONFIG_REG 0xD92
471 #define MCS_SEL_IN_FREQ_MASK 0x0070
472 #define MCS_SEL_IN_FREQ_SHIFT 4
473 #define MCS_PLL_CONFIG_REG_VAL 0x73
474 #define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1))
475 
476 #define MCS_PLL_M_REG 0xD94
477 #define MCS_PLL_N_REG 0xD96
478 #define MCS_PLL_M_REG_VAL 0xC8
479 #define MCS_PLL_N_REG_VAL 0x07
480 
481 #define SDIO_IO_DS 0xd14
482 
483 /* SDIO/wSPI DS configuration values */
484 enum {
486  HCI_IO_DS_4MA = 1, /* default */
489 };
490 
491 /* end PLL configuration algorithm for wl128x */
492 
493 /*
494  * Host Command Interrupt. Setting this bit masks
495  * the interrupt that the host issues to inform
496  * the FW that it has sent a command
497  * to the Wlan hardware Command Mailbox.
498  */
499 #define WL12XX_INTR_TRIG_CMD BIT(0)
500 
501 /*
502  * Host Event Acknowlegde Interrupt. The host
503  * sets this bit to acknowledge that it received
504  * the unsolicited information from the event
505  * mailbox.
506  */
507 #define WL12XX_INTR_TRIG_EVENT_ACK BIT(1)
508 
509 /*===============================================
510  HI_CFG Interface Configuration Register Values
511  ------------------------------------------
512  ===============================================*/
513 #define HI_CFG_UART_ENABLE 0x00000004
514 #define HI_CFG_RST232_ENABLE 0x00000008
515 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010
516 #define HI_CFG_HOST_INT_ENABLE 0x00000020
517 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
518 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
519 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
520 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
521 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
522 
523 #define HI_CFG_DEF_VAL \
524  (HI_CFG_UART_ENABLE | \
525  HI_CFG_RST232_ENABLE | \
526  HI_CFG_CLOCK_REQ_SELECT | \
527  HI_CFG_HOST_INT_ENABLE)
528 
529 #define WL127X_REG_FUSE_DATA_2_1 0x050a
530 #define WL128X_REG_FUSE_DATA_2_1 0x2152
531 #define PG_VER_MASK 0x3c
532 #define PG_VER_OFFSET 2
533 
534 #define WL127X_PG_MAJOR_VER_MASK 0x3
535 #define WL127X_PG_MAJOR_VER_OFFSET 0x0
536 #define WL127X_PG_MINOR_VER_MASK 0xc
537 #define WL127X_PG_MINOR_VER_OFFSET 0x2
538 
539 #define WL128X_PG_MAJOR_VER_MASK 0xc
540 #define WL128X_PG_MAJOR_VER_OFFSET 0x2
541 #define WL128X_PG_MINOR_VER_MASK 0x3
542 #define WL128X_PG_MINOR_VER_OFFSET 0x0
543 
544 #define WL127X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL127X_PG_MAJOR_VER_MASK) >> \
545  WL127X_PG_MAJOR_VER_OFFSET)
546 #define WL127X_PG_GET_MINOR(pg_ver) ((pg_ver & WL127X_PG_MINOR_VER_MASK) >> \
547  WL127X_PG_MINOR_VER_OFFSET)
548 #define WL128X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL128X_PG_MAJOR_VER_MASK) >> \
549  WL128X_PG_MAJOR_VER_OFFSET)
550 #define WL128X_PG_GET_MINOR(pg_ver) ((pg_ver & WL128X_PG_MINOR_VER_MASK) >> \
551  WL128X_PG_MINOR_VER_OFFSET)
552 
553 #define WL12XX_REG_FUSE_BD_ADDR_1 0x00310eb4
554 #define WL12XX_REG_FUSE_BD_ADDR_2 0x00310eb8
555 
556 #endif