reg.h File Reference

#include <linux/bitops.h>

Go to the source code of this file.

Macros
#define	REGISTERS_BASE   0x00300000
#define	DRPW_BASE   0x00310000
#define	REGISTERS_DOWN_SIZE   0x00008800
#define	REGISTERS_WORK_SIZE   0x0000b000
#define	HW_ACCESS_ELP_CTRL_REG_ADDR   0x1FFFC
#define	ELPCTRL_WAKE_UP   0x1
#define	ELPCTRL_WAKE_UP_WLAN_READY   0x5
#define	ELPCTRL_SLEEP   0x0
#define	ELPCTRL_WLAN_READY   0x2
#define	SOR_CFG   (REGISTERS_BASE + 0x0800)
#define	ECPU_CTRL   (REGISTERS_BASE + 0x0804)
#define	HI_CFG   (REGISTERS_BASE + 0x0808)
#define	EE_START   (REGISTERS_BASE + 0x080C)
#define	EE_CTL   (REGISTERS_BASE + 0x2000)
#define	EE_DATA   (REGISTERS_BASE + 0x2004)
#define	EE_ADDR   (REGISTERS_BASE + 0x2008)
#define	EE_CTL_READ   2
#define	CHIP_ID_B   (REGISTERS_BASE + 0x5674)
#define	CHIP_ID_1251_PG10   (0x7010101)
#define	CHIP_ID_1251_PG11   (0x7020101)
#define	CHIP_ID_1251_PG12   (0x7030101)
#define	ENABLE   (REGISTERS_BASE + 0x5450)
#define	ELP_CFG_MODE   (REGISTERS_BASE + 0x5804)
#define	ELP_CMD   (REGISTERS_BASE + 0x5808)
#define	PLL_CAL_TIME   (REGISTERS_BASE + 0x5810)
#define	CLK_REQ_TIME   (REGISTERS_BASE + 0x5814)
#define	CLK_BUF_TIME   (REGISTERS_BASE + 0x5818)
#define	CFG_PLL_SYNC_CNT   (REGISTERS_BASE + 0x5820)
#define	SCR_PAD0   (REGISTERS_BASE + 0x5608)
#define	SCR_PAD1   (REGISTERS_BASE + 0x560C)
#define	SCR_PAD2   (REGISTERS_BASE + 0x5610)
#define	SCR_PAD3   (REGISTERS_BASE + 0x5614)
#define	SCR_PAD4   (REGISTERS_BASE + 0x5618)
#define	SCR_PAD4_SET   (REGISTERS_BASE + 0x561C)
#define	SCR_PAD4_CLR   (REGISTERS_BASE + 0x5620)
#define	SCR_PAD5   (REGISTERS_BASE + 0x5624)
#define	SCR_PAD5_SET   (REGISTERS_BASE + 0x5628)
#define	SCR_PAD5_CLR   (REGISTERS_BASE + 0x562C)
#define	SCR_PAD6   (REGISTERS_BASE + 0x5630)
#define	SCR_PAD7   (REGISTERS_BASE + 0x5634)
#define	SCR_PAD8   (REGISTERS_BASE + 0x5638)
#define	SCR_PAD9   (REGISTERS_BASE + 0x563C)
#define	SPARE_A1   (REGISTERS_BASE + 0x0994)
#define	SPARE_A2   (REGISTERS_BASE + 0x0998)
#define	SPARE_A3   (REGISTERS_BASE + 0x099C)
#define	SPARE_A4   (REGISTERS_BASE + 0x09A0)
#define	SPARE_A5   (REGISTERS_BASE + 0x09A4)
#define	SPARE_A6   (REGISTERS_BASE + 0x09A8)
#define	SPARE_A7   (REGISTERS_BASE + 0x09AC)
#define	SPARE_A8   (REGISTERS_BASE + 0x09B0)
#define	SPARE_B1   (REGISTERS_BASE + 0x5420)
#define	SPARE_B2   (REGISTERS_BASE + 0x5424)
#define	SPARE_B3   (REGISTERS_BASE + 0x5428)
#define	SPARE_B4   (REGISTERS_BASE + 0x542C)
#define	SPARE_B5   (REGISTERS_BASE + 0x5430)
#define	SPARE_B6   (REGISTERS_BASE + 0x5434)
#define	SPARE_B7   (REGISTERS_BASE + 0x5438)
#define	SPARE_B8   (REGISTERS_BASE + 0x543C)
#define	ACX_SLV_SOFT_RESET_BIT   BIT(0)
#define	ACX_REG_EEPROM_START_BIT   BIT(0)
#define	REG_COMMAND_MAILBOX_PTR   (SCR_PAD0)
#define	REG_EVENT_MAILBOX_PTR   (SCR_PAD1)
#define	REG_ENABLE_TX_RX   (ENABLE)
#define	REG_RX_CONFIG   (RX_CFG)
#define	REG_RX_FILTER   (RX_FILTER_CFG)
#define	RX_CFG_ENABLE_PHY_HEADER_PLCP   0x0002
#define	RX_CFG_PROMISCUOUS   0x0008
#define	RX_CFG_BSSID   0x0020
#define	RX_CFG_MAC   0x0010
#define	RX_CFG_ENABLE_ONLY_MY_DEST_MAC   0x0010
#define	RX_CFG_ENABLE_ANY_DEST_MAC   0x0000
#define	RX_CFG_ENABLE_ONLY_MY_BSSID   0x0020
#define	RX_CFG_ENABLE_ANY_BSSID   0x0000
#define	RX_CFG_DISABLE_BCAST   0x0200
#define	RX_CFG_ENABLE_ONLY_MY_SSID   0x0400
#define	RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR   0x0800
#define	RX_CFG_COPY_RX_STATUS   0x2000
#define	RX_CFG_TSF   0x10000
#define	RX_CONFIG_OPTION_ANY_DST_MY_BSS
#define	RX_CONFIG_OPTION_MY_DST_ANY_BSS
#define	RX_CONFIG_OPTION_ANY_DST_ANY_BSS
#define	RX_CONFIG_OPTION_MY_DST_MY_BSS
#define	RX_CONFIG_OPTION_FOR_SCAN
#define	RX_CONFIG_OPTION_FOR_MEASUREMENT   (RX_CFG_ENABLE_ANY_DEST_MAC)
#define	RX_CONFIG_OPTION_FOR_JOIN
#define	RX_CONFIG_OPTION_FOR_IBSS_JOIN
#define	RX_FILTER_OPTION_DEF
#define	RX_FILTER_OPTION_FILTER_ALL   0
#define	RX_FILTER_OPTION_DEF_PRSP_BCN
#define	RX_FILTER_OPTION_JOIN
#define	EE_CTL   (REGISTERS_BASE + 0x2000)
#define	ACX_EE_CTL_REG   EE_CTL
#define	EE_WRITE   0x00000001ul
#define	EE_READ   0x00000002ul
#define	EE_ADDR   (REGISTERS_BASE + 0x2008)
#define	ACX_EE_ADDR_REG   EE_ADDR
#define	EE_DATA   (REGISTERS_BASE + 0x2004)
#define	ACX_EE_DATA_REG   EE_DATA
#define	EEPROM_ACCESS_TO   10000 /* timeout counter */
#define	START_EEPROM_MGR   0x00000001
#define	ACX_EE_CFG   EE_CFG
#define	ACX_GPIO_OUT_REG   GPIO_OUT
#define	ACX_MAX_GPIO_LINES   15
#define	ACX_CONT_WIND_CFG_REG   CONT_WIND_CFG
#define	ACX_CONT_WIND_MIN_MASK   0x0000007f
#define	ACX_CONT_WIND_MAX   0x03ff0000
#define	HI_CFG_UART_ENABLE   0x00000004
#define	HI_CFG_RST232_ENABLE   0x00000008
#define	HI_CFG_CLOCK_REQ_SELECT   0x00000010
#define	HI_CFG_HOST_INT_ENABLE   0x00000020
#define	HI_CFG_VLYNQ_OUTPUT_ENABLE   0x00000040
#define	HI_CFG_HOST_INT_ACTIVE_LOW   0x00000080
#define	HI_CFG_UART_TX_OUT_GPIO_15   0x00000100
#define	HI_CFG_UART_TX_OUT_GPIO_14   0x00000200
#define	HI_CFG_UART_TX_OUT_GPIO_7   0x00000400
#define	HI_CFG_DEF_VAL
#define	REF_FREQ_19_2   0
#define	REF_FREQ_26_0   1
#define	REF_FREQ_38_4   2
#define	REF_FREQ_40_0   3
#define	REF_FREQ_33_6   4
#define	REF_FREQ_NUM   5
#define	LUT_PARAM_INTEGER_DIVIDER   0
#define	LUT_PARAM_FRACTIONAL_DIVIDER   1
#define	LUT_PARAM_ATTN_BB   2
#define	LUT_PARAM_ALPHA_BB   3
#define	LUT_PARAM_STOP_TIME_BB   4
#define	LUT_PARAM_BB_PLL_LOOP_FILTER   5
#define	LUT_PARAM_NUM   6
#define	ACX_EEPROMLESS_IND_REG   (SCR_PAD4)
#define	USE_EEPROM   0
#define	SOFT_RESET_MAX_TIME   1000000
#define	SOFT_RESET_STALL_TIME   1000
#define	NVS_DATA_BUNDARY_ALIGNMENT   4
#define	CHUNK_SIZE   512
#define	FW_HDR_SIZE   8
#define	ECPU_CONTROL_HALT   0x00000101
#define	SHORT_PREAMBLE_BIT   BIT(0) /* CCK or Barker depending on the rate */
#define	OFDM_RATE_BIT   BIT(6)
#define	PBCC_RATE_BIT   BIT(7)
#define	INTR_TRIG_CMD   BIT(0)
#define	INTR_TRIG_EVENT_ACK   BIT(1)
#define	INTR_TRIG_TX_PROC0   BIT(2)
#define	INTR_TRIG_RX_PROC0   BIT(3)
#define	INTR_TRIG_DEBUG_ACK   BIT(4)
#define	INTR_TRIG_STATE_CHANGED   BIT(5)
#define	INTR_TRIG_RX_PROC1   BIT(17)
#define	INTR_TRIG_TX_PROC1   BIT(18)

Enumerations
enum	wl12xx_acx_int_reg {   ACX_REG_INTERRUPT_TRIG, ACX_REG_INTERRUPT_TRIG_H, ACX_REG_INTERRUPT_MASK, ACX_REG_HINT_MASK_SET,   ACX_REG_HINT_MASK_CLR, ACX_REG_INTERRUPT_NO_CLEAR, ACX_REG_INTERRUPT_CLEAR, ACX_REG_INTERRUPT_ACK,   ACX_REG_SLV_SOFT_RESET, ACX_REG_EE_START, ACX_REG_ECPU_CONTROL, ACX_REG_TABLE_LEN }
enum	{   RADIO_BAND_2_4GHZ = 0, RADIO_BAND_5GHZ = 1, RADIO_BAND_JAPAN_4_9_GHZ = 2, DEFAULT_BAND = RADIO_BAND_2_4GHZ,   INVALID_BAND = 0xFE, MAX_RADIO_BANDS = 0xFF }
enum	{   NO_RATE = 0, RATE_1MBPS = 0x0A, RATE_2MBPS = 0x14, RATE_5_5MBPS = 0x37,   RATE_6MBPS = 0x0B, RATE_9MBPS = 0x0F, RATE_11MBPS = 0x6E, RATE_12MBPS = 0x0A,   RATE_18MBPS = 0x0E, RATE_22MBPS = 0xDC, RATE_24MBPS = 0x09, RATE_36MBPS = 0x0D,   RATE_48MBPS = 0x08, RATE_54MBPS = 0x0C }
enum	{   RATE_INDEX_1MBPS = 0, RATE_INDEX_2MBPS = 1, RATE_INDEX_5_5MBPS = 2, RATE_INDEX_6MBPS = 3,   RATE_INDEX_9MBPS = 4, RATE_INDEX_11MBPS = 5, RATE_INDEX_12MBPS = 6, RATE_INDEX_18MBPS = 7,   RATE_INDEX_22MBPS = 8, RATE_INDEX_24MBPS = 9, RATE_INDEX_36MBPS = 10, RATE_INDEX_48MBPS = 11,   RATE_INDEX_54MBPS = 12, RATE_INDEX_MAX = RATE_INDEX_54MBPS, MAX_RATE_INDEX, INVALID_RATE_INDEX = MAX_RATE_INDEX,   RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF }
enum	{ RATE_MASK_1MBPS = 0x1, RATE_MASK_2MBPS = 0x2, RATE_MASK_5_5MBPS = 0x4, RATE_MASK_11MBPS = 0x20 }
enum	{   CCK_LONG = 0, CCK_SHORT = SHORT_PREAMBLE_BIT, PBCC_LONG = PBCC_RATE_BIT, PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,   OFDM = OFDM_RATE_BIT }

Macro Definition Documentation

#define ACX_CONT_WIND_CFG_REG   CONT_WIND_CFG

Definition at line 434 of file reg.h.

#define ACX_CONT_WIND_MAX   0x03ff0000

Definition at line 436 of file reg.h.

#define ACX_CONT_WIND_MIN_MASK   0x0000007f

Definition at line 435 of file reg.h.

#define ACX_EE_ADDR_REG   EE_ADDR

Definition at line 390 of file reg.h.

#define ACX_EE_CFG   EE_CFG

Definition at line 414 of file reg.h.

#define ACX_EE_CTL_REG   EE_CTL

Definition at line 379 of file reg.h.

#define ACX_EE_DATA_REG   EE_DATA

Definition at line 400 of file reg.h.

#define ACX_EEPROMLESS_IND_REG   (SCR_PAD4)

Definition at line 486 of file reg.h.

#define ACX_GPIO_OUT_REG   GPIO_OUT

Definition at line 423 of file reg.h.

#define ACX_MAX_GPIO_LINES   15

Definition at line 424 of file reg.h.

#define ACX_REG_EEPROM_START_BIT   BIT(0)

Definition at line 254 of file reg.h.

#define ACX_SLV_SOFT_RESET_BIT   BIT(0)

Definition at line 253 of file reg.h.

#define CFG_PLL_SYNC_CNT   (REGISTERS_BASE + 0x5820)

Definition at line 71 of file reg.h.

#define CHIP_ID_1251_PG10   (0x7010101)

Definition at line 58 of file reg.h.

#define CHIP_ID_1251_PG11   (0x7020101)

Definition at line 59 of file reg.h.

#define CHIP_ID_1251_PG12   (0x7030101)

Definition at line 60 of file reg.h.

#define CHIP_ID_B   (REGISTERS_BASE + 0x5674)

Definition at line 56 of file reg.h.

#define CHUNK_SIZE   512

Definition at line 494 of file reg.h.

#define CLK_BUF_TIME   (REGISTERS_BASE + 0x5818)

Definition at line 69 of file reg.h.

#define CLK_REQ_TIME   (REGISTERS_BASE + 0x5814)

Definition at line 68 of file reg.h.

#define DRPW_BASE   0x00310000

Definition at line 29 of file reg.h.

#define ECPU_CONTROL_HALT   0x00000101

Definition at line 499 of file reg.h.

#define ECPU_CTRL   (REGISTERS_BASE + 0x0804)

Definition at line 45 of file reg.h.

#define EE_ADDR   (REGISTERS_BASE + 0x2008)

Definition at line 389 of file reg.h.

#define EE_ADDR   (REGISTERS_BASE + 0x2008)

Definition at line 389 of file reg.h.

#define EE_CTL   (REGISTERS_BASE + 0x2000)

Definition at line 378 of file reg.h.

#define EE_CTL   (REGISTERS_BASE + 0x2000)

Definition at line 378 of file reg.h.

#define EE_CTL_READ   2

Definition at line 54 of file reg.h.

#define EE_DATA   (REGISTERS_BASE + 0x2004)

Definition at line 399 of file reg.h.

#define EE_DATA   (REGISTERS_BASE + 0x2004)

Definition at line 399 of file reg.h.

#define EE_READ   0x00000002ul

Definition at line 381 of file reg.h.

#define EE_START   (REGISTERS_BASE + 0x080C)

Definition at line 49 of file reg.h.

#define EE_WRITE   0x00000001ul

Definition at line 380 of file reg.h.

#define EEPROM_ACCESS_TO   10000 /* timeout counter */

Definition at line 402 of file reg.h.

#define ELP_CFG_MODE   (REGISTERS_BASE + 0x5804)

Definition at line 65 of file reg.h.

#define ELP_CMD   (REGISTERS_BASE + 0x5808)

Definition at line 66 of file reg.h.

#define ELPCTRL_SLEEP   0x0

Definition at line 39 of file reg.h.

#define ELPCTRL_WAKE_UP   0x1

Definition at line 37 of file reg.h.

#define ELPCTRL_WAKE_UP_WLAN_READY   0x5

Definition at line 38 of file reg.h.

#define ELPCTRL_WLAN_READY   0x2

Definition at line 41 of file reg.h.

#define ENABLE   (REGISTERS_BASE + 0x5450)

Definition at line 62 of file reg.h.

#define FW_HDR_SIZE   8

Definition at line 497 of file reg.h.

#define HI_CFG   (REGISTERS_BASE + 0x0808)

Definition at line 46 of file reg.h.

#define HI_CFG_CLOCK_REQ_SELECT   0x00000010

Definition at line 444 of file reg.h.

#define HI_CFG_DEF_VAL

Value:

(HI_CFG_UART_ENABLE |        \
    HI_CFG_RST232_ENABLE |      \
    HI_CFG_CLOCK_REQ_SELECT |   \
    HI_CFG_HOST_INT_ENABLE)

Definition at line 463 of file reg.h.

#define HI_CFG_HOST_INT_ACTIVE_LOW   0x00000080

Definition at line 447 of file reg.h.

#define HI_CFG_HOST_INT_ENABLE   0x00000020

Definition at line 445 of file reg.h.

#define HI_CFG_RST232_ENABLE   0x00000008

Definition at line 443 of file reg.h.

#define HI_CFG_UART_ENABLE   0x00000004

Definition at line 442 of file reg.h.

#define HI_CFG_UART_TX_OUT_GPIO_14   0x00000200

Definition at line 449 of file reg.h.

#define HI_CFG_UART_TX_OUT_GPIO_15   0x00000100

Definition at line 448 of file reg.h.

#define HI_CFG_UART_TX_OUT_GPIO_7   0x00000400

Definition at line 450 of file reg.h.

#define HI_CFG_VLYNQ_OUTPUT_ENABLE   0x00000040

Definition at line 446 of file reg.h.

#define HW_ACCESS_ELP_CTRL_REG_ADDR   0x1FFFC

Definition at line 34 of file reg.h.

#define INTR_TRIG_CMD   BIT(0)

Definition at line 610 of file reg.h.

#define INTR_TRIG_DEBUG_ACK   BIT(4)

Definition at line 634 of file reg.h.

#define INTR_TRIG_EVENT_ACK   BIT(1)

Definition at line 618 of file reg.h.

#define INTR_TRIG_RX_PROC0   BIT(3)

Definition at line 632 of file reg.h.

#define INTR_TRIG_RX_PROC1   BIT(17)

Definition at line 646 of file reg.h.

#define INTR_TRIG_STATE_CHANGED   BIT(5)

Definition at line 636 of file reg.h.

#define INTR_TRIG_TX_PROC0   BIT(2)

Definition at line 625 of file reg.h.

#define INTR_TRIG_TX_PROC1   BIT(18)

Definition at line 653 of file reg.h.

#define LUT_PARAM_ALPHA_BB   3

Definition at line 481 of file reg.h.

#define LUT_PARAM_ATTN_BB   2

Definition at line 480 of file reg.h.

#define LUT_PARAM_BB_PLL_LOOP_FILTER   5

Definition at line 483 of file reg.h.

#define LUT_PARAM_FRACTIONAL_DIVIDER   1

Definition at line 479 of file reg.h.

#define LUT_PARAM_INTEGER_DIVIDER   0

Definition at line 478 of file reg.h.

#define LUT_PARAM_NUM   6

Definition at line 484 of file reg.h.

#define LUT_PARAM_STOP_TIME_BB   4

Definition at line 482 of file reg.h.

#define NVS_DATA_BUNDARY_ALIGNMENT   4

Definition at line 490 of file reg.h.

#define OFDM_RATE_BIT   BIT(6)

Definition at line 563 of file reg.h.

#define PBCC_RATE_BIT   BIT(7)

Definition at line 564 of file reg.h.

#define PLL_CAL_TIME   (REGISTERS_BASE + 0x5810)

Definition at line 67 of file reg.h.

#define REF_FREQ_19_2   0

Definition at line 471 of file reg.h.

#define REF_FREQ_26_0   1

Definition at line 472 of file reg.h.

#define REF_FREQ_33_6   4

Definition at line 475 of file reg.h.

#define REF_FREQ_38_4   2

Definition at line 473 of file reg.h.

#define REF_FREQ_40_0   3

Definition at line 474 of file reg.h.

#define REF_FREQ_NUM   5

Definition at line 476 of file reg.h.

#define REG_COMMAND_MAILBOX_PTR   (SCR_PAD0)

Definition at line 271 of file reg.h.

#define REG_ENABLE_TX_RX   (ENABLE)

Definition at line 291 of file reg.h.

#define REG_EVENT_MAILBOX_PTR   (SCR_PAD1)

Definition at line 286 of file reg.h.

#define REG_RX_CONFIG   (RX_CFG)

Definition at line 296 of file reg.h.

#define REG_RX_FILTER   (RX_FILTER_CFG)

Definition at line 297 of file reg.h.

#define REGISTERS_BASE   0x00300000

Definition at line 28 of file reg.h.

#define REGISTERS_DOWN_SIZE   0x00008800

Definition at line 31 of file reg.h.

#define REGISTERS_WORK_SIZE   0x0000b000

Definition at line 32 of file reg.h.

#define RX_CFG_BSSID   0x0020

Definition at line 306 of file reg.h.

#define RX_CFG_COPY_RX_STATUS   0x2000

Definition at line 321 of file reg.h.

#define RX_CFG_DISABLE_BCAST   0x0200

Definition at line 317 of file reg.h.

#define RX_CFG_ENABLE_ANY_BSSID   0x0000

Definition at line 314 of file reg.h.

#define RX_CFG_ENABLE_ANY_DEST_MAC   0x0000

Definition at line 312 of file reg.h.

#define RX_CFG_ENABLE_ONLY_MY_BSSID   0x0020

Definition at line 313 of file reg.h.

#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC   0x0010

Definition at line 311 of file reg.h.

#define RX_CFG_ENABLE_ONLY_MY_SSID   0x0400

Definition at line 319 of file reg.h.

#define RX_CFG_ENABLE_PHY_HEADER_PLCP   0x0002

Definition at line 300 of file reg.h.

#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR   0x0800

Definition at line 320 of file reg.h.

#define RX_CFG_MAC   0x0010

Definition at line 309 of file reg.h.

#define RX_CFG_PROMISCUOUS   0x0008

Definition at line 303 of file reg.h.

#define RX_CFG_TSF   0x10000

Definition at line 322 of file reg.h.

#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS

Value:

(RX_CFG_ENABLE_ANY_DEST_MAC | \
                      RX_CFG_ENABLE_ANY_BSSID)

Definition at line 330 of file reg.h.

#define RX_CONFIG_OPTION_ANY_DST_MY_BSS

Value:

(RX_CFG_ENABLE_ANY_DEST_MAC | \
                      RX_CFG_ENABLE_ONLY_MY_BSSID)

Definition at line 324 of file reg.h.

#define RX_CONFIG_OPTION_FOR_IBSS_JOIN

Value:

(RX_CFG_ENABLE_ONLY_MY_SSID | \
                      RX_CFG_ENABLE_ONLY_MY_DEST_MAC)

Definition at line 345 of file reg.h.

#define RX_CONFIG_OPTION_FOR_JOIN

Value:

(RX_CFG_ENABLE_ONLY_MY_BSSID | \
                      RX_CFG_ENABLE_ONLY_MY_DEST_MAC)

Definition at line 342 of file reg.h.

#define RX_CONFIG_OPTION_FOR_MEASUREMENT   (RX_CFG_ENABLE_ANY_DEST_MAC)

Definition at line 340 of file reg.h.

#define RX_CONFIG_OPTION_FOR_SCAN

Value:

(RX_CFG_ENABLE_PHY_HEADER_PLCP \
                    | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
                    | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)

Definition at line 336 of file reg.h.

#define RX_CONFIG_OPTION_MY_DST_ANY_BSS

Value:

(RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
                      | RX_CFG_ENABLE_ANY_BSSID)

Definition at line 327 of file reg.h.

#define RX_CONFIG_OPTION_MY_DST_MY_BSS

Value:

(RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
                      | RX_CFG_ENABLE_ONLY_MY_BSSID)

Definition at line 333 of file reg.h.

#define RX_FILTER_OPTION_DEF

Value:

(CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
                       | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
                       | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)

Definition at line 348 of file reg.h.

#define RX_FILTER_OPTION_DEF_PRSP_BCN

Value:

(CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
                    | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)

Definition at line 354 of file reg.h.

#define RX_FILTER_OPTION_FILTER_ALL   0

Definition at line 352 of file reg.h.

#define RX_FILTER_OPTION_JOIN

Value:

(CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
                      | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
                      | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
                      | CFG_RX_PRSP_EN)

Definition at line 357 of file reg.h.

#define SCR_PAD0   (REGISTERS_BASE + 0x5608)

Definition at line 74 of file reg.h.

#define SCR_PAD1   (REGISTERS_BASE + 0x560C)

Definition at line 75 of file reg.h.

#define SCR_PAD2   (REGISTERS_BASE + 0x5610)

Definition at line 76 of file reg.h.

#define SCR_PAD3   (REGISTERS_BASE + 0x5614)

Definition at line 77 of file reg.h.

#define SCR_PAD4   (REGISTERS_BASE + 0x5618)

Definition at line 78 of file reg.h.

#define SCR_PAD4_CLR   (REGISTERS_BASE + 0x5620)

Definition at line 80 of file reg.h.

#define SCR_PAD4_SET   (REGISTERS_BASE + 0x561C)

Definition at line 79 of file reg.h.

#define SCR_PAD5   (REGISTERS_BASE + 0x5624)

Definition at line 81 of file reg.h.

#define SCR_PAD5_CLR   (REGISTERS_BASE + 0x562C)

Definition at line 83 of file reg.h.

#define SCR_PAD5_SET   (REGISTERS_BASE + 0x5628)

Definition at line 82 of file reg.h.

#define SCR_PAD6   (REGISTERS_BASE + 0x5630)

Definition at line 84 of file reg.h.

#define SCR_PAD7   (REGISTERS_BASE + 0x5634)

Definition at line 85 of file reg.h.

#define SCR_PAD8   (REGISTERS_BASE + 0x5638)

Definition at line 86 of file reg.h.

#define SCR_PAD9   (REGISTERS_BASE + 0x563C)

Definition at line 87 of file reg.h.

#define SHORT_PREAMBLE_BIT   BIT(0) /* CCK or Barker depending on the rate */

Definition at line 562 of file reg.h.

#define SOFT_RESET_MAX_TIME   1000000

Definition at line 488 of file reg.h.

#define SOFT_RESET_STALL_TIME   1000

Definition at line 489 of file reg.h.

#define SOR_CFG   (REGISTERS_BASE + 0x0800)

Definition at line 44 of file reg.h.

#define SPARE_A1   (REGISTERS_BASE + 0x0994)

Definition at line 90 of file reg.h.

#define SPARE_A2   (REGISTERS_BASE + 0x0998)

Definition at line 91 of file reg.h.

#define SPARE_A3   (REGISTERS_BASE + 0x099C)

Definition at line 92 of file reg.h.

#define SPARE_A4   (REGISTERS_BASE + 0x09A0)

Definition at line 93 of file reg.h.

#define SPARE_A5   (REGISTERS_BASE + 0x09A4)

Definition at line 94 of file reg.h.

#define SPARE_A6   (REGISTERS_BASE + 0x09A8)

Definition at line 95 of file reg.h.

#define SPARE_A7   (REGISTERS_BASE + 0x09AC)

Definition at line 96 of file reg.h.

#define SPARE_A8   (REGISTERS_BASE + 0x09B0)

Definition at line 97 of file reg.h.

#define SPARE_B1   (REGISTERS_BASE + 0x5420)

Definition at line 98 of file reg.h.

#define SPARE_B2   (REGISTERS_BASE + 0x5424)

Definition at line 99 of file reg.h.

#define SPARE_B3   (REGISTERS_BASE + 0x5428)

Definition at line 100 of file reg.h.

#define SPARE_B4   (REGISTERS_BASE + 0x542C)

Definition at line 101 of file reg.h.

#define SPARE_B5   (REGISTERS_BASE + 0x5430)

Definition at line 102 of file reg.h.

#define SPARE_B6   (REGISTERS_BASE + 0x5434)

Definition at line 103 of file reg.h.

#define SPARE_B7   (REGISTERS_BASE + 0x5438)

Definition at line 104 of file reg.h.

#define SPARE_B8   (REGISTERS_BASE + 0x543C)

Definition at line 105 of file reg.h.

#define START_EEPROM_MGR   0x00000001

Definition at line 403 of file reg.h.

#define USE_EEPROM   0

Definition at line 487 of file reg.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

RADIO_BAND_2_4GHZ
RADIO_BAND_5GHZ
RADIO_BAND_JAPAN_4_9_GHZ
DEFAULT_BAND
INVALID_BAND
MAX_RADIO_BANDS

Definition at line 509 of file reg.h.

anonymous enum

Enumerator:

NO_RATE
RATE_1MBPS
RATE_2MBPS
RATE_5_5MBPS
RATE_6MBPS
RATE_9MBPS
RATE_11MBPS
RATE_12MBPS
RATE_18MBPS
RATE_22MBPS
RATE_24MBPS
RATE_36MBPS
RATE_48MBPS
RATE_54MBPS

Definition at line 518 of file reg.h.

anonymous enum

Enumerator:

RATE_INDEX_1MBPS
RATE_INDEX_2MBPS
RATE_INDEX_5_5MBPS
RATE_INDEX_6MBPS
RATE_INDEX_9MBPS
RATE_INDEX_11MBPS
RATE_INDEX_12MBPS
RATE_INDEX_18MBPS
RATE_INDEX_22MBPS
RATE_INDEX_24MBPS
RATE_INDEX_36MBPS
RATE_INDEX_48MBPS
RATE_INDEX_54MBPS
RATE_INDEX_MAX
MAX_RATE_INDEX
INVALID_RATE_INDEX
RATE_INDEX_ENUM_MAX_SIZE

Definition at line 535 of file reg.h.

anonymous enum

Enumerator:

RATE_MASK_1MBPS
RATE_MASK_2MBPS
RATE_MASK_5_5MBPS
RATE_MASK_11MBPS

Definition at line 555 of file reg.h.

anonymous enum

Enumerator:

CCK_LONG
CCK_SHORT
PBCC_LONG
PBCC_SHORT
OFDM

Definition at line 566 of file reg.h.

enum wl12xx_acx_int_reg

Enumerator:

ACX_REG_INTERRUPT_TRIG
ACX_REG_INTERRUPT_TRIG_H
ACX_REG_INTERRUPT_MASK
ACX_REG_HINT_MASK_SET
ACX_REG_HINT_MASK_CLR
ACX_REG_INTERRUPT_NO_CLEAR
ACX_REG_INTERRUPT_CLEAR
ACX_REG_INTERRUPT_ACK
ACX_REG_SLV_SOFT_RESET
ACX_REG_EE_START
ACX_REG_ECPU_CONTROL
ACX_REG_TABLE_LEN

Definition at line 107 of file reg.h.