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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Enumerations | |
| enum | { COMPONENT_NO_SWITCH = 0x0, COMPONENT_2_WAY_SWITCH = 0x1, COMPONENT_3_WAY_SWITCH = 0x2, COMPONENT_MATCHING = 0x3 } |
| enum | { FEM_NONE = 0x0, FEM_VENDOR_1 = 0x1, FEM_VENDOR_2 = 0x2, FEM_VENDOR_3 = 0x3 } |
| enum | { BOARD_TYPE_EVB_18XX = 0, BOARD_TYPE_DVP_18XX = 1, BOARD_TYPE_HDK_18XX = 2, BOARD_TYPE_FPGA_18XX = 3, BOARD_TYPE_COM8_18XX = 4, NUM_BOARD_TYPES } |
| #define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4) |
| #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C) |
| #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000) |
| #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000) |
| #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000) |
| #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000) |
| #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00) |
| #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400) |
| #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800) |
| #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000) |
| #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C) |
| #define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0) |
| #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000) |
| #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004) |
| #define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1) |
| #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0) |
| #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC) |
| #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8) |
| #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074) |
| #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078) |
| #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC) |
| #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0) |
| #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4) |
| #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8) |
| #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC) |
| #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500) |
| #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504) |
| #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508) |
| #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C) |
| #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510) |
| #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514) |
| #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518) |
| #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C) |
| #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520) |
| #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE) |
| #define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018) |
| #define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008) |
| #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194) |
| #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198) |
| #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C) |
| #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0) |
| #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4) |
| #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8) |
| #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC) |
| #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0) |
| #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524) |
| #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528) |
| #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C) |
| #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530) |
| #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534) |
| #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538) |
| #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C) |
| #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540) |
| #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000) |
| #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000) |
| #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100) |
| #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000) |
| #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000) |
| anonymous enum |
| anonymous enum |
1.8.2