30 #define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0
32 #define HW_PARTITION_REGISTERS_ADDR 0x1FFC0
33 #define HW_PART0_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR)
34 #define HW_PART0_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 4)
35 #define HW_PART1_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 8)
36 #define HW_PART1_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 12)
37 #define HW_PART2_SIZE_ADDR (HW_PARTITION_REGISTERS_ADDR + 16)
38 #define HW_PART2_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 20)
39 #define HW_PART3_START_ADDR (HW_PARTITION_REGISTERS_ADDR + 24)
41 #define HW_ACCESS_REGISTER_SIZE 4
43 #define HW_ACCESS_PRAM_MAX_RANGE 0x3c000
58 void *
buf,
size_t len,
66 ret = wl->
if_ops->write(wl->
dev, addr, buf, len, fixed);
74 void *buf,
size_t len,
82 ret = wl->
if_ops->read(wl->
dev, addr, buf, len, fixed);
90 void *buf,
size_t len,
93 return wlcore_raw_read(wl, wl->
rtable[reg], buf, len, fixed);
97 void *buf,
size_t len,
100 return wlcore_raw_write(wl, wl->
rtable[reg], buf, len, fixed);
108 ret = wlcore_raw_read(wl, addr, &wl->
buffer_32,
123 return wlcore_raw_write(wl, addr, &wl->
buffer_32,
128 void *buf,
size_t len,
bool fixed)
134 return wlcore_raw_read(wl, physical, buf, len, fixed);
138 void *buf,
size_t len,
bool fixed)
144 return wlcore_raw_write(wl, physical, buf, len, fixed);
148 void *buf,
size_t len,
151 return wlcore_write(wl, wl->
rtable[reg], buf, len, fixed);
155 void *buf,
size_t len,
158 return wlcore_read(wl, wl->
rtable[reg], buf, len, fixed);
162 void *buf,
size_t len,
173 return wlcore_raw_read(wl, physical, buf, len, fixed);
191 return wlcore_raw_read32(wl,
199 return wlcore_raw_write32(wl,
204 static inline void wl1271_power_off(
struct wl1271 *wl)
216 static inline int wl1271_power_on(
struct wl1271 *wl)
218 int ret = wl->
if_ops->power(wl->
dev,
true);