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drivers
staging
tidspbridge
include
dspbridge
clk.h
Go to the documentation of this file.
1
/*
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* clk.h
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Provides Clock functions.
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef _CLK_H
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#define _CLK_H
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enum
dsp_clk_id
{
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DSP_CLK_IVA2
= 0,
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DSP_CLK_GPT5
,
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DSP_CLK_GPT6
,
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DSP_CLK_GPT7
,
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DSP_CLK_GPT8
,
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DSP_CLK_WDT3
,
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DSP_CLK_MCBSP1
,
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DSP_CLK_MCBSP2
,
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DSP_CLK_MCBSP3
,
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DSP_CLK_MCBSP4
,
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DSP_CLK_MCBSP5
,
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DSP_CLK_SSI
,
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DSP_CLK_NOT_DEFINED
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};
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/*
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* ======== dsp_clk_exit ========
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* Purpose:
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* Discontinue usage of module; free resources when reference count
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* reaches 0.
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* Parameters:
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* Returns:
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* Requires:
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* CLK initialized.
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* Ensures:
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* Resources used by module are freed when cRef reaches zero.
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*/
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extern
void
dsp_clk_exit
(
void
);
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/*
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* ======== dsp_clk_init ========
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* Purpose:
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* Initializes private state of CLK module.
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* Parameters:
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* Returns:
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* TRUE if initialized; FALSE if error occurred.
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* Requires:
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* Ensures:
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* CLK initialized.
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*/
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extern
void
dsp_clk_init
(
void
);
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void
dsp_gpt_wait_overflow
(
short
int
clk_id,
unsigned
int
load
);
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/*
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* ======== dsp_clk_enable ========
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* Purpose:
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* Enables the clock requested.
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* Parameters:
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* Returns:
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* 0: Success.
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* -EPERM: Error occurred while enabling the clock.
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* Requires:
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* Ensures:
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*/
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extern
int
dsp_clk_enable
(
enum
dsp_clk_id
clk_id);
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u32
dsp_clock_enable_all
(
u32
dsp_per_clocks);
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/*
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* ======== dsp_clk_disable ========
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* Purpose:
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* Disables the clock requested.
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* Parameters:
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* Returns:
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* 0: Success.
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* -EPERM: Error occurred while disabling the clock.
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* Requires:
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* Ensures:
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*/
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extern
int
dsp_clk_disable
(
enum
dsp_clk_id
clk_id);
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extern
u32
dsp_clk_get_iva2_rate
(
void
);
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u32
dsp_clock_disable_all
(
u32
dsp_per_clocks);
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extern
void
ssi_clk_prepare
(
bool
FLAG
);
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#endif
/* _SYNC_H */
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