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| #define | FLAG 0x7e |
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| #define | R0 0 /* Register selects */ |
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| #define | R1 1 |
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| #define | R2 2 |
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| #define | R3 3 |
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| #define | R4 4 |
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| #define | R5 5 |
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| #define | R6 6 |
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| #define | R7 7 |
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| #define | R8 8 |
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| #define | R9 9 |
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| #define | R10 10 |
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| #define | R11 11 |
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| #define | R12 12 |
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| #define | R13 13 |
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| #define | R14 14 |
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| #define | R15 15 |
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| #define | NULLCODE 0 /* Null Code */ |
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| #define | POINT_HIGH 0x8 /* Select upper half of registers */ |
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| #define | RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ |
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| #define | SEND_ABORT 0x18 /* HDLC Abort */ |
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| #define | RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ |
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| #define | RES_Tx_P 0x28 /* Reset TxINT Pending */ |
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| #define | ERR_RES 0x30 /* Error Reset */ |
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| #define | RES_H_IUS 0x38 /* Reset highest IUS */ |
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| #define | RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ |
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| #define | RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ |
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| #define | RES_EOM_L 0xC0 /* Reset EOM latch */ |
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| #define | EXT_INT_ENAB 0x1 /* Ext Int Enable */ |
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| #define | TxINT_ENAB 0x2 /* Tx Int Enable */ |
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| #define | PAR_SPEC 0x4 /* Parity is special condition */ |
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| #define | RxINT_DISAB 0 /* Rx Int Disable */ |
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| #define | RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ |
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| #define | INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ |
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| #define | INT_ERR_Rx 0x18 /* Int on error only */ |
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| #define | WT_RDY_RT 0x20 /* Wait/Ready on R/T */ |
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| #define | WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */ |
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| #define | WT_RDY_ENAB 0x80 /* Wait/Ready Enable */ |
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| #define | RxENABLE 0x1 /* Rx Enable */ |
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| #define | SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ |
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| #define | ADD_SM 0x4 /* Address Search Mode (SDLC) */ |
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| #define | RxCRC_ENAB 0x8 /* Rx CRC Enable */ |
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| #define | ENT_HM 0x10 /* Enter Hunt Mode */ |
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| #define | AUTO_ENAB 0x20 /* Auto Enables */ |
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| #define | Rx5 0x0 /* Rx 5 Bits/Character */ |
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| #define | Rx7 0x40 /* Rx 7 Bits/Character */ |
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| #define | Rx6 0x80 /* Rx 6 Bits/Character */ |
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| #define | Rx8 0xc0 /* Rx 8 Bits/Character */ |
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| #define | PAR_ENA 0x1 /* Parity Enable */ |
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| #define | PAR_EVEN 0x2 /* Parity Even/Odd* */ |
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| #define | SYNC_ENAB 0 /* Sync Modes Enable */ |
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| #define | SB1 0x4 /* 1 stop bit/char */ |
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| #define | SB15 0x8 /* 1.5 stop bits/char */ |
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| #define | SB2 0xc /* 2 stop bits/char */ |
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| #define | MONSYNC 0 /* 8 Bit Sync character */ |
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| #define | BISYNC 0x10 /* 16 bit sync character */ |
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| #define | SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ |
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| #define | EXTSYNC 0x30 /* External Sync Mode */ |
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| #define | X1CLK 0x0 /* x1 clock mode */ |
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| #define | X16CLK 0x40 /* x16 clock mode */ |
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| #define | X32CLK 0x80 /* x32 clock mode */ |
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| #define | X64CLK 0xC0 /* x64 clock mode */ |
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| #define | TxCRC_ENAB 0x1 /* Tx CRC Enable */ |
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| #define | RTS 0x2 /* RTS */ |
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| #define | SDLC_CRC 0x4 /* SDLC/CRC-16 */ |
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| #define | TxENAB 0x8 /* Tx Enable */ |
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| #define | SND_BRK 0x10 /* Send Break */ |
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| #define | Tx5 0x0 /* Tx 5 bits (or less)/character */ |
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| #define | Tx7 0x20 /* Tx 7 bits/character */ |
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| #define | Tx6 0x40 /* Tx 6 bits/character */ |
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| #define | Tx8 0x60 /* Tx 8 bits/character */ |
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| #define | DTR 0x80 /* DTR */ |
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| #define | VIS 1 /* Vector Includes Status */ |
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| #define | NV 2 /* No Vector */ |
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| #define | DLC 4 /* Disable Lower Chain */ |
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| #define | MIE 8 /* Master Interrupt Enable */ |
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| #define | STATHI 0x10 /* Status high */ |
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| #define | NORESET 0 /* No reset on write to R9 */ |
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| #define | CHRB 0x40 /* Reset channel B */ |
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| #define | CHRA 0x80 /* Reset channel A */ |
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| #define | FHWRES 0xc0 /* Force hardware reset */ |
| |
| #define | BIT6 1 /* 6 bit/8bit sync */ |
| |
| #define | LOOPMODE 2 /* SDLC Loop mode */ |
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| #define | ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ |
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| #define | MARKIDLE 8 /* Mark/flag on idle */ |
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| #define | GAOP 0x10 /* Go active on poll */ |
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| #define | NRZ 0 /* NRZ mode */ |
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| #define | NRZI 0x20 /* NRZI mode */ |
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| #define | FM1 0x40 /* FM1 (transition = 1) */ |
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| #define | FM0 0x60 /* FM0 (transition = 0) */ |
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| #define | CRCPS 0x80 /* CRC Preset I/O */ |
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| #define | TRxCXT 0 /* TRxC = Xtal output */ |
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| #define | TRxCTC 1 /* TRxC = Transmit clock */ |
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| #define | TRxCBR 2 /* TRxC = BR Generator Output */ |
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| #define | TRxCDP 3 /* TRxC = DPLL output */ |
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| #define | TRxCOI 4 /* TRxC O/I */ |
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| #define | TCRTxCP 0 /* Transmit clock = RTxC pin */ |
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| #define | TCTRxCP 8 /* Transmit clock = TRxC pin */ |
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| #define | TCBR 0x10 /* Transmit clock = BR Generator output */ |
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| #define | TCDPLL 0x18 /* Transmit clock = DPLL output */ |
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| #define | RCRTxCP 0 /* Receive clock = RTxC pin */ |
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| #define | RCTRxCP 0x20 /* Receive clock = TRxC pin */ |
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| #define | RCBR 0x40 /* Receive clock = BR Generator output */ |
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| #define | RCDPLL 0x60 /* Receive clock = DPLL output */ |
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| #define | RTxCX 0x80 /* RTxC Xtal/No Xtal */ |
| |
| #define | BRENABL 1 /* Baud rate generator enable */ |
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| #define | BRSRC 2 /* Baud rate generator source */ |
| |
| #define | DTRREQ 4 /* DTR/Request function */ |
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| #define | AUTOECHO 8 /* Auto Echo */ |
| |
| #define | LOOPBAK 0x10 /* Local loopback */ |
| |
| #define | SEARCH 0x20 /* Enter search mode */ |
| |
| #define | RMC 0x40 /* Reset missing clock */ |
| |
| #define | DISDPLL 0x60 /* Disable DPLL */ |
| |
| #define | SSBR 0x80 /* Set DPLL source = BR generator */ |
| |
| #define | SSRTxC 0xa0 /* Set DPLL source = RTxC */ |
| |
| #define | SFMM 0xc0 /* Set FM mode */ |
| |
| #define | SNRZI 0xe0 /* Set NRZI mode */ |
| |
| #define | ZCIE 2 /* Zero count IE */ |
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| #define | DCDIE 8 /* DCD IE */ |
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| #define | SYNCIE 0x10 /* Sync/hunt IE */ |
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| #define | CTSIE 0x20 /* CTS IE */ |
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| #define | TxUIE 0x40 /* Tx Underrun/EOM IE */ |
| |
| #define | BRKIE 0x80 /* Break/Abort IE */ |
| |
| #define | Rx_CH_AV 0x1 /* Rx Character Available */ |
| |
| #define | ZCOUNT 0x2 /* Zero count */ |
| |
| #define | Tx_BUF_EMP 0x4 /* Tx Buffer empty */ |
| |
| #define | DCD 0x8 /* DCD */ |
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| #define | SYNC_HUNT 0x10 /* Sync/hunt */ |
| |
| #define | CTS 0x20 /* CTS */ |
| |
| #define | TxEOM 0x40 /* Tx underrun */ |
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| #define | BRK_ABRT 0x80 /* Break/Abort */ |
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| #define | ALL_SNT 0x1 /* All sent */ |
| |
| #define | RES3 0x8 /* 0/3 */ |
| |
| #define | RES4 0x4 /* 0/4 */ |
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| #define | RES5 0xc /* 0/5 */ |
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| #define | RES6 0x2 /* 0/6 */ |
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| #define | RES7 0xa /* 0/7 */ |
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| #define | RES8 0x6 /* 0/8 */ |
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| #define | RES18 0xe /* 1/8 */ |
| |
| #define | RES28 0x0 /* 2/8 */ |
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| #define | PAR_ERR 0x10 /* Parity error */ |
| |
| #define | Rx_OVR 0x20 /* Rx Overrun Error */ |
| |
| #define | CRC_ERR 0x40 /* CRC/Framing Error */ |
| |
| #define | END_FR 0x80 /* End of Frame (SDLC) */ |
| |
| #define | CHBEXT 0x1 /* Channel B Ext/Stat IP */ |
| |
| #define | CHBTxIP 0x2 /* Channel B Tx IP */ |
| |
| #define | CHBRxIP 0x4 /* Channel B Rx IP */ |
| |
| #define | CHAEXT 0x8 /* Channel A Ext/Stat IP */ |
| |
| #define | CHATxIP 0x10 /* Channel A Tx IP */ |
| |
| #define | CHARxIP 0x20 /* Channel A Rx IP */ |
| |
| #define | ONLOOP 2 /* On loop */ |
| |
| #define | LOOPSEND 0x10 /* Loop sending */ |
| |
| #define | CLK2MIS 0x40 /* Two clocks missing */ |
| |
| #define | CLK1MIS 0x80 /* One clock missing */ |
| |
| #define | AUTOTXF 0x01 /* Auto Tx Flag */ |
| |
| #define | AUTOEOM 0x02 /* Auto EOM Latch Reset */ |
| |
| #define | AUTORTS 0x04 /* Auto RTS */ |
| |
| #define | TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */ |
| |
| #define | RXFIFOH 0x08 /* Z85230: Int on RX FIFO half full */ |
| |
| #define | FASTDTR 0x10 /* Fast DTR/REQ Mode */ |
| |
| #define | CRCCBCR 0x20 /* CRC Check Bytes Completely Received */ |
| |
| #define | TXFIFOE 0x20 /* Z85230: Int on TX FIFO completely empty */ |
| |
| #define | EXTRDEN 0x40 /* Extended Read Enabled */ |
| |
| #define | SHDLCE 1 /* SDLC/HDLC Enhancements Enable */ |
| |
| #define | FIFOE 4 /* FIFO Enable */ |
| |
| #define | BCLSB 0xff /* LSB of 14 bits count */ |
| |
| #define | BCMSB 0x3f /* MSB of 14 bits count */ |
| |
| #define | FDA 0x40 /* FIFO Data Available Status */ |
| |
| #define | FOS 0x80 /* FIFO Overflow Status */ |
| |
1.8.2