Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Macros
drxk_map.h File Reference

Go to the source code of this file.

Macros

#define AUD_COMM_EXEC__A   0x1000000
 
#define AUD_COMM_EXEC_STOP   0x0
 
#define FEC_COMM_EXEC__A   0x1C00000
 
#define FEC_COMM_EXEC_STOP   0x0
 
#define FEC_COMM_EXEC_ACTIVE   0x1
 
#define FEC_DI_COMM_EXEC__A   0x1C20000
 
#define FEC_DI_COMM_EXEC_STOP   0x0
 
#define FEC_DI_INPUT_CTL__A   0x1C20016
 
#define FEC_RS_COMM_EXEC__A   0x1C30000
 
#define FEC_RS_COMM_EXEC_STOP   0x0
 
#define FEC_RS_MEASUREMENT_PERIOD__A   0x1C30012
 
#define FEC_RS_MEASUREMENT_PRESCALE__A   0x1C30013
 
#define FEC_OC_MODE__A   0x1C40011
 
#define FEC_OC_MODE_PARITY__M   0x1
 
#define FEC_OC_DTO_MODE__A   0x1C40014
 
#define FEC_OC_DTO_MODE_DYNAMIC__M   0x1
 
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M   0x4
 
#define FEC_OC_DTO_PERIOD__A   0x1C40015
 
#define FEC_OC_DTO_BURST_LEN__A   0x1C40018
 
#define FEC_OC_FCT_MODE__A   0x1C4001A
 
#define FEC_OC_FCT_MODE__PRE   0x0
 
#define FEC_OC_FCT_MODE_RAT_ENA__M   0x1
 
#define FEC_OC_FCT_MODE_VIRT_ENA__M   0x2
 
#define FEC_OC_TMD_MODE__A   0x1C4001E
 
#define FEC_OC_TMD_COUNT__A   0x1C4001F
 
#define FEC_OC_TMD_HI_MARGIN__A   0x1C40020
 
#define FEC_OC_TMD_LO_MARGIN__A   0x1C40021
 
#define FEC_OC_TMD_INT_UPD_RATE__A   0x1C40023
 
#define FEC_OC_AVR_PARM_A__A   0x1C40026
 
#define FEC_OC_AVR_PARM_B__A   0x1C40027
 
#define FEC_OC_RCN_GAIN__A   0x1C4002E
 
#define FEC_OC_RCN_CTL_RATE_LO__A   0x1C40030
 
#define FEC_OC_RCN_CTL_STEP_LO__A   0x1C40032
 
#define FEC_OC_RCN_CTL_STEP_HI__A   0x1C40033
 
#define FEC_OC_SNC_MODE__A   0x1C40040
 
#define FEC_OC_SNC_MODE_SHUTDOWN__M   0x10
 
#define FEC_OC_SNC_LWM__A   0x1C40041
 
#define FEC_OC_SNC_HWM__A   0x1C40042
 
#define FEC_OC_SNC_UNLOCK__A   0x1C40043
 
#define FEC_OC_SNC_FAIL_PERIOD__A   0x1C40046
 
#define FEC_OC_IPR_MODE__A   0x1C40048
 
#define FEC_OC_IPR_MODE_SERIAL__M   0x1
 
#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M   0x4
 
#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M   0x10
 
#define FEC_OC_IPR_INVERT__A   0x1C40049
 
#define FEC_OC_IPR_INVERT_MD0__M   0x1
 
#define FEC_OC_IPR_INVERT_MD1__M   0x2
 
#define FEC_OC_IPR_INVERT_MD2__M   0x4
 
#define FEC_OC_IPR_INVERT_MD3__M   0x8
 
#define FEC_OC_IPR_INVERT_MD4__M   0x10
 
#define FEC_OC_IPR_INVERT_MD5__M   0x20
 
#define FEC_OC_IPR_INVERT_MD6__M   0x40
 
#define FEC_OC_IPR_INVERT_MD7__M   0x80
 
#define FEC_OC_IPR_INVERT_MERR__M   0x100
 
#define FEC_OC_IPR_INVERT_MSTRT__M   0x200
 
#define FEC_OC_IPR_INVERT_MVAL__M   0x400
 
#define FEC_OC_IPR_INVERT_MCLK__M   0x800
 
#define FEC_OC_OCR_INVERT__A   0x1C40052
 
#define IQM_COMM_EXEC__A   0x1800000
 
#define IQM_COMM_EXEC_B_STOP   0x0
 
#define IQM_COMM_EXEC_B_ACTIVE   0x1
 
#define IQM_FS_RATE_OFS_LO__A   0x1820010
 
#define IQM_FS_ADJ_SEL__A   0x1820014
 
#define IQM_FS_ADJ_SEL_B_OFF   0x0
 
#define IQM_FS_ADJ_SEL_B_QAM   0x1
 
#define IQM_FS_ADJ_SEL_B_VSB   0x2
 
#define IQM_FD_RATESEL__A   0x1830010
 
#define IQM_RC_RATE_OFS_LO__A   0x1840010
 
#define IQM_RC_RATE_OFS_LO__W   16
 
#define IQM_RC_RATE_OFS_LO__M   0xFFFF
 
#define IQM_RC_RATE_OFS_HI__M   0xFF
 
#define IQM_RC_ADJ_SEL__A   0x1840014
 
#define IQM_RC_ADJ_SEL_B_OFF   0x0
 
#define IQM_RC_ADJ_SEL_B_QAM   0x1
 
#define IQM_RC_ADJ_SEL_B_VSB   0x2
 
#define IQM_RC_STRETCH__A   0x1840016
 
#define IQM_CF_COMM_INT_MSK__A   0x1860006
 
#define IQM_CF_SYMMETRIC__A   0x1860010
 
#define IQM_CF_MIDTAP__A   0x1860011
 
#define IQM_CF_MIDTAP_RE__B   0
 
#define IQM_CF_MIDTAP_IM__B   1
 
#define IQM_CF_OUT_ENA__A   0x1860012
 
#define IQM_CF_OUT_ENA_QAM__B   1
 
#define IQM_CF_OUT_ENA_OFDM__M   0x4
 
#define IQM_CF_ADJ_SEL__A   0x1860013
 
#define IQM_CF_SCALE__A   0x1860014
 
#define IQM_CF_SCALE_SH__A   0x1860015
 
#define IQM_CF_SCALE_SH__PRE   0x0
 
#define IQM_CF_POW_MEAS_LEN__A   0x1860017
 
#define IQM_CF_DS_ENA__A   0x1860019
 
#define IQM_CF_TAP_RE0__A   0x1860020
 
#define IQM_CF_TAP_IM0__A   0x1860040
 
#define IQM_CF_CLP_VAL__A   0x1860060
 
#define IQM_CF_DATATH__A   0x1860061
 
#define IQM_CF_PKDTH__A   0x1860062
 
#define IQM_CF_WND_LEN__A   0x1860063
 
#define IQM_CF_DET_LCT__A   0x1860064
 
#define IQM_CF_BYPASSDET__A   0x1860067
 
#define IQM_AF_COMM_EXEC__A   0x1870000
 
#define IQM_AF_COMM_EXEC_ACTIVE   0x1
 
#define IQM_AF_CLKNEG__A   0x1870012
 
#define IQM_AF_CLKNEG_CLKNEGDATA__M   0x2
 
#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS   0x0
 
#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG   0x2
 
#define IQM_AF_START_LOCK__A   0x187001B
 
#define IQM_AF_PHASE0__A   0x187001C
 
#define IQM_AF_PHASE1__A   0x187001D
 
#define IQM_AF_PHASE2__A   0x187001E
 
#define IQM_AF_CLP_LEN__A   0x1870023
 
#define IQM_AF_CLP_TH__A   0x1870024
 
#define IQM_AF_SNS_LEN__A   0x1870026
 
#define IQM_AF_AGC_IF__A   0x1870028
 
#define IQM_AF_AGC_RF__A   0x1870029
 
#define IQM_AF_PDREF__A   0x187002B
 
#define IQM_AF_PDREF__M   0x1F
 
#define IQM_AF_STDBY__A   0x187002C
 
#define IQM_AF_STDBY_STDBY_ADC_STANDBY   0x2
 
#define IQM_AF_STDBY_STDBY_AMP_STANDBY   0x4
 
#define IQM_AF_STDBY_STDBY_PD_STANDBY   0x8
 
#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY   0x10
 
#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY   0x20
 
#define IQM_AF_AMUX__A   0x187002D
 
#define IQM_AF_AMUX_SIGNAL2ADC   0x1
 
#define IQM_AF_UPD_SEL__A   0x187002F
 
#define IQM_AF_INC_LCT__A   0x1870034
 
#define IQM_AF_INC_BYPASS__A   0x1870036
 
#define OFDM_CP_COMM_EXEC__A   0x2800000
 
#define OFDM_CP_COMM_EXEC_STOP   0x0
 
#define OFDM_EC_SB_PRIOR__A   0x3410013
 
#define OFDM_EC_SB_PRIOR_HI   0x0
 
#define OFDM_EC_SB_PRIOR_LO   0x1
 
#define OFDM_EQ_TOP_TD_TPS_CONST__A   0x3010054
 
#define OFDM_EQ_TOP_TD_TPS_CONST__M   0x3
 
#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM   0x2
 
#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A   0x3010056
 
#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M   0x7
 
#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8   0x4
 
#define OFDM_EQ_TOP_TD_SQR_ERR_I__A   0x301005E
 
#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A   0x301005F
 
#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A   0x3010060
 
#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A   0x3010061
 
#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A   0x3010062
 
#define OFDM_LC_COMM_EXEC__A   0x3800000
 
#define OFDM_LC_COMM_EXEC_STOP   0x0
 
#define OFDM_SC_COMM_EXEC__A   0x3C00000
 
#define OFDM_SC_COMM_EXEC_STOP   0x0
 
#define OFDM_SC_COMM_STATE__A   0x3C00001
 
#define OFDM_SC_RA_RAM_PARAM0__A   0x3C20040
 
#define OFDM_SC_RA_RAM_PARAM1__A   0x3C20041
 
#define OFDM_SC_RA_RAM_CMD_ADDR__A   0x3C20042
 
#define OFDM_SC_RA_RAM_CMD__A   0x3C20043
 
#define OFDM_SC_RA_RAM_CMD_NULL   0x0
 
#define OFDM_SC_RA_RAM_CMD_PROC_START   0x1
 
#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM   0x3
 
#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM   0x4
 
#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM   0x5
 
#define OFDM_SC_RA_RAM_CMD_USER_IO   0x6
 
#define OFDM_SC_RA_RAM_CMD_SET_TIMER   0x7
 
#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING   0x8
 
#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M   0x1
 
#define OFDM_SC_RA_RAM_LOCKTRACK_MIN   0x1
 
#define OFDM_SC_RA_RAM_OP_PARAM__A   0x3C20048
 
#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M   0x3
 
#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K   0x0
 
#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K   0x1
 
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32   0x0
 
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16   0x4
 
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8   0x8
 
#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4   0xC
 
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK   0x0
 
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16   0x10
 
#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64   0x20
 
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO   0x0
 
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1   0x40
 
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2   0x80
 
#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4   0xC0
 
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2   0x0
 
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3   0x200
 
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4   0x400
 
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6   0x600
 
#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8   0x800
 
#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI   0x0
 
#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO   0x1000
 
#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M   0x1
 
#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M   0x2
 
#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M   0x4
 
#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M   0x8
 
#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M   0x10
 
#define OFDM_SC_RA_RAM_LOCK__A   0x3C2004B
 
#define OFDM_SC_RA_RAM_LOCK_DEMOD__M   0x1
 
#define OFDM_SC_RA_RAM_LOCK_FEC__M   0x2
 
#define OFDM_SC_RA_RAM_LOCK_MPEG__M   0x4
 
#define OFDM_SC_RA_RAM_LOCK_NODVBT__M   0x8
 
#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A   0x3C2004D
 
#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A   0x3C2004E
 
#define OFDM_SC_RA_RAM_ECHO_THRES__A   0x3C2004F
 
#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B   0
 
#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M   0xFF
 
#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B   8
 
#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M   0xFF00
 
#define OFDM_SC_RA_RAM_CONFIG__A   0x3C20050
 
#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M   0x800
 
#define OFDM_SC_RA_RAM_FR_THRES_8K__A   0x3C2007D
 
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A   0x3C200E0
 
#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A   0x3C200E1
 
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A   0x3C200E3
 
#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A   0x3C200E4
 
#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A   0x3C200F8
 
#define QAM_COMM_EXEC__A   0x1400000
 
#define QAM_COMM_EXEC_STOP   0x0
 
#define QAM_COMM_EXEC_ACTIVE   0x1
 
#define QAM_TOP_ANNEX_A   0x0
 
#define QAM_TOP_ANNEX_C   0x2
 
#define QAM_SL_ERR_POWER__A   0x1430017
 
#define QAM_DQ_QUAL_FUN0__A   0x1440018
 
#define QAM_DQ_QUAL_FUN1__A   0x1440019
 
#define QAM_DQ_QUAL_FUN2__A   0x144001A
 
#define QAM_DQ_QUAL_FUN3__A   0x144001B
 
#define QAM_DQ_QUAL_FUN4__A   0x144001C
 
#define QAM_DQ_QUAL_FUN5__A   0x144001D
 
#define QAM_LC_MODE__A   0x1450010
 
#define QAM_LC_QUAL_TAB0__A   0x1450018
 
#define QAM_LC_QUAL_TAB1__A   0x1450019
 
#define QAM_LC_QUAL_TAB2__A   0x145001A
 
#define QAM_LC_QUAL_TAB3__A   0x145001B
 
#define QAM_LC_QUAL_TAB4__A   0x145001C
 
#define QAM_LC_QUAL_TAB5__A   0x145001D
 
#define QAM_LC_QUAL_TAB6__A   0x145001E
 
#define QAM_LC_QUAL_TAB8__A   0x145001F
 
#define QAM_LC_QUAL_TAB9__A   0x1450020
 
#define QAM_LC_QUAL_TAB10__A   0x1450021
 
#define QAM_LC_QUAL_TAB12__A   0x1450022
 
#define QAM_LC_QUAL_TAB15__A   0x1450023
 
#define QAM_LC_QUAL_TAB16__A   0x1450024
 
#define QAM_LC_QUAL_TAB20__A   0x1450025
 
#define QAM_LC_QUAL_TAB25__A   0x1450026
 
#define QAM_LC_LPF_FACTORP__A   0x1450028
 
#define QAM_LC_LPF_FACTORI__A   0x1450029
 
#define QAM_LC_RATE_LIMIT__A   0x145002A
 
#define QAM_LC_SYMBOL_FREQ__A   0x145002B
 
#define QAM_SY_TIMEOUT__A   0x1470011
 
#define QAM_SY_TIMEOUT__PRE   0x3A98
 
#define QAM_SY_SYNC_LWM__A   0x1470012
 
#define QAM_SY_SYNC_AWM__A   0x1470013
 
#define QAM_SY_SYNC_HWM__A   0x1470014
 
#define QAM_SY_SP_INV__A   0x1470017
 
#define QAM_SY_SP_INV_SPECTRUM_INV_DIS   0x0
 
#define SCU_COMM_EXEC__A   0x800000
 
#define SCU_COMM_EXEC_STOP   0x0
 
#define SCU_COMM_EXEC_ACTIVE   0x1
 
#define SCU_COMM_EXEC_HOLD   0x2
 
#define SCU_RAM_DRIVER_DEBUG__A   0x831EBF
 
#define SCU_RAM_QAM_FSM_STEP_PERIOD__A   0x831EC4
 
#define SCU_RAM_GPIO__A   0x831EC7
 
#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE   0x0
 
#define SCU_RAM_AGC_CLP_CTRL_MODE__A   0x831EC8
 
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A   0x831ECB
 
#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A   0x831F05
 
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A   0x831F15
 
#define SCU_RAM_AGC_KI_CYCLEN__A   0x831F17
 
#define SCU_RAM_AGC_SNS_CYCLEN__A   0x831F18
 
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A   0x831F19
 
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A   0x831F1A
 
#define SCU_RAM_AGC_RF_MAX__A   0x831F1B
 
#define SCU_RAM_AGC_CONFIG__A   0x831F24
 
#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M   0x1
 
#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M   0x2
 
#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M   0x100
 
#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M   0x200
 
#define SCU_RAM_AGC_KI__A   0x831F25
 
#define SCU_RAM_AGC_KI_RF__B   4
 
#define SCU_RAM_AGC_KI_RF__M   0xF0
 
#define SCU_RAM_AGC_KI_IF__B   8
 
#define SCU_RAM_AGC_KI_IF__M   0xF00
 
#define SCU_RAM_AGC_KI_RED__A   0x831F26
 
#define SCU_RAM_AGC_KI_RED_RAGC_RED__B   2
 
#define SCU_RAM_AGC_KI_RED_RAGC_RED__M   0xC
 
#define SCU_RAM_AGC_KI_RED_IAGC_RED__B   4
 
#define SCU_RAM_AGC_KI_RED_IAGC_RED__M   0x30
 
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A   0x831F27
 
#define SCU_RAM_AGC_KI_MINGAIN__A   0x831F28
 
#define SCU_RAM_AGC_KI_MAXGAIN__A   0x831F29
 
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A   0x831F2A
 
#define SCU_RAM_AGC_KI_MIN__A   0x831F2B
 
#define SCU_RAM_AGC_KI_MAX__A   0x831F2C
 
#define SCU_RAM_AGC_CLP_SUM__A   0x831F2D
 
#define SCU_RAM_AGC_CLP_SUM_MIN__A   0x831F2E
 
#define SCU_RAM_AGC_CLP_SUM_MAX__A   0x831F2F
 
#define SCU_RAM_AGC_CLP_CYCLEN__A   0x831F30
 
#define SCU_RAM_AGC_CLP_CYCCNT__A   0x831F31
 
#define SCU_RAM_AGC_CLP_DIR_TO__A   0x831F32
 
#define SCU_RAM_AGC_CLP_DIR_WD__A   0x831F33
 
#define SCU_RAM_AGC_CLP_DIR_STP__A   0x831F34
 
#define SCU_RAM_AGC_SNS_SUM__A   0x831F35
 
#define SCU_RAM_AGC_SNS_SUM_MIN__A   0x831F36
 
#define SCU_RAM_AGC_SNS_SUM_MAX__A   0x831F37
 
#define SCU_RAM_AGC_SNS_CYCCNT__A   0x831F38
 
#define SCU_RAM_AGC_SNS_DIR_TO__A   0x831F39
 
#define SCU_RAM_AGC_SNS_DIR_WD__A   0x831F3A
 
#define SCU_RAM_AGC_SNS_DIR_STP__A   0x831F3B
 
#define SCU_RAM_AGC_INGAIN_TGT__A   0x831F3D
 
#define SCU_RAM_AGC_INGAIN_TGT_MIN__A   0x831F3E
 
#define SCU_RAM_AGC_INGAIN_TGT_MAX__A   0x831F3F
 
#define SCU_RAM_AGC_IF_IACCU_HI__A   0x831F40
 
#define SCU_RAM_AGC_IF_IACCU_LO__A   0x831F41
 
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A   0x831F42
 
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A   0x831F43
 
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A   0x831F44
 
#define SCU_RAM_AGC_RF_IACCU_HI__A   0x831F45
 
#define SCU_RAM_AGC_RF_IACCU_LO__A   0x831F46
 
#define SCU_RAM_AGC_RF_IACCU_HI_CO__A   0x831F47
 
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A   0x831F84
 
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A   0x831F85
 
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A   0x831F86
 
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A   0x831F87
 
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A   0x831F88
 
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A   0x831F89
 
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A   0x831F8A
 
#define SCU_RAM_QAM_FSM_RTH__A   0x831F8E
 
#define SCU_RAM_QAM_FSM_FTH__A   0x831F8F
 
#define SCU_RAM_QAM_FSM_PTH__A   0x831F90
 
#define SCU_RAM_QAM_FSM_MTH__A   0x831F91
 
#define SCU_RAM_QAM_FSM_CTH__A   0x831F92
 
#define SCU_RAM_QAM_FSM_QTH__A   0x831F93
 
#define SCU_RAM_QAM_FSM_RATE_LIM__A   0x831F94
 
#define SCU_RAM_QAM_FSM_FREQ_LIM__A   0x831F95
 
#define SCU_RAM_QAM_FSM_COUNT_LIM__A   0x831F96
 
#define SCU_RAM_QAM_LC_CA_COARSE__A   0x831F97
 
#define SCU_RAM_QAM_LC_CA_FINE__A   0x831F99
 
#define SCU_RAM_QAM_LC_CP_COARSE__A   0x831F9A
 
#define SCU_RAM_QAM_LC_CP_MEDIUM__A   0x831F9B
 
#define SCU_RAM_QAM_LC_CP_FINE__A   0x831F9C
 
#define SCU_RAM_QAM_LC_CI_COARSE__A   0x831F9D
 
#define SCU_RAM_QAM_LC_CI_MEDIUM__A   0x831F9E
 
#define SCU_RAM_QAM_LC_CI_FINE__A   0x831F9F
 
#define SCU_RAM_QAM_LC_EP_COARSE__A   0x831FA0
 
#define SCU_RAM_QAM_LC_EP_MEDIUM__A   0x831FA1
 
#define SCU_RAM_QAM_LC_EP_FINE__A   0x831FA2
 
#define SCU_RAM_QAM_LC_EI_COARSE__A   0x831FA3
 
#define SCU_RAM_QAM_LC_EI_MEDIUM__A   0x831FA4
 
#define SCU_RAM_QAM_LC_EI_FINE__A   0x831FA5
 
#define SCU_RAM_QAM_LC_CF_COARSE__A   0x831FA6
 
#define SCU_RAM_QAM_LC_CF_MEDIUM__A   0x831FA7
 
#define SCU_RAM_QAM_LC_CF_FINE__A   0x831FA8
 
#define SCU_RAM_QAM_LC_CF1_COARSE__A   0x831FA9
 
#define SCU_RAM_QAM_LC_CF1_MEDIUM__A   0x831FAA
 
#define SCU_RAM_QAM_LC_CF1_FINE__A   0x831FAB
 
#define SCU_RAM_QAM_SL_SIG_POWER__A   0x831FAC
 
#define SCU_RAM_QAM_EQ_CMA_RAD0__A   0x831FAD
 
#define SCU_RAM_QAM_EQ_CMA_RAD1__A   0x831FAE
 
#define SCU_RAM_QAM_EQ_CMA_RAD2__A   0x831FAF
 
#define SCU_RAM_QAM_EQ_CMA_RAD3__A   0x831FB0
 
#define SCU_RAM_QAM_EQ_CMA_RAD4__A   0x831FB1
 
#define SCU_RAM_QAM_EQ_CMA_RAD5__A   0x831FB2
 
#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED   0x4000
 
#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED   0x8000
 
#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK   0xC000
 
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A   0x831FEA
 
#define SCU_RAM_DRIVER_VER_HI__A   0x831FEB
 
#define SCU_RAM_DRIVER_VER_LO__A   0x831FEC
 
#define SCU_RAM_PARAM_15__A   0x831FED
 
#define SCU_RAM_PARAM_0__A   0x831FFC
 
#define SCU_RAM_COMMAND__A   0x831FFD
 
#define SCU_RAM_COMMAND_CMD_DEMOD_RESET   0x1
 
#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV   0x2
 
#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM   0x3
 
#define SCU_RAM_COMMAND_CMD_DEMOD_START   0x4
 
#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK   0x5
 
#define SCU_RAM_COMMAND_CMD_DEMOD_STOP   0x9
 
#define SCU_RAM_COMMAND_STANDARD_QAM   0x200
 
#define SCU_RAM_COMMAND_STANDARD_OFDM   0x400
 
#define SIO_TOP_COMM_KEY__A   0x41000F
 
#define SIO_TOP_COMM_KEY_KEY   0xFABA
 
#define SIO_TOP_JTAGID_LO__A   0x410012
 
#define SIO_HI_RA_RAM_RES__A   0x420031
 
#define SIO_HI_RA_RAM_CMD__A   0x420032
 
#define SIO_HI_RA_RAM_CMD_RESET   0x2
 
#define SIO_HI_RA_RAM_CMD_CONFIG   0x3
 
#define SIO_HI_RA_RAM_CMD_BRDCTRL   0x7
 
#define SIO_HI_RA_RAM_PAR_1__A   0x420033
 
#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY   0x3945
 
#define SIO_HI_RA_RAM_PAR_2__A   0x420034
 
#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M   0x7F
 
#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN   0x0
 
#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED   0x4
 
#define SIO_HI_RA_RAM_PAR_3__A   0x420035
 
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M   0x7F
 
#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B   7
 
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ   0x0
 
#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE   0x8
 
#define SIO_HI_RA_RAM_PAR_4__A   0x420036
 
#define SIO_HI_RA_RAM_PAR_5__A   0x420037
 
#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE   0x1
 
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M   0x8
 
#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ   0x8
 
#define SIO_HI_RA_RAM_PAR_6__A   0x420038
 
#define SIO_CC_PLL_LOCK__A   0x450012
 
#define SIO_CC_PWD_MODE__A   0x450015
 
#define SIO_CC_PWD_MODE_LEVEL_NONE   0x0
 
#define SIO_CC_PWD_MODE_LEVEL_OFDM   0x1
 
#define SIO_CC_PWD_MODE_LEVEL_CLOCK   0x2
 
#define SIO_CC_PWD_MODE_LEVEL_PLL   0x3
 
#define SIO_CC_PWD_MODE_LEVEL_OSC   0x4
 
#define SIO_CC_SOFT_RST__A   0x450016
 
#define SIO_CC_SOFT_RST_OFDM__M   0x1
 
#define SIO_CC_SOFT_RST_SYS__M   0x2
 
#define SIO_CC_SOFT_RST_OSC__M   0x4
 
#define SIO_CC_UPDATE__A   0x450017
 
#define SIO_CC_UPDATE_KEY   0xFABA
 
#define SIO_OFDM_SH_OFDM_RING_ENABLE__A   0x470010
 
#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF   0x0
 
#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON   0x1
 
#define SIO_OFDM_SH_OFDM_RING_STATUS__A   0x470012
 
#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN   0x0
 
#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED   0x1
 
#define SIO_BL_COMM_EXEC__A   0x480000
 
#define SIO_BL_COMM_EXEC_ACTIVE   0x1
 
#define SIO_BL_STATUS__A   0x480010
 
#define SIO_BL_MODE__A   0x480011
 
#define SIO_BL_MODE_DIRECT   0x0
 
#define SIO_BL_MODE_CHAIN   0x1
 
#define SIO_BL_ENABLE__A   0x480012
 
#define SIO_BL_ENABLE_ON   0x1
 
#define SIO_BL_TGT_HDR__A   0x480014
 
#define SIO_BL_TGT_ADDR__A   0x480015
 
#define SIO_BL_SRC_ADDR__A   0x480016
 
#define SIO_BL_SRC_LEN__A   0x480017
 
#define SIO_BL_CHAIN_ADDR__A   0x480018
 
#define SIO_BL_CHAIN_LEN__A   0x480019
 
#define SIO_PDR_MON_CFG__A   0x7F0010
 
#define SIO_PDR_UIO_IN_HI__A   0x7F0015
 
#define SIO_PDR_UIO_OUT_LO__A   0x7F0016
 
#define SIO_PDR_OHW_CFG__A   0x7F001F
 
#define SIO_PDR_OHW_CFG_FREF_SEL__M   0x3
 
#define SIO_PDR_GPIO_CFG__A   0x7F0021
 
#define SIO_PDR_MSTRT_CFG__A   0x7F0025
 
#define SIO_PDR_MERR_CFG__A   0x7F0026
 
#define SIO_PDR_MCLK_CFG__A   0x7F0028
 
#define SIO_PDR_MCLK_CFG_DRIVE__B   3
 
#define SIO_PDR_MVAL_CFG__A   0x7F0029
 
#define SIO_PDR_MD0_CFG__A   0x7F002A
 
#define SIO_PDR_MD0_CFG_DRIVE__B   3
 
#define SIO_PDR_MD1_CFG__A   0x7F002B
 
#define SIO_PDR_MD2_CFG__A   0x7F002C
 
#define SIO_PDR_MD3_CFG__A   0x7F002D
 
#define SIO_PDR_MD4_CFG__A   0x7F002F
 
#define SIO_PDR_MD5_CFG__A   0x7F0030
 
#define SIO_PDR_MD6_CFG__A   0x7F0031
 
#define SIO_PDR_MD7_CFG__A   0x7F0032
 
#define SIO_PDR_SMA_RX_CFG__A   0x7F0037
 
#define SIO_PDR_SMA_TX_CFG__A   0x7F0038
 

Macro Definition Documentation

#define AUD_COMM_EXEC__A   0x1000000

Definition at line 1 of file drxk_map.h.

#define AUD_COMM_EXEC_STOP   0x0

Definition at line 2 of file drxk_map.h.

#define FEC_COMM_EXEC__A   0x1C00000

Definition at line 3 of file drxk_map.h.

#define FEC_COMM_EXEC_ACTIVE   0x1

Definition at line 5 of file drxk_map.h.

#define FEC_COMM_EXEC_STOP   0x0

Definition at line 4 of file drxk_map.h.

#define FEC_DI_COMM_EXEC__A   0x1C20000

Definition at line 6 of file drxk_map.h.

#define FEC_DI_COMM_EXEC_STOP   0x0

Definition at line 7 of file drxk_map.h.

#define FEC_DI_INPUT_CTL__A   0x1C20016

Definition at line 8 of file drxk_map.h.

#define FEC_OC_AVR_PARM_A__A   0x1C40026

Definition at line 29 of file drxk_map.h.

#define FEC_OC_AVR_PARM_B__A   0x1C40027

Definition at line 30 of file drxk_map.h.

#define FEC_OC_DTO_BURST_LEN__A   0x1C40018

Definition at line 19 of file drxk_map.h.

#define FEC_OC_DTO_MODE__A   0x1C40014

Definition at line 15 of file drxk_map.h.

#define FEC_OC_DTO_MODE_DYNAMIC__M   0x1

Definition at line 16 of file drxk_map.h.

#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M   0x4

Definition at line 17 of file drxk_map.h.

#define FEC_OC_DTO_PERIOD__A   0x1C40015

Definition at line 18 of file drxk_map.h.

#define FEC_OC_FCT_MODE__A   0x1C4001A

Definition at line 20 of file drxk_map.h.

#define FEC_OC_FCT_MODE__PRE   0x0

Definition at line 21 of file drxk_map.h.

#define FEC_OC_FCT_MODE_RAT_ENA__M   0x1

Definition at line 22 of file drxk_map.h.

#define FEC_OC_FCT_MODE_VIRT_ENA__M   0x2

Definition at line 23 of file drxk_map.h.

#define FEC_OC_IPR_INVERT__A   0x1C40049

Definition at line 45 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MCLK__M   0x800

Definition at line 57 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD0__M   0x1

Definition at line 46 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD1__M   0x2

Definition at line 47 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD2__M   0x4

Definition at line 48 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD3__M   0x8

Definition at line 49 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD4__M   0x10

Definition at line 50 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD5__M   0x20

Definition at line 51 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD6__M   0x40

Definition at line 52 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MD7__M   0x80

Definition at line 53 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MERR__M   0x100

Definition at line 54 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MSTRT__M   0x200

Definition at line 55 of file drxk_map.h.

#define FEC_OC_IPR_INVERT_MVAL__M   0x400

Definition at line 56 of file drxk_map.h.

#define FEC_OC_IPR_MODE__A   0x1C40048

Definition at line 41 of file drxk_map.h.

#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M   0x4

Definition at line 43 of file drxk_map.h.

#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M   0x10

Definition at line 44 of file drxk_map.h.

#define FEC_OC_IPR_MODE_SERIAL__M   0x1

Definition at line 42 of file drxk_map.h.

#define FEC_OC_MODE__A   0x1C40011

Definition at line 13 of file drxk_map.h.

#define FEC_OC_MODE_PARITY__M   0x1

Definition at line 14 of file drxk_map.h.

#define FEC_OC_OCR_INVERT__A   0x1C40052

Definition at line 58 of file drxk_map.h.

#define FEC_OC_RCN_CTL_RATE_LO__A   0x1C40030

Definition at line 32 of file drxk_map.h.

#define FEC_OC_RCN_CTL_STEP_HI__A   0x1C40033

Definition at line 34 of file drxk_map.h.

#define FEC_OC_RCN_CTL_STEP_LO__A   0x1C40032

Definition at line 33 of file drxk_map.h.

#define FEC_OC_RCN_GAIN__A   0x1C4002E

Definition at line 31 of file drxk_map.h.

#define FEC_OC_SNC_FAIL_PERIOD__A   0x1C40046

Definition at line 40 of file drxk_map.h.

#define FEC_OC_SNC_HWM__A   0x1C40042

Definition at line 38 of file drxk_map.h.

#define FEC_OC_SNC_LWM__A   0x1C40041

Definition at line 37 of file drxk_map.h.

#define FEC_OC_SNC_MODE__A   0x1C40040

Definition at line 35 of file drxk_map.h.

#define FEC_OC_SNC_MODE_SHUTDOWN__M   0x10

Definition at line 36 of file drxk_map.h.

#define FEC_OC_SNC_UNLOCK__A   0x1C40043

Definition at line 39 of file drxk_map.h.

#define FEC_OC_TMD_COUNT__A   0x1C4001F

Definition at line 25 of file drxk_map.h.

#define FEC_OC_TMD_HI_MARGIN__A   0x1C40020

Definition at line 26 of file drxk_map.h.

#define FEC_OC_TMD_INT_UPD_RATE__A   0x1C40023

Definition at line 28 of file drxk_map.h.

#define FEC_OC_TMD_LO_MARGIN__A   0x1C40021

Definition at line 27 of file drxk_map.h.

#define FEC_OC_TMD_MODE__A   0x1C4001E

Definition at line 24 of file drxk_map.h.

#define FEC_RS_COMM_EXEC__A   0x1C30000

Definition at line 9 of file drxk_map.h.

#define FEC_RS_COMM_EXEC_STOP   0x0

Definition at line 10 of file drxk_map.h.

#define FEC_RS_MEASUREMENT_PERIOD__A   0x1C30012

Definition at line 11 of file drxk_map.h.

#define FEC_RS_MEASUREMENT_PRESCALE__A   0x1C30013

Definition at line 12 of file drxk_map.h.

#define IQM_AF_AGC_IF__A   0x1870028

Definition at line 112 of file drxk_map.h.

#define IQM_AF_AGC_RF__A   0x1870029

Definition at line 113 of file drxk_map.h.

#define IQM_AF_AMUX__A   0x187002D

Definition at line 122 of file drxk_map.h.

#define IQM_AF_AMUX_SIGNAL2ADC   0x1

Definition at line 123 of file drxk_map.h.

#define IQM_AF_CLKNEG__A   0x1870012

Definition at line 101 of file drxk_map.h.

#define IQM_AF_CLKNEG_CLKNEGDATA__M   0x2

Definition at line 102 of file drxk_map.h.

#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG   0x2

Definition at line 104 of file drxk_map.h.

#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS   0x0

Definition at line 103 of file drxk_map.h.

#define IQM_AF_CLP_LEN__A   0x1870023

Definition at line 109 of file drxk_map.h.

#define IQM_AF_CLP_TH__A   0x1870024

Definition at line 110 of file drxk_map.h.

#define IQM_AF_COMM_EXEC__A   0x1870000

Definition at line 99 of file drxk_map.h.

#define IQM_AF_COMM_EXEC_ACTIVE   0x1

Definition at line 100 of file drxk_map.h.

#define IQM_AF_INC_BYPASS__A   0x1870036

Definition at line 126 of file drxk_map.h.

#define IQM_AF_INC_LCT__A   0x1870034

Definition at line 125 of file drxk_map.h.

#define IQM_AF_PDREF__A   0x187002B

Definition at line 114 of file drxk_map.h.

#define IQM_AF_PDREF__M   0x1F

Definition at line 115 of file drxk_map.h.

#define IQM_AF_PHASE0__A   0x187001C

Definition at line 106 of file drxk_map.h.

#define IQM_AF_PHASE1__A   0x187001D

Definition at line 107 of file drxk_map.h.

#define IQM_AF_PHASE2__A   0x187001E

Definition at line 108 of file drxk_map.h.

#define IQM_AF_SNS_LEN__A   0x1870026

Definition at line 111 of file drxk_map.h.

#define IQM_AF_START_LOCK__A   0x187001B

Definition at line 105 of file drxk_map.h.

#define IQM_AF_STDBY__A   0x187002C

Definition at line 116 of file drxk_map.h.

#define IQM_AF_STDBY_STDBY_ADC_STANDBY   0x2

Definition at line 117 of file drxk_map.h.

#define IQM_AF_STDBY_STDBY_AMP_STANDBY   0x4

Definition at line 118 of file drxk_map.h.

#define IQM_AF_STDBY_STDBY_PD_STANDBY   0x8

Definition at line 119 of file drxk_map.h.

#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY   0x10

Definition at line 120 of file drxk_map.h.

#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY   0x20

Definition at line 121 of file drxk_map.h.

#define IQM_AF_UPD_SEL__A   0x187002F

Definition at line 124 of file drxk_map.h.

#define IQM_CF_ADJ_SEL__A   0x1860013

Definition at line 85 of file drxk_map.h.

#define IQM_CF_BYPASSDET__A   0x1860067

Definition at line 98 of file drxk_map.h.

#define IQM_CF_CLP_VAL__A   0x1860060

Definition at line 93 of file drxk_map.h.

#define IQM_CF_COMM_INT_MSK__A   0x1860006

Definition at line 77 of file drxk_map.h.

#define IQM_CF_DATATH__A   0x1860061

Definition at line 94 of file drxk_map.h.

#define IQM_CF_DET_LCT__A   0x1860064

Definition at line 97 of file drxk_map.h.

#define IQM_CF_DS_ENA__A   0x1860019

Definition at line 90 of file drxk_map.h.

#define IQM_CF_MIDTAP__A   0x1860011

Definition at line 79 of file drxk_map.h.

#define IQM_CF_MIDTAP_IM__B   1

Definition at line 81 of file drxk_map.h.

#define IQM_CF_MIDTAP_RE__B   0

Definition at line 80 of file drxk_map.h.

#define IQM_CF_OUT_ENA__A   0x1860012

Definition at line 82 of file drxk_map.h.

#define IQM_CF_OUT_ENA_OFDM__M   0x4

Definition at line 84 of file drxk_map.h.

#define IQM_CF_OUT_ENA_QAM__B   1

Definition at line 83 of file drxk_map.h.

#define IQM_CF_PKDTH__A   0x1860062

Definition at line 95 of file drxk_map.h.

#define IQM_CF_POW_MEAS_LEN__A   0x1860017

Definition at line 89 of file drxk_map.h.

#define IQM_CF_SCALE__A   0x1860014

Definition at line 86 of file drxk_map.h.

#define IQM_CF_SCALE_SH__A   0x1860015

Definition at line 87 of file drxk_map.h.

#define IQM_CF_SCALE_SH__PRE   0x0

Definition at line 88 of file drxk_map.h.

#define IQM_CF_SYMMETRIC__A   0x1860010

Definition at line 78 of file drxk_map.h.

#define IQM_CF_TAP_IM0__A   0x1860040

Definition at line 92 of file drxk_map.h.

#define IQM_CF_TAP_RE0__A   0x1860020

Definition at line 91 of file drxk_map.h.

#define IQM_CF_WND_LEN__A   0x1860063

Definition at line 96 of file drxk_map.h.

#define IQM_COMM_EXEC__A   0x1800000

Definition at line 59 of file drxk_map.h.

#define IQM_COMM_EXEC_B_ACTIVE   0x1

Definition at line 61 of file drxk_map.h.

#define IQM_COMM_EXEC_B_STOP   0x0

Definition at line 60 of file drxk_map.h.

#define IQM_FD_RATESEL__A   0x1830010

Definition at line 67 of file drxk_map.h.

#define IQM_FS_ADJ_SEL__A   0x1820014

Definition at line 63 of file drxk_map.h.

#define IQM_FS_ADJ_SEL_B_OFF   0x0

Definition at line 64 of file drxk_map.h.

#define IQM_FS_ADJ_SEL_B_QAM   0x1

Definition at line 65 of file drxk_map.h.

#define IQM_FS_ADJ_SEL_B_VSB   0x2

Definition at line 66 of file drxk_map.h.

#define IQM_FS_RATE_OFS_LO__A   0x1820010

Definition at line 62 of file drxk_map.h.

#define IQM_RC_ADJ_SEL__A   0x1840014

Definition at line 72 of file drxk_map.h.

#define IQM_RC_ADJ_SEL_B_OFF   0x0

Definition at line 73 of file drxk_map.h.

#define IQM_RC_ADJ_SEL_B_QAM   0x1

Definition at line 74 of file drxk_map.h.

#define IQM_RC_ADJ_SEL_B_VSB   0x2

Definition at line 75 of file drxk_map.h.

#define IQM_RC_RATE_OFS_HI__M   0xFF

Definition at line 71 of file drxk_map.h.

#define IQM_RC_RATE_OFS_LO__A   0x1840010

Definition at line 68 of file drxk_map.h.

#define IQM_RC_RATE_OFS_LO__M   0xFFFF

Definition at line 70 of file drxk_map.h.

#define IQM_RC_RATE_OFS_LO__W   16

Definition at line 69 of file drxk_map.h.

#define IQM_RC_STRETCH__A   0x1840016

Definition at line 76 of file drxk_map.h.

#define OFDM_CP_COMM_EXEC__A   0x2800000

Definition at line 127 of file drxk_map.h.

#define OFDM_CP_COMM_EXEC_STOP   0x0

Definition at line 128 of file drxk_map.h.

#define OFDM_EC_SB_PRIOR__A   0x3410013

Definition at line 129 of file drxk_map.h.

#define OFDM_EC_SB_PRIOR_HI   0x0

Definition at line 130 of file drxk_map.h.

#define OFDM_EC_SB_PRIOR_LO   0x1

Definition at line 131 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A   0x3010061

Definition at line 141 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A   0x3010060

Definition at line 140 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_SQR_ERR_I__A   0x301005E

Definition at line 138 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A   0x301005F

Definition at line 139 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A   0x3010056

Definition at line 135 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M   0x7

Definition at line 136 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8   0x4

Definition at line 137 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM   0x2

Definition at line 134 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_CONST__A   0x3010054

Definition at line 132 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_CONST__M   0x3

Definition at line 133 of file drxk_map.h.

#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A   0x3010062

Definition at line 142 of file drxk_map.h.

#define OFDM_LC_COMM_EXEC__A   0x3800000

Definition at line 143 of file drxk_map.h.

#define OFDM_LC_COMM_EXEC_STOP   0x0

Definition at line 144 of file drxk_map.h.

#define OFDM_SC_COMM_EXEC__A   0x3C00000

Definition at line 145 of file drxk_map.h.

#define OFDM_SC_COMM_EXEC_STOP   0x0

Definition at line 146 of file drxk_map.h.

#define OFDM_SC_COMM_STATE__A   0x3C00001

Definition at line 147 of file drxk_map.h.

#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A   0x3C2004D

Definition at line 194 of file drxk_map.h.

#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A   0x3C2004E

Definition at line 195 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD__A   0x3C20043

Definition at line 151 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_ADDR__A   0x3C20042

Definition at line 150 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM   0x5

Definition at line 156 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_NULL   0x0

Definition at line 152 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_PROC_START   0x1

Definition at line 153 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM   0x4

Definition at line 155 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING   0x8

Definition at line 159 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM   0x3

Definition at line 154 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_SET_TIMER   0x7

Definition at line 158 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CMD_USER_IO   0x6

Definition at line 157 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CONFIG__A   0x3C20050

Definition at line 201 of file drxk_map.h.

#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M   0x800

Definition at line 202 of file drxk_map.h.

#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B   8

Definition at line 199 of file drxk_map.h.

#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M   0xFF00

Definition at line 200 of file drxk_map.h.

#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B   0

Definition at line 197 of file drxk_map.h.

#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M   0xFF

Definition at line 198 of file drxk_map.h.

#define OFDM_SC_RA_RAM_ECHO_THRES__A   0x3C2004F

Definition at line 196 of file drxk_map.h.

#define OFDM_SC_RA_RAM_FR_THRES_8K__A   0x3C2007D

Definition at line 203 of file drxk_map.h.

#define OFDM_SC_RA_RAM_LOCK__A   0x3C2004B

Definition at line 189 of file drxk_map.h.

#define OFDM_SC_RA_RAM_LOCK_DEMOD__M   0x1

Definition at line 190 of file drxk_map.h.

#define OFDM_SC_RA_RAM_LOCK_FEC__M   0x2

Definition at line 191 of file drxk_map.h.

#define OFDM_SC_RA_RAM_LOCK_MPEG__M   0x4

Definition at line 192 of file drxk_map.h.

#define OFDM_SC_RA_RAM_LOCK_NODVBT__M   0x8

Definition at line 193 of file drxk_map.h.

#define OFDM_SC_RA_RAM_LOCKTRACK_MIN   0x1

Definition at line 161 of file drxk_map.h.

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A   0x3C200E0

Definition at line 204 of file drxk_map.h.

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A   0x3C200E1

Definition at line 205 of file drxk_map.h.

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A   0x3C200E3

Definition at line 206 of file drxk_map.h.

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A   0x3C200E4

Definition at line 207 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M   0x4

Definition at line 186 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M   0x2

Definition at line 185 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M   0x8

Definition at line 187 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M   0x1

Definition at line 184 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M   0x10

Definition at line 188 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM__A   0x3C20048

Definition at line 162 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16   0x10

Definition at line 171 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64   0x20

Definition at line 172 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK   0x0

Definition at line 170 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16   0x4

Definition at line 167 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32   0x0

Definition at line 166 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4   0xC

Definition at line 169 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8   0x8

Definition at line 168 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1   0x40

Definition at line 174 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2   0x80

Definition at line 175 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4   0xC0

Definition at line 176 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO   0x0

Definition at line 173 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K   0x0

Definition at line 164 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K   0x1

Definition at line 165 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M   0x3

Definition at line 163 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI   0x0

Definition at line 182 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO   0x1000

Definition at line 183 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2   0x0

Definition at line 177 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3   0x200

Definition at line 178 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4   0x400

Definition at line 179 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6   0x600

Definition at line 180 of file drxk_map.h.

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8   0x800

Definition at line 181 of file drxk_map.h.

#define OFDM_SC_RA_RAM_PARAM0__A   0x3C20040

Definition at line 148 of file drxk_map.h.

#define OFDM_SC_RA_RAM_PARAM1__A   0x3C20041

Definition at line 149 of file drxk_map.h.

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A   0x3C200F8

Definition at line 208 of file drxk_map.h.

#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M   0x1

Definition at line 160 of file drxk_map.h.

#define QAM_COMM_EXEC__A   0x1400000

Definition at line 209 of file drxk_map.h.

#define QAM_COMM_EXEC_ACTIVE   0x1

Definition at line 211 of file drxk_map.h.

#define QAM_COMM_EXEC_STOP   0x0

Definition at line 210 of file drxk_map.h.

#define QAM_DQ_QUAL_FUN0__A   0x1440018

Definition at line 215 of file drxk_map.h.

#define QAM_DQ_QUAL_FUN1__A   0x1440019

Definition at line 216 of file drxk_map.h.

#define QAM_DQ_QUAL_FUN2__A   0x144001A

Definition at line 217 of file drxk_map.h.

#define QAM_DQ_QUAL_FUN3__A   0x144001B

Definition at line 218 of file drxk_map.h.

#define QAM_DQ_QUAL_FUN4__A   0x144001C

Definition at line 219 of file drxk_map.h.

#define QAM_DQ_QUAL_FUN5__A   0x144001D

Definition at line 220 of file drxk_map.h.

#define QAM_LC_LPF_FACTORI__A   0x1450029

Definition at line 238 of file drxk_map.h.

#define QAM_LC_LPF_FACTORP__A   0x1450028

Definition at line 237 of file drxk_map.h.

#define QAM_LC_MODE__A   0x1450010

Definition at line 221 of file drxk_map.h.

#define QAM_LC_QUAL_TAB0__A   0x1450018

Definition at line 222 of file drxk_map.h.

#define QAM_LC_QUAL_TAB10__A   0x1450021

Definition at line 231 of file drxk_map.h.

#define QAM_LC_QUAL_TAB12__A   0x1450022

Definition at line 232 of file drxk_map.h.

#define QAM_LC_QUAL_TAB15__A   0x1450023

Definition at line 233 of file drxk_map.h.

#define QAM_LC_QUAL_TAB16__A   0x1450024

Definition at line 234 of file drxk_map.h.

#define QAM_LC_QUAL_TAB1__A   0x1450019

Definition at line 223 of file drxk_map.h.

#define QAM_LC_QUAL_TAB20__A   0x1450025

Definition at line 235 of file drxk_map.h.

#define QAM_LC_QUAL_TAB25__A   0x1450026

Definition at line 236 of file drxk_map.h.

#define QAM_LC_QUAL_TAB2__A   0x145001A

Definition at line 224 of file drxk_map.h.

#define QAM_LC_QUAL_TAB3__A   0x145001B

Definition at line 225 of file drxk_map.h.

#define QAM_LC_QUAL_TAB4__A   0x145001C

Definition at line 226 of file drxk_map.h.

#define QAM_LC_QUAL_TAB5__A   0x145001D

Definition at line 227 of file drxk_map.h.

#define QAM_LC_QUAL_TAB6__A   0x145001E

Definition at line 228 of file drxk_map.h.

#define QAM_LC_QUAL_TAB8__A   0x145001F

Definition at line 229 of file drxk_map.h.

#define QAM_LC_QUAL_TAB9__A   0x1450020

Definition at line 230 of file drxk_map.h.

#define QAM_LC_RATE_LIMIT__A   0x145002A

Definition at line 239 of file drxk_map.h.

#define QAM_LC_SYMBOL_FREQ__A   0x145002B

Definition at line 240 of file drxk_map.h.

#define QAM_SL_ERR_POWER__A   0x1430017

Definition at line 214 of file drxk_map.h.

#define QAM_SY_SP_INV__A   0x1470017

Definition at line 246 of file drxk_map.h.

#define QAM_SY_SP_INV_SPECTRUM_INV_DIS   0x0

Definition at line 247 of file drxk_map.h.

#define QAM_SY_SYNC_AWM__A   0x1470013

Definition at line 244 of file drxk_map.h.

#define QAM_SY_SYNC_HWM__A   0x1470014

Definition at line 245 of file drxk_map.h.

#define QAM_SY_SYNC_LWM__A   0x1470012

Definition at line 243 of file drxk_map.h.

#define QAM_SY_TIMEOUT__A   0x1470011

Definition at line 241 of file drxk_map.h.

#define QAM_SY_TIMEOUT__PRE   0x3A98

Definition at line 242 of file drxk_map.h.

#define QAM_TOP_ANNEX_A   0x0

Definition at line 212 of file drxk_map.h.

#define QAM_TOP_ANNEX_C   0x2

Definition at line 213 of file drxk_map.h.

#define SCU_COMM_EXEC__A   0x800000

Definition at line 248 of file drxk_map.h.

#define SCU_COMM_EXEC_ACTIVE   0x1

Definition at line 250 of file drxk_map.h.

#define SCU_COMM_EXEC_HOLD   0x2

Definition at line 251 of file drxk_map.h.

#define SCU_COMM_EXEC_STOP   0x0

Definition at line 249 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_CTRL_MODE__A   0x831EC8

Definition at line 256 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_CYCCNT__A   0x831F31

Definition at line 290 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_CYCLEN__A   0x831F30

Definition at line 289 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_DIR_STP__A   0x831F34

Definition at line 293 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_DIR_TO__A   0x831F32

Definition at line 291 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_DIR_WD__A   0x831F33

Definition at line 292 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_SUM__A   0x831F2D

Definition at line 286 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_SUM_MAX__A   0x831F2F

Definition at line 288 of file drxk_map.h.

#define SCU_RAM_AGC_CLP_SUM_MIN__A   0x831F2E

Definition at line 287 of file drxk_map.h.

#define SCU_RAM_AGC_CONFIG__A   0x831F24

Definition at line 265 of file drxk_map.h.

#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M   0x2

Definition at line 267 of file drxk_map.h.

#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M   0x1

Definition at line 266 of file drxk_map.h.

#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M   0x100

Definition at line 268 of file drxk_map.h.

#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M   0x200

Definition at line 269 of file drxk_map.h.

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A   0x831FEA

Definition at line 358 of file drxk_map.h.

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A   0x831F15

Definition at line 259 of file drxk_map.h.

#define SCU_RAM_AGC_IF_IACCU_HI__A   0x831F40

Definition at line 304 of file drxk_map.h.

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A   0x831F42

Definition at line 306 of file drxk_map.h.

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A   0x831F44

Definition at line 308 of file drxk_map.h.

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A   0x831F43

Definition at line 307 of file drxk_map.h.

#define SCU_RAM_AGC_IF_IACCU_LO__A   0x831F41

Definition at line 305 of file drxk_map.h.

#define SCU_RAM_AGC_INGAIN_TGT__A   0x831F3D

Definition at line 301 of file drxk_map.h.

#define SCU_RAM_AGC_INGAIN_TGT_MAX__A   0x831F3F

Definition at line 303 of file drxk_map.h.

#define SCU_RAM_AGC_INGAIN_TGT_MIN__A   0x831F3E

Definition at line 302 of file drxk_map.h.

#define SCU_RAM_AGC_KI__A   0x831F25

Definition at line 270 of file drxk_map.h.

#define SCU_RAM_AGC_KI_CYCLEN__A   0x831F17

Definition at line 260 of file drxk_map.h.

#define SCU_RAM_AGC_KI_IF__B   8

Definition at line 273 of file drxk_map.h.

#define SCU_RAM_AGC_KI_IF__M   0xF00

Definition at line 274 of file drxk_map.h.

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A   0x831F27

Definition at line 280 of file drxk_map.h.

#define SCU_RAM_AGC_KI_MAX__A   0x831F2C

Definition at line 285 of file drxk_map.h.

#define SCU_RAM_AGC_KI_MAXGAIN__A   0x831F29

Definition at line 282 of file drxk_map.h.

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A   0x831F2A

Definition at line 283 of file drxk_map.h.

#define SCU_RAM_AGC_KI_MIN__A   0x831F2B

Definition at line 284 of file drxk_map.h.

#define SCU_RAM_AGC_KI_MINGAIN__A   0x831F28

Definition at line 281 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RED__A   0x831F26

Definition at line 275 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RED_IAGC_RED__B   4

Definition at line 278 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RED_IAGC_RED__M   0x30

Definition at line 279 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RED_RAGC_RED__B   2

Definition at line 276 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RED_RAGC_RED__M   0xC

Definition at line 277 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RF__B   4

Definition at line 271 of file drxk_map.h.

#define SCU_RAM_AGC_KI_RF__M   0xF0

Definition at line 272 of file drxk_map.h.

#define SCU_RAM_AGC_RF_IACCU_HI__A   0x831F45

Definition at line 309 of file drxk_map.h.

#define SCU_RAM_AGC_RF_IACCU_HI_CO__A   0x831F47

Definition at line 311 of file drxk_map.h.

#define SCU_RAM_AGC_RF_IACCU_LO__A   0x831F46

Definition at line 310 of file drxk_map.h.

#define SCU_RAM_AGC_RF_MAX__A   0x831F1B

Definition at line 264 of file drxk_map.h.

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A   0x831F19

Definition at line 262 of file drxk_map.h.

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A   0x831F1A

Definition at line 263 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_CYCCNT__A   0x831F38

Definition at line 297 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_CYCLEN__A   0x831F18

Definition at line 261 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_DIR_STP__A   0x831F3B

Definition at line 300 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_DIR_TO__A   0x831F39

Definition at line 298 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_DIR_WD__A   0x831F3A

Definition at line 299 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_SUM__A   0x831F35

Definition at line 294 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_SUM_MAX__A   0x831F37

Definition at line 296 of file drxk_map.h.

#define SCU_RAM_AGC_SNS_SUM_MIN__A   0x831F36

Definition at line 295 of file drxk_map.h.

#define SCU_RAM_COMMAND__A   0x831FFD

Definition at line 363 of file drxk_map.h.

#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK   0x5

Definition at line 368 of file drxk_map.h.

#define SCU_RAM_COMMAND_CMD_DEMOD_RESET   0x1

Definition at line 364 of file drxk_map.h.

#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV   0x2

Definition at line 365 of file drxk_map.h.

#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM   0x3

Definition at line 366 of file drxk_map.h.

#define SCU_RAM_COMMAND_CMD_DEMOD_START   0x4

Definition at line 367 of file drxk_map.h.

#define SCU_RAM_COMMAND_CMD_DEMOD_STOP   0x9

Definition at line 369 of file drxk_map.h.

#define SCU_RAM_COMMAND_STANDARD_OFDM   0x400

Definition at line 371 of file drxk_map.h.

#define SCU_RAM_COMMAND_STANDARD_QAM   0x200

Definition at line 370 of file drxk_map.h.

#define SCU_RAM_DRIVER_DEBUG__A   0x831EBF

Definition at line 252 of file drxk_map.h.

#define SCU_RAM_DRIVER_VER_HI__A   0x831FEB

Definition at line 359 of file drxk_map.h.

#define SCU_RAM_DRIVER_VER_LO__A   0x831FEC

Definition at line 360 of file drxk_map.h.

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A   0x831ECB

Definition at line 257 of file drxk_map.h.

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A   0x831F05

Definition at line 258 of file drxk_map.h.

#define SCU_RAM_GPIO__A   0x831EC7

Definition at line 254 of file drxk_map.h.

#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE   0x0

Definition at line 255 of file drxk_map.h.

#define SCU_RAM_PARAM_0__A   0x831FFC

Definition at line 362 of file drxk_map.h.

#define SCU_RAM_PARAM_15__A   0x831FED

Definition at line 361 of file drxk_map.h.

#define SCU_RAM_QAM_EQ_CMA_RAD0__A   0x831FAD

Definition at line 349 of file drxk_map.h.

#define SCU_RAM_QAM_EQ_CMA_RAD1__A   0x831FAE

Definition at line 350 of file drxk_map.h.

#define SCU_RAM_QAM_EQ_CMA_RAD2__A   0x831FAF

Definition at line 351 of file drxk_map.h.

#define SCU_RAM_QAM_EQ_CMA_RAD3__A   0x831FB0

Definition at line 352 of file drxk_map.h.

#define SCU_RAM_QAM_EQ_CMA_RAD4__A   0x831FB1

Definition at line 353 of file drxk_map.h.

#define SCU_RAM_QAM_EQ_CMA_RAD5__A   0x831FB2

Definition at line 354 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_COUNT_LIM__A   0x831F96

Definition at line 327 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_CTH__A   0x831F92

Definition at line 323 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_FREQ_LIM__A   0x831F95

Definition at line 326 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_FTH__A   0x831F8F

Definition at line 320 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A   0x831F86

Definition at line 314 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A   0x831F87

Definition at line 315 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A   0x831F88

Definition at line 316 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A   0x831F89

Definition at line 317 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A   0x831F8A

Definition at line 318 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A   0x831F84

Definition at line 312 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_MTH__A   0x831F91

Definition at line 322 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_PTH__A   0x831F90

Definition at line 321 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_QTH__A   0x831F93

Definition at line 324 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A   0x831F85

Definition at line 313 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_RATE_LIM__A   0x831F94

Definition at line 325 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_RTH__A   0x831F8E

Definition at line 319 of file drxk_map.h.

#define SCU_RAM_QAM_FSM_STEP_PERIOD__A   0x831EC4

Definition at line 253 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CA_COARSE__A   0x831F97

Definition at line 328 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CA_FINE__A   0x831F99

Definition at line 329 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CF1_COARSE__A   0x831FA9

Definition at line 345 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CF1_FINE__A   0x831FAB

Definition at line 347 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CF1_MEDIUM__A   0x831FAA

Definition at line 346 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CF_COARSE__A   0x831FA6

Definition at line 342 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CF_FINE__A   0x831FA8

Definition at line 344 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CF_MEDIUM__A   0x831FA7

Definition at line 343 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CI_COARSE__A   0x831F9D

Definition at line 333 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CI_FINE__A   0x831F9F

Definition at line 335 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CI_MEDIUM__A   0x831F9E

Definition at line 334 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CP_COARSE__A   0x831F9A

Definition at line 330 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CP_FINE__A   0x831F9C

Definition at line 332 of file drxk_map.h.

#define SCU_RAM_QAM_LC_CP_MEDIUM__A   0x831F9B

Definition at line 331 of file drxk_map.h.

#define SCU_RAM_QAM_LC_EI_COARSE__A   0x831FA3

Definition at line 339 of file drxk_map.h.

#define SCU_RAM_QAM_LC_EI_FINE__A   0x831FA5

Definition at line 341 of file drxk_map.h.

#define SCU_RAM_QAM_LC_EI_MEDIUM__A   0x831FA4

Definition at line 340 of file drxk_map.h.

#define SCU_RAM_QAM_LC_EP_COARSE__A   0x831FA0

Definition at line 336 of file drxk_map.h.

#define SCU_RAM_QAM_LC_EP_FINE__A   0x831FA2

Definition at line 338 of file drxk_map.h.

#define SCU_RAM_QAM_LC_EP_MEDIUM__A   0x831FA1

Definition at line 337 of file drxk_map.h.

#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED   0x4000

Definition at line 355 of file drxk_map.h.

#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED   0x8000

Definition at line 356 of file drxk_map.h.

#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK   0xC000

Definition at line 357 of file drxk_map.h.

#define SCU_RAM_QAM_SL_SIG_POWER__A   0x831FAC

Definition at line 348 of file drxk_map.h.

#define SIO_BL_CHAIN_ADDR__A   0x480018

Definition at line 428 of file drxk_map.h.

#define SIO_BL_CHAIN_LEN__A   0x480019

Definition at line 429 of file drxk_map.h.

#define SIO_BL_COMM_EXEC__A   0x480000

Definition at line 416 of file drxk_map.h.

#define SIO_BL_COMM_EXEC_ACTIVE   0x1

Definition at line 417 of file drxk_map.h.

#define SIO_BL_ENABLE__A   0x480012

Definition at line 422 of file drxk_map.h.

#define SIO_BL_ENABLE_ON   0x1

Definition at line 423 of file drxk_map.h.

#define SIO_BL_MODE__A   0x480011

Definition at line 419 of file drxk_map.h.

#define SIO_BL_MODE_CHAIN   0x1

Definition at line 421 of file drxk_map.h.

#define SIO_BL_MODE_DIRECT   0x0

Definition at line 420 of file drxk_map.h.

#define SIO_BL_SRC_ADDR__A   0x480016

Definition at line 426 of file drxk_map.h.

#define SIO_BL_SRC_LEN__A   0x480017

Definition at line 427 of file drxk_map.h.

#define SIO_BL_STATUS__A   0x480010

Definition at line 418 of file drxk_map.h.

#define SIO_BL_TGT_ADDR__A   0x480015

Definition at line 425 of file drxk_map.h.

#define SIO_BL_TGT_HDR__A   0x480014

Definition at line 424 of file drxk_map.h.

#define SIO_CC_PLL_LOCK__A   0x450012

Definition at line 397 of file drxk_map.h.

#define SIO_CC_PWD_MODE__A   0x450015

Definition at line 398 of file drxk_map.h.

#define SIO_CC_PWD_MODE_LEVEL_CLOCK   0x2

Definition at line 401 of file drxk_map.h.

#define SIO_CC_PWD_MODE_LEVEL_NONE   0x0

Definition at line 399 of file drxk_map.h.

#define SIO_CC_PWD_MODE_LEVEL_OFDM   0x1

Definition at line 400 of file drxk_map.h.

#define SIO_CC_PWD_MODE_LEVEL_OSC   0x4

Definition at line 403 of file drxk_map.h.

#define SIO_CC_PWD_MODE_LEVEL_PLL   0x3

Definition at line 402 of file drxk_map.h.

#define SIO_CC_SOFT_RST__A   0x450016

Definition at line 404 of file drxk_map.h.

#define SIO_CC_SOFT_RST_OFDM__M   0x1

Definition at line 405 of file drxk_map.h.

#define SIO_CC_SOFT_RST_OSC__M   0x4

Definition at line 407 of file drxk_map.h.

#define SIO_CC_SOFT_RST_SYS__M   0x2

Definition at line 406 of file drxk_map.h.

#define SIO_CC_UPDATE__A   0x450017

Definition at line 408 of file drxk_map.h.

#define SIO_CC_UPDATE_KEY   0xFABA

Definition at line 409 of file drxk_map.h.

#define SIO_HI_RA_RAM_CMD__A   0x420032

Definition at line 376 of file drxk_map.h.

#define SIO_HI_RA_RAM_CMD_BRDCTRL   0x7

Definition at line 379 of file drxk_map.h.

#define SIO_HI_RA_RAM_CMD_CONFIG   0x3

Definition at line 378 of file drxk_map.h.

#define SIO_HI_RA_RAM_CMD_RESET   0x2

Definition at line 377 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_1__A   0x420033

Definition at line 380 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY   0x3945

Definition at line 381 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_2__A   0x420034

Definition at line 382 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED   0x4

Definition at line 385 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN   0x0

Definition at line 384 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M   0x7F

Definition at line 383 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_3__A   0x420035

Definition at line 386 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ   0x0

Definition at line 389 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE   0x8

Definition at line 390 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B   7

Definition at line 388 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M   0x7F

Definition at line 387 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_4__A   0x420036

Definition at line 391 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_5__A   0x420037

Definition at line 392 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M   0x8

Definition at line 394 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ   0x8

Definition at line 395 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE   0x1

Definition at line 393 of file drxk_map.h.

#define SIO_HI_RA_RAM_PAR_6__A   0x420038

Definition at line 396 of file drxk_map.h.

#define SIO_HI_RA_RAM_RES__A   0x420031

Definition at line 375 of file drxk_map.h.

#define SIO_OFDM_SH_OFDM_RING_ENABLE__A   0x470010

Definition at line 410 of file drxk_map.h.

#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF   0x0

Definition at line 411 of file drxk_map.h.

#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON   0x1

Definition at line 412 of file drxk_map.h.

#define SIO_OFDM_SH_OFDM_RING_STATUS__A   0x470012

Definition at line 413 of file drxk_map.h.

#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN   0x0

Definition at line 414 of file drxk_map.h.

#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED   0x1

Definition at line 415 of file drxk_map.h.

#define SIO_PDR_GPIO_CFG__A   0x7F0021

Definition at line 435 of file drxk_map.h.

#define SIO_PDR_MCLK_CFG__A   0x7F0028

Definition at line 438 of file drxk_map.h.

#define SIO_PDR_MCLK_CFG_DRIVE__B   3

Definition at line 439 of file drxk_map.h.

#define SIO_PDR_MD0_CFG__A   0x7F002A

Definition at line 441 of file drxk_map.h.

#define SIO_PDR_MD0_CFG_DRIVE__B   3

Definition at line 442 of file drxk_map.h.

#define SIO_PDR_MD1_CFG__A   0x7F002B

Definition at line 443 of file drxk_map.h.

#define SIO_PDR_MD2_CFG__A   0x7F002C

Definition at line 444 of file drxk_map.h.

#define SIO_PDR_MD3_CFG__A   0x7F002D

Definition at line 445 of file drxk_map.h.

#define SIO_PDR_MD4_CFG__A   0x7F002F

Definition at line 446 of file drxk_map.h.

#define SIO_PDR_MD5_CFG__A   0x7F0030

Definition at line 447 of file drxk_map.h.

#define SIO_PDR_MD6_CFG__A   0x7F0031

Definition at line 448 of file drxk_map.h.

#define SIO_PDR_MD7_CFG__A   0x7F0032

Definition at line 449 of file drxk_map.h.

#define SIO_PDR_MERR_CFG__A   0x7F0026

Definition at line 437 of file drxk_map.h.

#define SIO_PDR_MON_CFG__A   0x7F0010

Definition at line 430 of file drxk_map.h.

#define SIO_PDR_MSTRT_CFG__A   0x7F0025

Definition at line 436 of file drxk_map.h.

#define SIO_PDR_MVAL_CFG__A   0x7F0029

Definition at line 440 of file drxk_map.h.

#define SIO_PDR_OHW_CFG__A   0x7F001F

Definition at line 433 of file drxk_map.h.

#define SIO_PDR_OHW_CFG_FREF_SEL__M   0x3

Definition at line 434 of file drxk_map.h.

#define SIO_PDR_SMA_RX_CFG__A   0x7F0037

Definition at line 450 of file drxk_map.h.

#define SIO_PDR_SMA_TX_CFG__A   0x7F0038

Definition at line 451 of file drxk_map.h.

#define SIO_PDR_UIO_IN_HI__A   0x7F0015

Definition at line 431 of file drxk_map.h.

#define SIO_PDR_UIO_OUT_LO__A   0x7F0016

Definition at line 432 of file drxk_map.h.

#define SIO_TOP_COMM_KEY__A   0x41000F

Definition at line 372 of file drxk_map.h.

#define SIO_TOP_COMM_KEY_KEY   0xFABA

Definition at line 373 of file drxk_map.h.

#define SIO_TOP_JTAGID_LO__A   0x410012

Definition at line 374 of file drxk_map.h.