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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Macros | |
| #define | DS_REGA_DV2 0x40 /* countdown chain */ |
| #define | DS_REGA_DV1 0x20 /* oscillator enable */ |
| #define | DS_REGA_DV0 0x10 /* bank select */ |
| #define | DS_B1_MODEL 0x40 /* model number byte */ |
| #define | DS_B1_SN1 0x41 /* serial number byte 1 */ |
| #define | DS_B1_SN2 0x42 /* serial number byte 2 */ |
| #define | DS_B1_SN3 0x43 /* serial number byte 3 */ |
| #define | DS_B1_SN4 0x44 /* serial number byte 4 */ |
| #define | DS_B1_SN5 0x45 /* serial number byte 5 */ |
| #define | DS_B1_SN6 0x46 /* serial number byte 6 */ |
| #define | DS_B1_CRC 0x47 /* CRC byte */ |
| #define | DS_B1_CENTURY 0x48 /* Century byte */ |
| #define | DS_B1_DALARM 0x49 /* date alarm */ |
| #define | DS_B1_XCTRL4A 0x4a /* extendec control register 4a */ |
| #define | DS_B1_XCTRL4B 0x4b /* extendec control register 4b */ |
| #define | DS_B1_RTCADDR2 0x4e /* rtc address 2 */ |
| #define | DS_B1_RTCADDR3 0x4f /* rtc address 3 */ |
| #define | DS_B1_RAMLSB 0x50 /* extended ram LSB */ |
| #define | DS_B1_RAMMSB 0x51 /* extended ram MSB */ |
| #define | DS_B1_RAMDPORT 0x53 /* extended ram data port */ |
| #define | DS_XCTRL4A_VRT2 0x80 /* valid ram and time */ |
| #define | DS_XCTRL4A_INCR 0x40 /* increment progress status */ |
| #define | DS_XCTRL4A_BME 0x20 /* burst mode enable */ |
| #define | DS_XCTRL4A_PAB 0x08 /* power active bar ctrl */ |
| #define | DS_XCTRL4A_RF 0x04 /* ram clear flag */ |
| #define | DS_XCTRL4A_WF 0x02 /* wake up alarm flag */ |
| #define | DS_XCTRL4A_KF 0x01 /* kickstart flag */ |
| #define | DS_XCTRL4A_IFS (DS_XCTRL4A_RF|DS_XCTRL4A_WF|DS_XCTRL4A_KF) |
| #define | DS_XCTRL4B_ABE 0x80 /* auxiliary battery enable */ |
| #define | DS_XCTRL4B_E32K 0x40 /* enable 32.768 kHz Output */ |
| #define | DS_XCTRL4B_CS 0x20 /* crystal select */ |
| #define | DS_XCTRL4B_RCE 0x10 /* ram clear enable */ |
| #define | DS_XCTRL4B_PRS 0x08 /* PAB resec select */ |
| #define | DS_XCTRL4B_RIE 0x04 /* ram clear interrupt enable */ |
| #define | DS_XCTRL4B_WFE 0x02 /* wake up alarm interrupt enable */ |
| #define | DS_XCTRL4B_KFE 0x01 /* kickstart interrupt enable */ |
| #define | DS_XCTRL4B_IFES (DS_XCTRL4B_RIE|DS_XCTRL4B_WFE|DS_XCTRL4B_KFE) |
| #define DS_B1_CENTURY 0x48 /* Century byte */ |
Definition at line 30 of file ds17287rtc.h.
| #define DS_B1_CRC 0x47 /* CRC byte */ |
Definition at line 29 of file ds17287rtc.h.
| #define DS_B1_DALARM 0x49 /* date alarm */ |
Definition at line 31 of file ds17287rtc.h.
| #define DS_B1_MODEL 0x40 /* model number byte */ |
Definition at line 22 of file ds17287rtc.h.
| #define DS_B1_RAMDPORT 0x53 /* extended ram data port */ |
Definition at line 38 of file ds17287rtc.h.
| #define DS_B1_RAMLSB 0x50 /* extended ram LSB */ |
Definition at line 36 of file ds17287rtc.h.
| #define DS_B1_RAMMSB 0x51 /* extended ram MSB */ |
Definition at line 37 of file ds17287rtc.h.
| #define DS_B1_RTCADDR2 0x4e /* rtc address 2 */ |
Definition at line 34 of file ds17287rtc.h.
| #define DS_B1_RTCADDR3 0x4f /* rtc address 3 */ |
Definition at line 35 of file ds17287rtc.h.
| #define DS_B1_SN1 0x41 /* serial number byte 1 */ |
Definition at line 23 of file ds17287rtc.h.
| #define DS_B1_SN2 0x42 /* serial number byte 2 */ |
Definition at line 24 of file ds17287rtc.h.
| #define DS_B1_SN3 0x43 /* serial number byte 3 */ |
Definition at line 25 of file ds17287rtc.h.
| #define DS_B1_SN4 0x44 /* serial number byte 4 */ |
Definition at line 26 of file ds17287rtc.h.
| #define DS_B1_SN5 0x45 /* serial number byte 5 */ |
Definition at line 27 of file ds17287rtc.h.
| #define DS_B1_SN6 0x46 /* serial number byte 6 */ |
Definition at line 28 of file ds17287rtc.h.
| #define DS_B1_XCTRL4A 0x4a /* extendec control register 4a */ |
Definition at line 32 of file ds17287rtc.h.
| #define DS_B1_XCTRL4B 0x4b /* extendec control register 4b */ |
Definition at line 33 of file ds17287rtc.h.
| #define DS_REGA_DV0 0x10 /* bank select */ |
Definition at line 19 of file ds17287rtc.h.
| #define DS_REGA_DV1 0x20 /* oscillator enable */ |
Definition at line 18 of file ds17287rtc.h.
| #define DS_REGA_DV2 0x40 /* countdown chain */ |
Definition at line 17 of file ds17287rtc.h.
| #define DS_XCTRL4A_BME 0x20 /* burst mode enable */ |
Definition at line 44 of file ds17287rtc.h.
| #define DS_XCTRL4A_IFS (DS_XCTRL4A_RF|DS_XCTRL4A_WF|DS_XCTRL4A_KF) |
Definition at line 51 of file ds17287rtc.h.
| #define DS_XCTRL4A_INCR 0x40 /* increment progress status */ |
Definition at line 43 of file ds17287rtc.h.
| #define DS_XCTRL4A_KF 0x01 /* kickstart flag */ |
Definition at line 48 of file ds17287rtc.h.
| #define DS_XCTRL4A_PAB 0x08 /* power active bar ctrl */ |
Definition at line 45 of file ds17287rtc.h.
| #define DS_XCTRL4A_RF 0x04 /* ram clear flag */ |
Definition at line 46 of file ds17287rtc.h.
| #define DS_XCTRL4A_VRT2 0x80 /* valid ram and time */ |
Definition at line 42 of file ds17287rtc.h.
| #define DS_XCTRL4A_WF 0x02 /* wake up alarm flag */ |
Definition at line 47 of file ds17287rtc.h.
| #define DS_XCTRL4B_ABE 0x80 /* auxiliary battery enable */ |
Definition at line 54 of file ds17287rtc.h.
| #define DS_XCTRL4B_CS 0x20 /* crystal select */ |
Definition at line 56 of file ds17287rtc.h.
| #define DS_XCTRL4B_E32K 0x40 /* enable 32.768 kHz Output */ |
Definition at line 55 of file ds17287rtc.h.
| #define DS_XCTRL4B_IFES (DS_XCTRL4B_RIE|DS_XCTRL4B_WFE|DS_XCTRL4B_KFE) |
Definition at line 64 of file ds17287rtc.h.
| #define DS_XCTRL4B_KFE 0x01 /* kickstart interrupt enable */ |
Definition at line 61 of file ds17287rtc.h.
| #define DS_XCTRL4B_PRS 0x08 /* PAB resec select */ |
Definition at line 58 of file ds17287rtc.h.
| #define DS_XCTRL4B_RCE 0x10 /* ram clear enable */ |
Definition at line 57 of file ds17287rtc.h.
| #define DS_XCTRL4B_RIE 0x04 /* ram clear interrupt enable */ |
Definition at line 59 of file ds17287rtc.h.
| #define DS_XCTRL4B_WFE 0x02 /* wake up alarm interrupt enable */ |
Definition at line 60 of file ds17287rtc.h.
1.8.2