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dvma.h
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1 /*
2  * include/asm-m68k/dma.h
3  *
4  * Copyright 1995 (C) David S. Miller ([email protected])
5  *
6  * Hacked to fit Sun3x needs by Thomas Bogendoerfer
7  */
8 
9 #ifndef __M68K_DVMA_H
10 #define __M68K_DVMA_H
11 
12 
13 #define DVMA_PAGE_SHIFT 13
14 #define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
15 #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
16 #define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
17 
18 extern void dvma_init(void);
19 extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
20  int len);
21 
22 #define dvma_malloc(x) dvma_malloc_align(x, 0)
23 #define dvma_map(x, y) dvma_map_align(x, y, 0)
24 #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
25 #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
26 extern unsigned long dvma_map_align(unsigned long kaddr, int len,
27  int align);
28 extern void *dvma_malloc_align(unsigned long len, unsigned long align);
29 
30 extern void dvma_unmap(void *baddr);
31 extern void dvma_free(void *vaddr);
32 
33 
34 #ifdef CONFIG_SUN3
35 /* sun3 dvma page support */
36 
37 /* memory and pmegs potentially reserved for dvma */
38 #define DVMA_PMEG_START 10
39 #define DVMA_PMEG_END 16
40 #define DVMA_START 0xf00000
41 #define DVMA_END 0xfe0000
42 #define DVMA_SIZE (DVMA_END-DVMA_START)
43 #define IOMMU_TOTAL_ENTRIES 128
44 #define IOMMU_ENTRIES 120
45 
46 /* empirical kludge -- dvma regions only seem to work right on 0x10000
47  byte boundaries */
48 #define DVMA_REGION_SIZE 0x10000
49 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
50  ~(DVMA_REGION_SIZE-1))
51 
52 /* virt <-> phys conversions */
53 #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
54 #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
55 #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
56 #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
57 #define dvma_vtob(x) dvma_vtop(x)
58 #define dvma_btov(x) dvma_ptov(x)
59 
60 static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
61  int len)
62 {
63  return 0;
64 }
65 
66 #else /* Sun3x */
67 
68 /* sun3x dvma page support */
69 
70 #define DVMA_START 0x0
71 #define DVMA_END 0xf00000
72 #define DVMA_SIZE (DVMA_END-DVMA_START)
73 #define IOMMU_TOTAL_ENTRIES 2048
74 /* the prom takes the top meg */
75 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
76 
77 #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
78 #define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
79 
80 extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
81 
82 
83 
84 /* everything below this line is specific to dma used for the onboard
85  ESP scsi on sun3x */
86 
87 /* Structure to describe the current status of DMA registers on the Sparc */
88 struct sparc_dma_registers {
89  __volatile__ unsigned long cond_reg; /* DMA condition register */
90  __volatile__ unsigned long st_addr; /* Start address of this transfer */
91  __volatile__ unsigned long cnt; /* How many bytes to transfer */
92  __volatile__ unsigned long dma_test; /* DMA test register */
93 };
94 
95 /* DVMA chip revisions */
96 enum dvma_rev {
97  dvmarev0,
98  dvmaesc1,
99  dvmarev1,
100  dvmarev2,
101  dvmarev3,
102  dvmarevplus,
103  dvmahme
104 };
105 
106 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
107 
108 /* Linux DMA information structure, filled during probe. */
109 struct Linux_SBus_DMA {
110  struct Linux_SBus_DMA *next;
111  struct linux_sbus_device *SBus_dev;
112  struct sparc_dma_registers *regs;
113 
114  /* Status, misc info */
115  int node; /* Prom node for this DMA device */
116  int running; /* Are we doing DMA now? */
117  int allocated; /* Are we "owned" by anyone yet? */
118 
119  /* Transfer information. */
120  unsigned long addr; /* Start address of current transfer */
121  int nbytes; /* Size of current transfer */
122  int realbytes; /* For splitting up large transfers, etc. */
123 
124  /* DMA revision */
125  enum dvma_rev revision;
126 };
127 
128 extern struct Linux_SBus_DMA *dma_chain;
129 
130 /* Broken hardware... */
131 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
132 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
133 
134 /* Fields in the cond_reg register */
135 /* First, the version identification bits */
136 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
137 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
138 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
139 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
140 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
141 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
142 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
143 
144 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
145 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
146 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
147 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
148 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
149 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
150 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
151 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
152 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
153 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
154 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
155 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
156 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
157 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
158 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
159 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
160 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
161 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
162 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
163 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
164 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
165 #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
166 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
167 #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
168 #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
169 #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
170 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
171 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
172 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
173 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
174 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
175 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
176 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
177 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
178 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
179 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
180 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
181 
182 /* Values describing the burst-size property from the PROM */
183 #define DMA_BURST1 0x01
184 #define DMA_BURST2 0x02
185 #define DMA_BURST4 0x04
186 #define DMA_BURST8 0x08
187 #define DMA_BURST16 0x10
188 #define DMA_BURST32 0x20
189 #define DMA_BURST64 0x40
190 #define DMA_BURSTBITS 0x7f
191 
192 /* Determine highest possible final transfer address given a base */
193 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
194 
195 /* Yes, I hack a lot of elisp in my spare time... */
196 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
197 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
198 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
199 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
200 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
201 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
202 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
203 #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
204 #define DMA_BEGINDMA_W(regs) \
205  ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
206 #define DMA_BEGINDMA_R(regs) \
207  ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
208 
209 /* For certain DMA chips, we need to disable ints upon irq entry
210  * and turn them back on when we are done. So in any ESP interrupt
211  * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
212  * when leaving the handler. You have been warned...
213  */
214 #define DMA_IRQ_ENTRY(dma, dregs) do { \
215  if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
216  } while (0)
217 
218 #define DMA_IRQ_EXIT(dma, dregs) do { \
219  if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
220  } while(0)
221 
222 /* Reset the friggin' thing... */
223 #define DMA_RESET(dma) do { \
224  struct sparc_dma_registers *regs = dma->regs; \
225  /* Let the current FIFO drain itself */ \
226  sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
227  /* Reset the logic */ \
228  regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
229  __delay(400); /* let the bits set ;) */ \
230  regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
231  sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
232  /* Enable FAST transfers if available */ \
233  if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
234  dma->running = 0; \
235 } while(0)
236 
237 
238 #endif /* !CONFIG_SUN3 */
239 
240 #endif /* !(__M68K_DVMA_H) */
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