29 #ifndef __EHEA_QMR_H__
30 #define __EHEA_QMR_H__
32 #include <linux/prefetch.h>
40 #define EHEA_PAGESHIFT 12
41 #define EHEA_PAGESIZE (1UL << EHEA_PAGESHIFT)
42 #define EHEA_SECTSIZE (1UL << 24)
43 #define EHEA_PAGES_PER_SECTION (EHEA_SECTSIZE >> EHEA_PAGESHIFT)
44 #define EHEA_HUGEPAGESHIFT 34
45 #define EHEA_HUGEPAGE_SIZE (1UL << EHEA_HUGEPAGESHIFT)
46 #define EHEA_HUGEPAGE_PFN_MASK ((EHEA_HUGEPAGE_SIZE - 1) >> PAGE_SHIFT)
48 #if ((1UL << SECTION_SIZE_BITS) < EHEA_SECTSIZE)
49 #error eHEA module cannot work if kernel sectionsize < ehea sectionsize
63 #define EHEA_WR_ID_COUNT EHEA_BMASK_IBM(0, 19)
64 #define EHEA_WR_ID_TYPE EHEA_BMASK_IBM(20, 23)
65 #define EHEA_SWQE2_TYPE 0x1
66 #define EHEA_SWQE3_TYPE 0x2
67 #define EHEA_RWQE2_TYPE 0x3
68 #define EHEA_RWQE3_TYPE 0x4
69 #define EHEA_WR_ID_INDEX EHEA_BMASK_IBM(24, 47)
70 #define EHEA_WR_ID_REFILL EHEA_BMASK_IBM(48, 63)
79 #define EHEA_MAX_WQE_SG_ENTRIES 252
80 #define SWQE2_MAX_IMM (0xD0 - 0x30)
81 #define SWQE3_MAX_IMM 224
84 #define EHEA_SWQE_CRC 0x8000
85 #define EHEA_SWQE_IP_CHECKSUM 0x4000
86 #define EHEA_SWQE_TCP_CHECKSUM 0x2000
87 #define EHEA_SWQE_TSO 0x1000
88 #define EHEA_SWQE_SIGNALLED_COMPLETION 0x0800
89 #define EHEA_SWQE_VLAN_INSERT 0x0400
90 #define EHEA_SWQE_IMM_DATA_PRESENT 0x0200
91 #define EHEA_SWQE_DESCRIPTORS_PRESENT 0x0100
92 #define EHEA_SWQE_WRAP_CTL_REC 0x0080
93 #define EHEA_SWQE_WRAP_CTL_FORCE 0x0040
94 #define EHEA_SWQE_BIND 0x0020
95 #define EHEA_SWQE_PURGE 0x0010
98 #define SWQE_HEADER_SIZE 32
149 #define EHEA_CQE_VLAN_TAG_XTRACT 0x0400
151 #define EHEA_CQE_TYPE_RQ 0x60
152 #define EHEA_CQE_STAT_ERR_MASK 0x700F
153 #define EHEA_CQE_STAT_FAT_ERR_MASK 0xF
154 #define EHEA_CQE_BLIND_CKSUM 0x8000
155 #define EHEA_CQE_STAT_ERR_TCP 0x4000
156 #define EHEA_CQE_STAT_ERR_IP 0x2000
157 #define EHEA_CQE_STAT_ERR_CRC 0x1000
160 #define EHEA_CQE_STAT_RESET_MASK 0x0002
182 #define EHEA_EQE_VALID EHEA_BMASK_IBM(0, 0)
183 #define EHEA_EQE_IS_CQE EHEA_BMASK_IBM(1, 1)
184 #define EHEA_EQE_IDENTIFIER EHEA_BMASK_IBM(2, 7)
185 #define EHEA_EQE_QP_CQ_NUMBER EHEA_BMASK_IBM(8, 31)
186 #define EHEA_EQE_QP_TOKEN EHEA_BMASK_IBM(32, 63)
187 #define EHEA_EQE_CQ_TOKEN EHEA_BMASK_IBM(32, 63)
188 #define EHEA_EQE_KEY EHEA_BMASK_IBM(32, 63)
189 #define EHEA_EQE_PORT_NUMBER EHEA_BMASK_IBM(56, 63)
190 #define EHEA_EQE_EQ_NUMBER EHEA_BMASK_IBM(48, 63)
191 #define EHEA_EQE_SM_ID EHEA_BMASK_IBM(48, 63)
192 #define EHEA_EQE_SM_MECH_NUMBER EHEA_BMASK_IBM(48, 55)
193 #define EHEA_EQE_SM_PORT_NUMBER EHEA_BMASK_IBM(56, 63)
195 #define EHEA_AER_RESTYPE_QP 0x8
196 #define EHEA_AER_RESTYPE_CQ 0x4
197 #define EHEA_AER_RESTYPE_EQ 0x3
200 #define EHEA_AER_RESET_MASK 0xFFFFFFFFFEFFFFFFULL
201 #define EHEA_AERR_RESET_MASK 0xFFFFFFFFFFFFFFFFULL
207 #define ERROR_DATA_LENGTH EHEA_BMASK_IBM(52, 63)
208 #define ERROR_DATA_TYPE EHEA_BMASK_IBM(0, 7)
235 static inline void *hw_qeit_get_inc(
struct hw_queue *queue)
237 void *retvalue = hw_qeit_get(queue);
242 static inline void *hw_qeit_get_inc_valid(
struct hw_queue *queue)
244 struct ehea_cqe *retvalue = hw_qeit_get(queue);
259 static inline void *hw_qeit_get_valid(
struct hw_queue *queue)
261 struct ehea_cqe *retvalue = hw_qeit_get(queue);
269 valid = retvalue->
valid;
275 static inline void *hw_qeit_reset(
struct hw_queue *queue)
278 return hw_qeit_get(queue);
281 static inline void *hw_qeit_eq_get_inc(
struct hw_queue *queue)
286 retvalue = hw_qeit_get(queue);
295 static inline void *hw_eqit_eq_get_inc_valid(
struct hw_queue *queue)
297 void *retvalue = hw_qeit_get(queue);
298 u32 qe = *(
u8 *)retvalue;
300 hw_qeit_eq_get_inc(queue);
318 return hw_qeit_get_inc(queue);
328 wqe_p = hw_qeit_get_inc(&my_qp->
hw_squeue);
333 static inline void ehea_post_swqe(
struct ehea_qp *my_qp,
struct ehea_swqe *swqe)
336 ehea_update_sqa(my_qp, 1);
339 static inline struct ehea_cqe *ehea_poll_rq1(
struct ehea_qp *qp,
int *wqe_index)
344 return hw_qeit_get_valid(queue);
347 static inline void ehea_inc_cq(
struct ehea_cq *cq)
352 static inline void ehea_inc_rq1(
struct ehea_qp *qp)
359 return hw_qeit_get_valid(&my_cq->
hw_queue);
362 #define EHEA_CQ_REGISTER_ORIG 0
363 #define EHEA_EQ_REGISTER_ORIG 0
379 u64 eq_handle,
u32 cq_token);