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#define | IPR_DRIVER_VERSION "2.5.4" |
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#define | IPR_DRIVER_DATE "(July 11, 2012)" |
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#define | IPR_MAX_CMD_PER_LUN 6 |
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#define | IPR_MAX_CMD_PER_ATA_LUN 1 |
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#define | IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds) |
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#define | PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 |
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#define | PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D |
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#define | PCI_DEVICE_ID_IBM_CROCODILE 0x034A |
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#define | IPR_SUBS_DEV_ID_2780 0x0264 |
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#define | IPR_SUBS_DEV_ID_5702 0x0266 |
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#define | IPR_SUBS_DEV_ID_5703 0x0278 |
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#define | IPR_SUBS_DEV_ID_572E 0x028D |
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#define | IPR_SUBS_DEV_ID_573E 0x02D3 |
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#define | IPR_SUBS_DEV_ID_573D 0x02D4 |
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#define | IPR_SUBS_DEV_ID_571A 0x02C0 |
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#define | IPR_SUBS_DEV_ID_571B 0x02BE |
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#define | IPR_SUBS_DEV_ID_571E 0x02BF |
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#define | IPR_SUBS_DEV_ID_571F 0x02D5 |
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#define | IPR_SUBS_DEV_ID_572A 0x02C1 |
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#define | IPR_SUBS_DEV_ID_572B 0x02C2 |
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#define | IPR_SUBS_DEV_ID_572F 0x02C3 |
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#define | IPR_SUBS_DEV_ID_574E 0x030A |
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#define | IPR_SUBS_DEV_ID_575B 0x030D |
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#define | IPR_SUBS_DEV_ID_575C 0x0338 |
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#define | IPR_SUBS_DEV_ID_57B3 0x033A |
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#define | IPR_SUBS_DEV_ID_57B7 0x0360 |
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#define | IPR_SUBS_DEV_ID_57B8 0x02C2 |
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#define | IPR_SUBS_DEV_ID_57B4 0x033B |
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#define | IPR_SUBS_DEV_ID_57B2 0x035F |
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#define | IPR_SUBS_DEV_ID_57C3 0x0353 |
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#define | IPR_SUBS_DEV_ID_57C4 0x0354 |
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#define | IPR_SUBS_DEV_ID_57C6 0x0357 |
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#define | IPR_SUBS_DEV_ID_57CC 0x035C |
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#define | IPR_SUBS_DEV_ID_57B5 0x033C |
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#define | IPR_SUBS_DEV_ID_57CE 0x035E |
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#define | IPR_SUBS_DEV_ID_57B1 0x0355 |
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#define | IPR_SUBS_DEV_ID_574D 0x0356 |
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#define | IPR_SUBS_DEV_ID_57C8 0x035D |
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#define | IPR_NAME "ipr" |
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#define | IPR_RC_JOB_CONTINUE 1 |
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#define | IPR_RC_JOB_RETURN 2 |
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#define | IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 |
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#define | IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 |
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#define | IPR_IOASC_SYNC_REQUIRED 0x023f0000 |
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#define | IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 |
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#define | IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 |
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#define | IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 |
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#define | IPR_IOASC_IOASC_MASK 0xFFFFFF00 |
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#define | IPR_IOASC_SCSI_STATUS_MASK 0x000000FF |
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#define | IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 |
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#define | IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 |
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#define | IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 |
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#define | IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 |
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#define | IPR_IOASC_BUS_WAS_RESET 0x06290000 |
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#define | IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 |
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#define | IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 |
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#define | IPR_FIRST_DRIVER_IOASC 0x10000000 |
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#define | IPR_IOASC_IOA_WAS_RESET 0x10000001 |
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#define | IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 |
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#define | IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 |
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#define | IPR_USE_PCI_WARM_RESET 0x00000002 |
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#define | IPR_DEFAULT_MAX_ERROR_DUMP 984 |
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#define | IPR_NUM_LOG_HCAMS 2 |
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#define | IPR_NUM_CFG_CHG_HCAMS 2 |
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#define | IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) |
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#define | IPR_MAX_SIS64_TARGETS_PER_BUS 1024 |
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#define | IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff |
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#define | IPR_MAX_NUM_TARGETS_PER_BUS 256 |
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#define | IPR_MAX_NUM_LUNS_PER_TARGET 256 |
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#define | IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 |
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#define | IPR_VSET_BUS 0xff |
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#define | IPR_IOA_BUS 0xff |
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#define | IPR_IOA_TARGET 0xff |
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#define | IPR_IOA_LUN 0xff |
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#define | IPR_MAX_NUM_BUSES 16 |
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#define | IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES |
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#define | IPR_NUM_RESET_RELOAD_RETRIES 3 |
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#define | IPR_NUM_INTERNAL_CMD_BLKS |
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#define | IPR_MAX_COMMANDS 100 |
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#define | IPR_NUM_CMD_BLKS |
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#define | IPR_MAX_PHYSICAL_DEVS 192 |
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#define | IPR_DEFAULT_SIS64_DEVS 1024 |
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#define | IPR_MAX_SIS64_DEVS 4096 |
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#define | IPR_MAX_SGLIST 64 |
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#define | IPR_IOA_MAX_SECTORS 32767 |
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#define | IPR_VSET_MAX_SECTORS 512 |
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#define | IPR_MAX_CDB_LEN 16 |
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#define | IPR_MAX_HRRQ_RETRIES 3 |
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#define | IPR_DEFAULT_BUS_WIDTH 16 |
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#define | IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) |
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#define | IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) |
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#define | IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) |
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#define | IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) |
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#define | IPR_IOA_RES_HANDLE 0xffffffff |
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#define | IPR_INVALID_RES_HANDLE 0 |
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#define | IPR_IOA_RES_ADDR 0x00ffffff |
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#define | IPR_QUERY_RSRC_STATE 0xC2 |
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#define | IPR_RESET_DEVICE 0xC3 |
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#define | IPR_RESET_TYPE_SELECT 0x80 |
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#define | IPR_LUN_RESET 0x40 |
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#define | IPR_TARGET_RESET 0x20 |
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#define | IPR_BUS_RESET 0x10 |
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#define | IPR_ATA_PHY_RESET 0x80 |
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#define | IPR_ID_HOST_RR_Q 0xC4 |
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#define | IPR_QUERY_IOA_CONFIG 0xC5 |
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#define | IPR_CANCEL_ALL_REQUESTS 0xCE |
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#define | IPR_HOST_CONTROLLED_ASYNC 0xCF |
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#define | IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 |
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#define | IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 |
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#define | IPR_SET_SUPPORTED_DEVICES 0xFB |
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#define | IPR_SET_ALL_SUPPORTED_DEVICES 0x80 |
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#define | IPR_IOA_SHUTDOWN 0xF7 |
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#define | IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 |
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#define | IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) |
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#define | IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) |
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#define | IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) |
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#define | IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) |
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#define | IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
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#define | IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
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#define | IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
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#define | IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
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#define | IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ) |
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#define | IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) |
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#define | IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) |
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#define | IPR_OPERATIONAL_TIMEOUT (5 * 60) |
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#define | IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) |
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#define | IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) |
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#define | IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) |
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#define | IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) |
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#define | IPR_PCI_RESET_TIMEOUT (HZ / 2) |
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#define | IPR_SIS32_DUMP_TIMEOUT (15 * HZ) |
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#define | IPR_SIS64_DUMP_TIMEOUT (40 * HZ) |
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#define | IPR_DUMP_DELAY_SECONDS 4 |
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#define | IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ) |
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#define | IPR_VENDOR_ID_LEN 8 |
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#define | IPR_PROD_ID_LEN 16 |
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#define | IPR_SERIAL_NUM_LEN 8 |
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#define | IPR_FMT2_MBX_ADDR_MASK 0x0fffffff |
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#define | IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 |
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#define | IPR_FMT2_MKR_BAR_SEL_SHIFT 28 |
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#define | IPR_GET_FMT2_BAR_SEL(mbx) (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) |
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#define | IPR_SDT_FMT2_BAR0_SEL 0x0 |
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#define | IPR_SDT_FMT2_BAR1_SEL 0x1 |
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#define | IPR_SDT_FMT2_BAR2_SEL 0x2 |
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#define | IPR_SDT_FMT2_BAR3_SEL 0x3 |
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#define | IPR_SDT_FMT2_BAR4_SEL 0x4 |
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#define | IPR_SDT_FMT2_BAR5_SEL 0x5 |
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#define | IPR_SDT_FMT2_EXP_ROM_SEL 0x8 |
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#define | IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 |
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#define | IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 |
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#define | IPR_DOORBELL 0x82800000 |
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#define | IPR_RUNTIME_RESET 0x40000000 |
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#define | IPR_IPL_INIT_MIN_STAGE_TIME 5 |
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#define | IPR_IPL_INIT_DEFAULT_STAGE_TIME 15 |
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#define | IPR_IPL_INIT_STAGE_UNKNOWN 0x0 |
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#define | IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 |
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#define | IPR_IPL_INIT_STAGE_MASK 0xff000000 |
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#define | IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff |
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#define | IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) |
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#define | IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) |
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#define | IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) |
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#define | IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) |
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#define | IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) |
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#define | IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) |
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#define | IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) |
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#define | IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) |
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#define | IPR_PCII_MMIO_ERROR (0x80000000 >> 28) |
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#define | IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) |
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#define | IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) |
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#define | IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) |
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#define | IPR_PCII_ERROR_INTERRUPTS |
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#define | IPR_PCII_OPER_INTERRUPTS (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) |
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#define | IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) |
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#define | IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) |
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#define | IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23) |
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#define | IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ |
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#define | IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ |
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#define | IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) |
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#define | IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024) |
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#define | IPR_FMT2_NUM_SDT_ENTRIES 511 |
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#define | IPR_FMT3_NUM_SDT_ENTRIES 0xFFF |
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#define | IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) |
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#define | IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) |
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#define | IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST |
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#define | IPR_GET_PHYS_LOC(res_addr) (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) |
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#define | IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) |
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#define | IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) |
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#define | IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 |
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#define | IPR_IS_DASD_DEVICE(std_inq) |
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#define | IPR_IS_SES_DEVICE(std_inq) (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) |
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#define | IPR_RES_TYPE_AF_DASD 0x00 |
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#define | IPR_RES_TYPE_GENERIC_SCSI 0x01 |
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#define | IPR_RES_TYPE_VOLUME_SET 0x02 |
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#define | IPR_RES_TYPE_REMOTE_AF_DASD 0x03 |
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#define | IPR_RES_TYPE_GENERIC_ATA 0x04 |
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#define | IPR_RES_TYPE_ARRAY 0x05 |
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#define | IPR_RES_TYPE_IOAFP 0xff |
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#define | IPR_PROTO_SATA 0x02 |
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#define | IPR_PROTO_SATA_ATAPI 0x03 |
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#define | IPR_PROTO_SAS_STP 0x06 |
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#define | IPR_PROTO_SAS_STP_ATAPI 0x07 |
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#define | IPR_IS_IOA_RESOURCE 0x80 |
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#define | IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) |
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#define | IPR_QUEUE_FROZEN_MODEL 0 |
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#define | IPR_QUEUE_NACA_MODEL 1 |
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#define | IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) |
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#define | IPR_MAX_RES_PATH_LENGTH 24 |
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#define | IPR_UCODE_DOWNLOAD_REQ 0x10 |
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#define | IPR_RQTYPE_SCSICDB 0x00 |
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#define | IPR_RQTYPE_IOACMD 0x01 |
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#define | IPR_RQTYPE_HCAM 0x02 |
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#define | IPR_RQTYPE_ATA_PASSTHRU 0x04 |
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#define | IPR_FLAGS_HI_WRITE_NOT_READ 0x80 |
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#define | IPR_FLAGS_HI_NO_ULEN_CHK 0x20 |
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#define | IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 |
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#define | IPR_FLAGS_HI_SYNC_COMPLETE 0x08 |
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#define | IPR_FLAGS_HI_NO_LINK_DESC 0x04 |
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#define | IPR_FLAGS_LO_ALIGNED_BFR 0x20 |
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#define | IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 |
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#define | IPR_FLAGS_LO_UNTAGGED_TASK 0x00 |
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#define | IPR_FLAGS_LO_SIMPLE_TASK 0x02 |
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#define | IPR_FLAGS_LO_ORDERED_TASK 0x04 |
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#define | IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 |
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#define | IPR_FLAGS_LO_ACA_TASK 0x08 |
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#define | IPR_ATA_FLAG_PACKET_CMD 0x80 |
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#define | IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 |
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#define | IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 |
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#define | IPR_IOADL_FLAGS_MASK 0xff000000 |
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#define | IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) |
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#define | IPR_IOADL_DATA_LEN_MASK 0x00ffffff |
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#define | IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) |
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#define | IPR_IOADL_FLAGS_READ 0x48000000 |
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#define | IPR_IOADL_FLAGS_READ_LAST 0x49000000 |
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#define | IPR_IOADL_FLAGS_WRITE 0x68000000 |
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#define | IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 |
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#define | IPR_IOADL_FLAGS_LAST 0x01000000 |
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#define | IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) |
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#define | IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) |
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#define | IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) |
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#define | IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) |
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#define | IPR_NO_ILID 0 |
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#define | IPR_DRIVER_ILID 0xffffffff |
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#define | IPR_ADDITIONAL_STATUS_FMT 0x80000000 |
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#define | IPR_AUTOSENSE_VALID 0x40000000 |
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#define | IPR_ATA_DEVICE_WAS_RESET 0x20000000 |
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#define | IPR_IOASC_SPECIFIC_MASK 0x00ffffff |
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#define | IPR_FIELD_POINTER_VALID (0x80000000 >> 8) |
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#define | IPR_FIELD_POINTER_MASK 0x0000ffff |
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#define | IPR_MODE_PAGE_PS 0x80 |
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#define | IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) |
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#define | IPR_SCSI_ATTR_ENABLE_QAS 0x80 |
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#define | IPR_SCSI_ATTR_DISABLE_QAS 0x40 |
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#define | IPR_SCSI_ATTR_QAS_MASK 0xC0 |
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#define | IPR_SCSI_ATTR_ENABLE_TM 0x20 |
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#define | IPR_SCSI_ATTR_NO_TERM_PWR 0x10 |
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#define | IPR_SCSI_ATTR_TM_SUPPORTED 0x08 |
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#define | IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 |
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#define | IPR_EXTENDED_RESET_DELAY 7 |
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#define | IPR_ENABLE_DUAL_IOA_AF 0x80 |
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#define | IPR_CAP_DUAL_IOA_RAID 0x80 |
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#define | IPR_INQUIRY_PAGE0_ENTRIES 20 |
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#define | IPR_INVALID_ARRAY_DEV_NUM 0xff |
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#define | IPR_PATH_CFG_TYPE_MASK 0xF0 |
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#define | IPR_PATH_CFG_NOT_EXIST 0x00 |
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#define | IPR_PATH_CFG_IOA_PORT 0x10 |
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#define | IPR_PATH_CFG_EXP_PORT 0x20 |
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#define | IPR_PATH_CFG_DEVICE_PORT 0x30 |
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#define | IPR_PATH_CFG_DEVICE_LUN 0x40 |
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#define | IPR_PATH_CFG_STATUS_MASK 0x0F |
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#define | IPR_PATH_CFG_NO_PROB 0x00 |
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#define | IPR_PATH_CFG_DEGRADED 0x01 |
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#define | IPR_PATH_CFG_FAILED 0x02 |
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#define | IPR_PATH_CFG_SUSPECT 0x03 |
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#define | IPR_PATH_NOT_DETECTED 0x04 |
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#define | IPR_PATH_INCORRECT_CONN 0x05 |
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#define | IPR_PHY_LINK_RATE_MASK 0x0F |
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#define | IPR_DESCRIPTOR_MASK 0xC0 |
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#define | IPR_DESCRIPTOR_SIS64 0x00 |
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#define | IPR_PATH_ACTIVE_MASK 0xC0 |
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#define | IPR_PATH_NO_INFO 0x00 |
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#define | IPR_PATH_ACTIVE 0x40 |
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#define | IPR_PATH_NOT_ACTIVE 0x80 |
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#define | IPR_PATH_STATE_MASK 0x0F |
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#define | IPR_PATH_STATE_NO_INFO 0x00 |
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#define | IPR_PATH_HEALTHY 0x01 |
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#define | IPR_PATH_DEGRADED 0x02 |
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#define | IPR_PATH_FAILED 0x03 |
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#define | for_each_fabric_cfg(fabric, cfg) |
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#define | IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 |
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#define | IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 |
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#define | IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 |
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#define | IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 |
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#define | IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 |
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#define | IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 |
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#define | IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 |
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#define | IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 |
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#define | IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 |
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#define | IPR_HOSTRCB_INTERNAL_OPER 0x80 |
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#define | IPR_HOSTRCB_ERR_RESP_SENT 0x40 |
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#define | IPR_HOST_RCB_OVERLAY_ID_1 0x01 |
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#define | IPR_HOST_RCB_OVERLAY_ID_2 0x02 |
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#define | IPR_HOST_RCB_OVERLAY_ID_3 0x03 |
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#define | IPR_HOST_RCB_OVERLAY_ID_4 0x04 |
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#define | IPR_HOST_RCB_OVERLAY_ID_6 0x06 |
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#define | IPR_HOST_RCB_OVERLAY_ID_7 0x07 |
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#define | IPR_HOST_RCB_OVERLAY_ID_12 0x12 |
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#define | IPR_HOST_RCB_OVERLAY_ID_13 0x13 |
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#define | IPR_HOST_RCB_OVERLAY_ID_14 0x14 |
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#define | IPR_HOST_RCB_OVERLAY_ID_16 0x16 |
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#define | IPR_HOST_RCB_OVERLAY_ID_17 0x17 |
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#define | IPR_HOST_RCB_OVERLAY_ID_20 0x20 |
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#define | IPR_HOST_RCB_OVERLAY_ID_23 0x23 |
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#define | IPR_HOST_RCB_OVERLAY_ID_24 0x24 |
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#define | IPR_HOST_RCB_OVERLAY_ID_26 0x26 |
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#define | IPR_HOST_RCB_OVERLAY_ID_30 0x30 |
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#define | IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF |
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#define | IPR_SDT_ENDIAN 0x80 |
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#define | IPR_SDT_VALID_ENTRY 0x20 |
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#define | IPR_ARRAY_VIRTUAL_BUS 0x1 |
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#define | IPR_VSET_VIRTUAL_BUS 0x2 |
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#define | IPR_IOAFP_VIRTUAL_BUS 0x3 |
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#define | IPR_GET_RES_PHYS_LOC(res) (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) |
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#define | IPR_ENDIAN_SWAP_KEY 0x00080800 |
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#define | IPR_USE_LSI 0x00 |
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#define | IPR_USE_MSI 0x01 |
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#define | IPR_SIS32 0x00 |
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#define | IPR_SIS64 0x01 |
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#define | IPR_PCI_CFG 0x00 |
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#define | IPR_MMIO 0x01 |
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#define | IPR_TRACE_START 0x00 |
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#define | IPR_TRACE_FINISH 0xff |
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#define | IPR_EYECATCHER "iprcfg" |
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#define | IPR_MAX_LOG_LEVEL 4 |
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#define | IPR_DEFAULT_LOG_LEVEL 2 |
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#define | IPR_NUM_TRACE_INDEX_BITS 8 |
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#define | IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) |
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#define | IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) |
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#define | IPR_TRACE_START_LABEL "trace" |
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#define | IPR_FREEQ_LABEL "free-q" |
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#define | IPR_PENDQ_LABEL "pend-q" |
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#define | IPR_CFG_TBL_START "cfg" |
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#define | IPR_RES_TABLE_LABEL "res_tbl" |
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#define | IPR_HCAM_LABEL "hcams" |
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#define | IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc |
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#define | IPR_HRRQ_RESP_BIT_SET 0x00000002 |
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#define | IPR_HRRQ_TOGGLE_BIT 0x00000001 |
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#define | IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 |
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#define | IPR_CMD_LABEL "ipr_cmd" |
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#define | IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 |
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#define | IPR_DUMP_STATUS_SUCCESS 0 |
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#define | IPR_DUMP_STATUS_QUAL_SUCCESS 2 |
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#define | IPR_DUMP_STATUS_FAILED 0xffffffff |
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#define | IPR_DUMP_OS_LINUX 0x4C4E5558 |
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#define | IPR_DUMP_DRIVER_NAME 0x49505232 |
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#define | IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 |
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#define | IPR_DUMP_DATA_TYPE_ASCII 0x41534349 |
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#define | IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 |
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#define | IPR_DUMP_IOA_DUMP_ID 0x494F4131 |
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#define | IPR_DUMP_LOCATION_ID 0x4C4F4341 |
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#define | IPR_DUMP_TRACE_ID 0x54524143 |
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#define | IPR_DUMP_DRIVER_VERSION_ID 0x44525652 |
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#define | IPR_DUMP_DRIVER_TYPE_ID 0x54595045 |
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#define | IPR_DUMP_IOA_CTRL_BLK 0x494F4342 |
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#define | IPR_DUMP_PEND_OPS 0x414F5053 |
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#define | IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } |
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#define | ipr_create_trace_file(kobj, attr) 0 |
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#define | ipr_remove_trace_file(kobj, attr) do { } while(0) |
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#define | ipr_create_dump_file(kobj, attr) 0 |
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#define | ipr_remove_dump_file(kobj, attr) do { } while(0) |
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#define | ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) |
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#define | ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) |
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#define | ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) |
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#define | ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt,...) |
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#define | ipr_res_err(ioa_cfg, res, fmt,...) ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) |
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#define | ipr_ra_printk(level, ioa_cfg, ra, fmt,...) |
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#define | ipr_ra_err(ioa_cfg, ra, fmt,...) ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) |
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#define | ipr_phys_res_err(ioa_cfg, res, fmt,...) |
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#define | ipr_hcam_err(hostrcb, fmt,...) |
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#define | ipr_trace |
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#define | ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) |
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#define | LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) |
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#define | ipr_err_separator ipr_err("----------------------------------------------------------\n") |
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