Data Structures
struct	emif_regs

Macros
#define	EMIF_MAX_NUM_FREQUENCIES 6

#define	DDR_VOLTAGE_STABLE 0

#define	DDR_VOLTAGE_RAMPING 1

#define	EMIF_NORMAL_TIMINGS 0

#define	EMIF_DERATED_TIMINGS 1

#define	EMIF_READ_IDLE_LEN_VAL 5

#define	READ_IDLE_INTERVAL_DVFS (1*1000000)

#define	READ_IDLE_INTERVAL_NORMAL (50*1000000)

#define	DLL_CALIB_INTERVAL_DVFS (1*1000000)

#define	DLL_CALIB_ACK_WAIT_VAL 5

#define	EMIF_ZQCS_INTERVAL_US (50*1000)

#define	ZQ_SFEXITEN_ENABLE 1

#define	ZQ_DUALCALEN_DISABLE 0

#define	ZQ_DUALCALEN_ENABLE 1

#define	T_ZQCS_DEFAULT_NS 90

#define	T_ZQCL_DEFAULT_NS 360

#define	T_ZQINIT_DEFAULT_NS 1000

#define	DPD_DISABLE 0

#define	DPD_ENABLE 1

#define	EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048

#define	EMIF_LP_MODE_TIMEOUT_POWER 512

#define	EMIF_LP_MODE_FREQ_THRESHOLD 400000000

#define	EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000

#define	EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41

#define	EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80

#define	EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF

#define	EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200

#define	EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000

#define	TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360

#define	EMIF_T_CSTA 3

#define	EMIF_T_PDLL_UL 128

#define	EMIF_EXT_PHY_CTRL_1_VAL 0x04020080

#define	EMIF_EXT_PHY_CTRL_5_VAL 0x04010040

#define	EMIF_EXT_PHY_CTRL_6_VAL 0x01004010

#define	EMIF_EXT_PHY_CTRL_7_VAL 0x00001004

#define	EMIF_EXT_PHY_CTRL_8_VAL 0x04010040

#define	EMIF_EXT_PHY_CTRL_9_VAL 0x01004010

#define	EMIF_EXT_PHY_CTRL_10_VAL 0x00001004

#define	EMIF_EXT_PHY_CTRL_11_VAL 0x00000000

#define	EMIF_EXT_PHY_CTRL_12_VAL 0x00000000

#define	EMIF_EXT_PHY_CTRL_13_VAL 0x00000000

#define	EMIF_EXT_PHY_CTRL_14_VAL 0x80080080

#define	EMIF_EXT_PHY_CTRL_15_VAL 0x00800800

#define	EMIF_EXT_PHY_CTRL_16_VAL 0x08102040

#define	EMIF_EXT_PHY_CTRL_17_VAL 0x00000001

#define	EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150

#define	EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0

#define	EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540

#define	EMIF_EXT_PHY_CTRL_21_VAL 0x00000000

#define	EMIF_EXT_PHY_CTRL_22_VAL 0x00000000

#define	EMIF_EXT_PHY_CTRL_23_VAL 0x00000000

#define	EMIF_EXT_PHY_CTRL_24_VAL 0x00000077

#define	EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200

#define	EMIF_MODULE_ID_AND_REVISION 0x0000

#define	EMIF_STATUS 0x0004

#define	EMIF_SDRAM_CONFIG 0x0008

#define	EMIF_SDRAM_CONFIG_2 0x000c

#define	EMIF_SDRAM_REFRESH_CONTROL 0x0010

#define	EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014

#define	EMIF_SDRAM_TIMING_1 0x0018

#define	EMIF_SDRAM_TIMING_1_SHDW 0x001c

#define	EMIF_SDRAM_TIMING_2 0x0020

#define	EMIF_SDRAM_TIMING_2_SHDW 0x0024

#define	EMIF_SDRAM_TIMING_3 0x0028

#define	EMIF_SDRAM_TIMING_3_SHDW 0x002c

#define	EMIF_LPDDR2_NVM_TIMING 0x0030

#define	EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034

#define	EMIF_POWER_MANAGEMENT_CONTROL 0x0038

#define	EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c

#define	EMIF_LPDDR2_MODE_REG_DATA 0x0040

#define	EMIF_LPDDR2_MODE_REG_CONFIG 0x0050

#define	EMIF_OCP_CONFIG 0x0054

#define	EMIF_OCP_CONFIG_VALUE_1 0x0058

#define	EMIF_OCP_CONFIG_VALUE_2 0x005c

#define	EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060

#define	EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064

#define	EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068

#define	EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c

#define	EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070

#define	EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074

#define	EMIF_PERFORMANCE_COUNTER_1 0x0080

#define	EMIF_PERFORMANCE_COUNTER_2 0x0084

#define	EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088

#define	EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c

#define	EMIF_PERFORMANCE_COUNTER_TIME 0x0090

#define	EMIF_MISC_REG 0x0094

#define	EMIF_DLL_CALIB_CTRL 0x0098

#define	EMIF_DLL_CALIB_CTRL_SHDW 0x009c

#define	EMIF_END_OF_INTERRUPT 0x00a0

#define	EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4

#define	EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8

#define	EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac

#define	EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0

#define	EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4

#define	EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8

#define	EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc

#define	EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0

#define	EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8

#define	EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc

#define	EMIF_OCP_ERROR_LOG 0x00d0

#define	EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4

#define	EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8

#define	EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc

#define	EMIF_DDR_PHY_CTRL_1 0x00e4

#define	EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8

#define	EMIF_DDR_PHY_CTRL_2 0x00ec

#define	EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100

#define	EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104

#define	EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108

#define	EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120

#define	EMIF_COS_CONFIG 0x0124

#define	EMIF_PHY_STATUS_1 0x0140

#define	EMIF_PHY_STATUS_2 0x0144

#define	EMIF_PHY_STATUS_3 0x0148

#define	EMIF_PHY_STATUS_4 0x014c

#define	EMIF_PHY_STATUS_5 0x0150

#define	EMIF_PHY_STATUS_6 0x0154

#define	EMIF_PHY_STATUS_7 0x0158

#define	EMIF_PHY_STATUS_8 0x015c

#define	EMIF_PHY_STATUS_9 0x0160

#define	EMIF_PHY_STATUS_10 0x0164

#define	EMIF_PHY_STATUS_11 0x0168

#define	EMIF_PHY_STATUS_12 0x016c

#define	EMIF_PHY_STATUS_13 0x0170

#define	EMIF_PHY_STATUS_14 0x0174

#define	EMIF_PHY_STATUS_15 0x0178

#define	EMIF_PHY_STATUS_16 0x017c

#define	EMIF_PHY_STATUS_17 0x0180

#define	EMIF_PHY_STATUS_18 0x0184

#define	EMIF_PHY_STATUS_19 0x0188

#define	EMIF_PHY_STATUS_20 0x018c

#define	EMIF_PHY_STATUS_21 0x0190

#define	EMIF_EXT_PHY_CTRL_1 0x0200

#define	EMIF_EXT_PHY_CTRL_1_SHDW 0x0204

#define	EMIF_EXT_PHY_CTRL_2 0x0208

#define	EMIF_EXT_PHY_CTRL_2_SHDW 0x020c

#define	EMIF_EXT_PHY_CTRL_3 0x0210

#define	EMIF_EXT_PHY_CTRL_3_SHDW 0x0214

#define	EMIF_EXT_PHY_CTRL_4 0x0218

#define	EMIF_EXT_PHY_CTRL_4_SHDW 0x021c

#define	EMIF_EXT_PHY_CTRL_5 0x0220

#define	EMIF_EXT_PHY_CTRL_5_SHDW 0x0224

#define	EMIF_EXT_PHY_CTRL_6 0x0228

#define	EMIF_EXT_PHY_CTRL_6_SHDW 0x022c

#define	EMIF_EXT_PHY_CTRL_7 0x0230

#define	EMIF_EXT_PHY_CTRL_7_SHDW 0x0234

#define	EMIF_EXT_PHY_CTRL_8 0x0238

#define	EMIF_EXT_PHY_CTRL_8_SHDW 0x023c

#define	EMIF_EXT_PHY_CTRL_9 0x0240

#define	EMIF_EXT_PHY_CTRL_9_SHDW 0x0244

#define	EMIF_EXT_PHY_CTRL_10 0x0248

#define	EMIF_EXT_PHY_CTRL_10_SHDW 0x024c

#define	EMIF_EXT_PHY_CTRL_11 0x0250

#define	EMIF_EXT_PHY_CTRL_11_SHDW 0x0254

#define	EMIF_EXT_PHY_CTRL_12 0x0258

#define	EMIF_EXT_PHY_CTRL_12_SHDW 0x025c

#define	EMIF_EXT_PHY_CTRL_13 0x0260

#define	EMIF_EXT_PHY_CTRL_13_SHDW 0x0264

#define	EMIF_EXT_PHY_CTRL_14 0x0268

#define	EMIF_EXT_PHY_CTRL_14_SHDW 0x026c

#define	EMIF_EXT_PHY_CTRL_15 0x0270

#define	EMIF_EXT_PHY_CTRL_15_SHDW 0x0274

#define	EMIF_EXT_PHY_CTRL_16 0x0278

#define	EMIF_EXT_PHY_CTRL_16_SHDW 0x027c

#define	EMIF_EXT_PHY_CTRL_17 0x0280

#define	EMIF_EXT_PHY_CTRL_17_SHDW 0x0284

#define	EMIF_EXT_PHY_CTRL_18 0x0288

#define	EMIF_EXT_PHY_CTRL_18_SHDW 0x028c

#define	EMIF_EXT_PHY_CTRL_19 0x0290

#define	EMIF_EXT_PHY_CTRL_19_SHDW 0x0294

#define	EMIF_EXT_PHY_CTRL_20 0x0298

#define	EMIF_EXT_PHY_CTRL_20_SHDW 0x029c

#define	EMIF_EXT_PHY_CTRL_21 0x02a0

#define	EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4

#define	EMIF_EXT_PHY_CTRL_22 0x02a8

#define	EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac

#define	EMIF_EXT_PHY_CTRL_23 0x02b0

#define	EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4

#define	EMIF_EXT_PHY_CTRL_24 0x02b8

#define	EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc

#define	EMIF_EXT_PHY_CTRL_25 0x02c0

#define	EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4

#define	EMIF_EXT_PHY_CTRL_26 0x02c8

#define	EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc

#define	EMIF_EXT_PHY_CTRL_27 0x02d0

#define	EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4

#define	EMIF_EXT_PHY_CTRL_28 0x02d8

#define	EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc

#define	EMIF_EXT_PHY_CTRL_29 0x02e0

#define	EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4

#define	EMIF_EXT_PHY_CTRL_30 0x02e8

#define	EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec

#define	SCHEME_SHIFT 30

#define	SCHEME_MASK (0x3 << 30)

#define	MODULE_ID_SHIFT 16

#define	MODULE_ID_MASK (0xfff << 16)

#define	RTL_VERSION_SHIFT 11

#define	RTL_VERSION_MASK (0x1f << 11)

#define	MAJOR_REVISION_SHIFT 8

#define	MAJOR_REVISION_MASK (0x7 << 8)

#define	MINOR_REVISION_SHIFT 0

#define	MINOR_REVISION_MASK (0x3f << 0)

#define	BE_SHIFT 31

#define	BE_MASK (1 << 31)

#define	DUAL_CLK_MODE_SHIFT 30

#define	DUAL_CLK_MODE_MASK (1 << 30)

#define	FAST_INIT_SHIFT 29

#define	FAST_INIT_MASK (1 << 29)

#define	RDLVLGATETO_SHIFT 6

#define	RDLVLGATETO_MASK (1 << 6)

#define	RDLVLTO_SHIFT 5

#define	RDLVLTO_MASK (1 << 5)

#define	WRLVLTO_SHIFT 4

#define	WRLVLTO_MASK (1 << 4)

#define	PHY_DLL_READY_SHIFT 2

#define	PHY_DLL_READY_MASK (1 << 2)

#define	SDRAM_TYPE_SHIFT 29

#define	SDRAM_TYPE_MASK (0x7 << 29)

#define	IBANK_POS_SHIFT 27

#define	IBANK_POS_MASK (0x3 << 27)

#define	DDR_TERM_SHIFT 24

#define	DDR_TERM_MASK (0x7 << 24)

#define	DDR2_DDQS_SHIFT 23

#define	DDR2_DDQS_MASK (1 << 23)

#define	DYN_ODT_SHIFT 21

#define	DYN_ODT_MASK (0x3 << 21)

#define	DDR_DISABLE_DLL_SHIFT 20

#define	DDR_DISABLE_DLL_MASK (1 << 20)

#define	SDRAM_DRIVE_SHIFT 18

#define	SDRAM_DRIVE_MASK (0x3 << 18)

#define	CWL_SHIFT 16

#define	CWL_MASK (0x3 << 16)

#define	NARROW_MODE_SHIFT 14

#define	NARROW_MODE_MASK (0x3 << 14)

#define	CL_SHIFT 10

#define	CL_MASK (0xf << 10)

#define	ROWSIZE_SHIFT 7

#define	ROWSIZE_MASK (0x7 << 7)

#define	IBANK_SHIFT 4

#define	IBANK_MASK (0x7 << 4)

#define	EBANK_SHIFT 3

#define	EBANK_MASK (1 << 3)

#define	PAGESIZE_SHIFT 0

#define	PAGESIZE_MASK (0x7 << 0)

#define	CS1NVMEN_SHIFT 30

#define	CS1NVMEN_MASK (1 << 30)

#define	EBANK_POS_SHIFT 27

#define	EBANK_POS_MASK (1 << 27)

#define	RDBNUM_SHIFT 4

#define	RDBNUM_MASK (0x3 << 4)

#define	RDBSIZE_SHIFT 0

#define	RDBSIZE_MASK (0x7 << 0)

#define	INITREF_DIS_SHIFT 31

#define	INITREF_DIS_MASK (1 << 31)

#define	SRT_SHIFT 29

#define	SRT_MASK (1 << 29)

#define	ASR_SHIFT 28

#define	ASR_MASK (1 << 28)

#define	PASR_SHIFT 24

#define	PASR_MASK (0x7 << 24)

#define	REFRESH_RATE_SHIFT 0

#define	REFRESH_RATE_MASK (0xffff << 0)

#define	T_RTW_SHIFT 29

#define	T_RTW_MASK (0x7 << 29)

#define	T_RP_SHIFT 25

#define	T_RP_MASK (0xf << 25)

#define	T_RCD_SHIFT 21

#define	T_RCD_MASK (0xf << 21)

#define	T_WR_SHIFT 17

#define	T_WR_MASK (0xf << 17)

#define	T_RAS_SHIFT 12

#define	T_RAS_MASK (0x1f << 12)

#define	T_RC_SHIFT 6

#define	T_RC_MASK (0x3f << 6)

#define	T_RRD_SHIFT 3

#define	T_RRD_MASK (0x7 << 3)

#define	T_WTR_SHIFT 0

#define	T_WTR_MASK (0x7 << 0)

#define	T_XP_SHIFT 28

#define	T_XP_MASK (0x7 << 28)

#define	T_ODT_SHIFT 25

#define	T_ODT_MASK (0x7 << 25)

#define	T_XSNR_SHIFT 16

#define	T_XSNR_MASK (0x1ff << 16)

#define	T_XSRD_SHIFT 6

#define	T_XSRD_MASK (0x3ff << 6)

#define	T_RTP_SHIFT 3

#define	T_RTP_MASK (0x7 << 3)

#define	T_CKE_SHIFT 0

#define	T_CKE_MASK (0x7 << 0)

#define	T_PDLL_UL_SHIFT 28

#define	T_PDLL_UL_MASK (0xf << 28)

#define	T_CSTA_SHIFT 24

#define	T_CSTA_MASK (0xf << 24)

#define	T_CKESR_SHIFT 21

#define	T_CKESR_MASK (0x7 << 21)

#define	ZQ_ZQCS_SHIFT 15

#define	ZQ_ZQCS_MASK (0x3f << 15)

#define	T_TDQSCKMAX_SHIFT 13

#define	T_TDQSCKMAX_MASK (0x3 << 13)

#define	T_RFC_SHIFT 4

#define	T_RFC_MASK (0x1ff << 4)

#define	T_RAS_MAX_SHIFT 0

#define	T_RAS_MAX_MASK (0xf << 0)

#define	PD_TIM_SHIFT 12

#define	PD_TIM_MASK (0xf << 12)

#define	DPD_EN_SHIFT 11

#define	DPD_EN_MASK (1 << 11)

#define	LP_MODE_SHIFT 8

#define	LP_MODE_MASK (0x7 << 8)

#define	SR_TIM_SHIFT 4

#define	SR_TIM_MASK (0xf << 4)

#define	CS_TIM_SHIFT 0

#define	CS_TIM_MASK (0xf << 0)

#define	VALUE_0_SHIFT 0

#define	VALUE_0_MASK (0x7f << 0)

#define	CS_SHIFT 31

#define	CS_MASK (1 << 31)

#define	REFRESH_EN_SHIFT 30

#define	REFRESH_EN_MASK (1 << 30)

#define	ADDRESS_SHIFT 0

#define	ADDRESS_MASK (0xff << 0)

#define	SYS_THRESH_MAX_SHIFT 24

#define	SYS_THRESH_MAX_MASK (0xf << 24)

#define	MPU_THRESH_MAX_SHIFT 20

#define	MPU_THRESH_MAX_MASK (0xf << 20)

#define	LL_THRESH_MAX_SHIFT 16

#define	LL_THRESH_MAX_MASK (0xf << 16)

#define	COUNTER1_SHIFT 0

#define	COUNTER1_MASK (0xffffffff << 0)

#define	COUNTER2_SHIFT 0

#define	COUNTER2_MASK (0xffffffff << 0)

#define	CNTR2_MCONNID_EN_SHIFT 31

#define	CNTR2_MCONNID_EN_MASK (1 << 31)

#define	CNTR2_REGION_EN_SHIFT 30

#define	CNTR2_REGION_EN_MASK (1 << 30)

#define	CNTR2_CFG_SHIFT 16

#define	CNTR2_CFG_MASK (0xf << 16)

#define	CNTR1_MCONNID_EN_SHIFT 15

#define	CNTR1_MCONNID_EN_MASK (1 << 15)

#define	CNTR1_REGION_EN_SHIFT 14

#define	CNTR1_REGION_EN_MASK (1 << 14)

#define	CNTR1_CFG_SHIFT 0

#define	CNTR1_CFG_MASK (0xf << 0)

#define	MCONNID2_SHIFT 24

#define	MCONNID2_MASK (0xff << 24)

#define	REGION_SEL2_SHIFT 16

#define	REGION_SEL2_MASK (0x3 << 16)

#define	MCONNID1_SHIFT 8

#define	MCONNID1_MASK (0xff << 8)

#define	REGION_SEL1_SHIFT 0

#define	REGION_SEL1_MASK (0x3 << 0)

#define	TOTAL_TIME_SHIFT 0

#define	TOTAL_TIME_MASK (0xffffffff << 0)

#define	ACK_WAIT_SHIFT 16

#define	ACK_WAIT_MASK (0xf << 16)

#define	DLL_CALIB_INTERVAL_SHIFT 0

#define	DLL_CALIB_INTERVAL_MASK (0x1ff << 0)

#define	EOI_SHIFT 0

#define	EOI_MASK (1 << 0)

#define	DNV_SYS_SHIFT 2

#define	DNV_SYS_MASK (1 << 2)

#define	TA_SYS_SHIFT 1

#define	TA_SYS_MASK (1 << 1)

#define	ERR_SYS_SHIFT 0

#define	ERR_SYS_MASK (1 << 0)

#define	DNV_LL_SHIFT 2

#define	DNV_LL_MASK (1 << 2)

#define	TA_LL_SHIFT 1

#define	TA_LL_MASK (1 << 1)

#define	ERR_LL_SHIFT 0

#define	ERR_LL_MASK (1 << 0)

#define	EN_DNV_SYS_SHIFT 2

#define	EN_DNV_SYS_MASK (1 << 2)

#define	EN_TA_SYS_SHIFT 1

#define	EN_TA_SYS_MASK (1 << 1)

#define	EN_ERR_SYS_SHIFT 0

#define	EN_ERR_SYS_MASK (1 << 0)

#define	EN_DNV_LL_SHIFT 2

#define	EN_DNV_LL_MASK (1 << 2)

#define	EN_TA_LL_SHIFT 1

#define	EN_TA_LL_MASK (1 << 1)

#define	EN_ERR_LL_SHIFT 0

#define	EN_ERR_LL_MASK (1 << 0)

#define	ZQ_CS1EN_SHIFT 31

#define	ZQ_CS1EN_MASK (1 << 31)

#define	ZQ_CS0EN_SHIFT 30

#define	ZQ_CS0EN_MASK (1 << 30)

#define	ZQ_DUALCALEN_SHIFT 29

#define	ZQ_DUALCALEN_MASK (1 << 29)

#define	ZQ_SFEXITEN_SHIFT 28

#define	ZQ_SFEXITEN_MASK (1 << 28)

#define	ZQ_ZQINIT_MULT_SHIFT 18

#define	ZQ_ZQINIT_MULT_MASK (0x3 << 18)

#define	ZQ_ZQCL_MULT_SHIFT 16

#define	ZQ_ZQCL_MULT_MASK (0x3 << 16)

#define	ZQ_REFINTERVAL_SHIFT 0

#define	ZQ_REFINTERVAL_MASK (0xffff << 0)

#define	TA_CS1EN_SHIFT 31

#define	TA_CS1EN_MASK (1 << 31)

#define	TA_CS0EN_SHIFT 30

#define	TA_CS0EN_MASK (1 << 30)

#define	TA_SFEXITEN_SHIFT 28

#define	TA_SFEXITEN_MASK (1 << 28)

#define	TA_DEVWDT_SHIFT 26

#define	TA_DEVWDT_MASK (0x3 << 26)

#define	TA_DEVCNT_SHIFT 24

#define	TA_DEVCNT_MASK (0x3 << 24)

#define	TA_REFINTERVAL_SHIFT 0

#define	TA_REFINTERVAL_MASK (0x3fffff << 0)

#define	MADDRSPACE_SHIFT 14

#define	MADDRSPACE_MASK (0x3 << 14)

#define	MBURSTSEQ_SHIFT 11

#define	MBURSTSEQ_MASK (0x7 << 11)

#define	MCMD_SHIFT 8

#define	MCMD_MASK (0x7 << 8)

#define	MCONNID_SHIFT 0

#define	MCONNID_MASK (0xff << 0)

#define	DLL_SLAVE_DLY_CTRL_SHIFT_4D 4

#define	DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)

#define	READ_LATENCY_SHIFT_4D 0

#define	READ_LATENCY_MASK_4D (0xf << 0)

#define	DLL_HALF_DELAY_SHIFT_4D5 21

#define	DLL_HALF_DELAY_MASK_4D5 (1 << 21)

#define	READ_LATENCY_SHIFT_4D5 0

#define	READ_LATENCY_MASK_4D5 (0x1f << 0)

#define	DDR_PHY_CTRL_1_SHDW_SHIFT 5

#define	DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)

#define	READ_LATENCY_SHDW_SHIFT 0

#define	READ_LATENCY_SHDW_MASK (0x1f << 0)

Macro Definition Documentation

#define ACK_WAIT_MASK (0xf << 16)

Definition at line 460 of file emif.h.

#define ACK_WAIT_SHIFT 16

Definition at line 459 of file emif.h.

#define ADDRESS_MASK (0xff << 0)

Definition at line 412 of file emif.h.

#define ADDRESS_SHIFT 0

Definition at line 411 of file emif.h.

#define ASR_MASK (1 << 28)

Definition at line 336 of file emif.h.

#define ASR_SHIFT 28

Definition at line 335 of file emif.h.

#define BE_MASK (1 << 31)

Definition at line 276 of file emif.h.

#define BE_SHIFT 31

Definition at line 275 of file emif.h.

#define CL_MASK (0xf << 10)

Definition at line 310 of file emif.h.

#define CL_SHIFT 10

Definition at line 309 of file emif.h.

#define CNTR1_CFG_MASK (0xf << 0)

Definition at line 442 of file emif.h.

#define CNTR1_CFG_SHIFT 0

Definition at line 441 of file emif.h.

#define CNTR1_MCONNID_EN_MASK (1 << 15)

Definition at line 438 of file emif.h.

#define CNTR1_MCONNID_EN_SHIFT 15

Definition at line 437 of file emif.h.

#define CNTR1_REGION_EN_MASK (1 << 14)

Definition at line 440 of file emif.h.

#define CNTR1_REGION_EN_SHIFT 14

Definition at line 439 of file emif.h.

#define CNTR2_CFG_MASK (0xf << 16)

Definition at line 436 of file emif.h.

#define CNTR2_CFG_SHIFT 16

Definition at line 435 of file emif.h.

#define CNTR2_MCONNID_EN_MASK (1 << 31)

Definition at line 432 of file emif.h.

#define CNTR2_MCONNID_EN_SHIFT 31

Definition at line 431 of file emif.h.

#define CNTR2_REGION_EN_MASK (1 << 30)

Definition at line 434 of file emif.h.

#define CNTR2_REGION_EN_SHIFT 30

Definition at line 433 of file emif.h.

#define COUNTER1_MASK (0xffffffff << 0)

Definition at line 424 of file emif.h.

#define COUNTER1_SHIFT 0

Definition at line 423 of file emif.h.

#define COUNTER2_MASK (0xffffffff << 0)

Definition at line 428 of file emif.h.

#define COUNTER2_SHIFT 0

Definition at line 427 of file emif.h.

#define CS1NVMEN_MASK (1 << 30)

Definition at line 322 of file emif.h.

#define CS1NVMEN_SHIFT 30

Definition at line 321 of file emif.h.

#define CS_MASK (1 << 31)

Definition at line 408 of file emif.h.

#define CS_SHIFT 31

Definition at line 407 of file emif.h.

#define CS_TIM_MASK (0xf << 0)

Definition at line 400 of file emif.h.

#define CS_TIM_SHIFT 0

Definition at line 399 of file emif.h.

#define CWL_MASK (0x3 << 16)

Definition at line 306 of file emif.h.

#define CWL_SHIFT 16

Definition at line 305 of file emif.h.

#define DDR2_DDQS_MASK (1 << 23)

Definition at line 298 of file emif.h.

#define DDR2_DDQS_SHIFT 23

Definition at line 297 of file emif.h.

#define DDR_DISABLE_DLL_MASK (1 << 20)

Definition at line 302 of file emif.h.

#define DDR_DISABLE_DLL_SHIFT 20

Definition at line 301 of file emif.h.

#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)

Definition at line 554 of file emif.h.

#define DDR_PHY_CTRL_1_SHDW_SHIFT 5

Definition at line 553 of file emif.h.

#define DDR_TERM_MASK (0x7 << 24)

Definition at line 296 of file emif.h.

#define DDR_TERM_SHIFT 24

Definition at line 295 of file emif.h.

#define DDR_VOLTAGE_RAMPING 1

Definition at line 24 of file emif.h.

#define DDR_VOLTAGE_STABLE 0

Definition at line 23 of file emif.h.

#define DLL_CALIB_ACK_WAIT_VAL 5

Definition at line 48 of file emif.h.

#define DLL_CALIB_INTERVAL_DVFS (1*1000000)

Definition at line 46 of file emif.h.

#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)

Definition at line 462 of file emif.h.

#define DLL_CALIB_INTERVAL_SHIFT 0

Definition at line 461 of file emif.h.

#define DLL_HALF_DELAY_MASK_4D5 (1 << 21)

Definition at line 548 of file emif.h.

#define DLL_HALF_DELAY_SHIFT_4D5 21

Definition at line 547 of file emif.h.

#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)

Definition at line 542 of file emif.h.

#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4

Definition at line 541 of file emif.h.

#define DNV_LL_MASK (1 << 2)

Definition at line 478 of file emif.h.

#define DNV_LL_SHIFT 2

Definition at line 477 of file emif.h.

#define DNV_SYS_MASK (1 << 2)

Definition at line 470 of file emif.h.

#define DNV_SYS_SHIFT 2

Definition at line 469 of file emif.h.

#define DPD_DISABLE 0

Definition at line 66 of file emif.h.

#define DPD_EN_MASK (1 << 11)

Definition at line 394 of file emif.h.

#define DPD_EN_SHIFT 11

Definition at line 393 of file emif.h.

#define DPD_ENABLE 1

Definition at line 67 of file emif.h.

#define DUAL_CLK_MODE_MASK (1 << 30)

Definition at line 278 of file emif.h.

#define DUAL_CLK_MODE_SHIFT 30

Definition at line 277 of file emif.h.

#define DYN_ODT_MASK (0x3 << 21)

Definition at line 300 of file emif.h.

#define DYN_ODT_SHIFT 21

Definition at line 299 of file emif.h.

#define EBANK_MASK (1 << 3)

Definition at line 316 of file emif.h.

#define EBANK_POS_MASK (1 << 27)

Definition at line 324 of file emif.h.

#define EBANK_POS_SHIFT 27

Definition at line 323 of file emif.h.

#define EBANK_SHIFT 3

Definition at line 315 of file emif.h.

#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104

Definition at line 174 of file emif.h.

#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108

Definition at line 175 of file emif.h.

#define EMIF_COS_CONFIG 0x0124

Definition at line 177 of file emif.h.

#define EMIF_DDR_PHY_CTRL_1 0x00e4

Definition at line 170 of file emif.h.

#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000

Definition at line 79 of file emif.h.

#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200

Definition at line 85 of file emif.h.

#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8

Definition at line 171 of file emif.h.

#define EMIF_DDR_PHY_CTRL_2 0x00ec

Definition at line 172 of file emif.h.

#define EMIF_DERATED_TIMINGS 1

Definition at line 28 of file emif.h.

#define EMIF_DLL_CALIB_CTRL 0x0098

Definition at line 153 of file emif.h.

#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c

Definition at line 154 of file emif.h.

#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF

Definition at line 82 of file emif.h.

#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80

Definition at line 81 of file emif.h.

#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41

Definition at line 80 of file emif.h.

#define EMIF_END_OF_INTERRUPT 0x00a0

Definition at line 155 of file emif.h.

#define EMIF_EXT_PHY_CTRL_1 0x0200

Definition at line 199 of file emif.h.

#define EMIF_EXT_PHY_CTRL_10 0x0248

Definition at line 217 of file emif.h.

#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c

Definition at line 218 of file emif.h.

#define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004

Definition at line 101 of file emif.h.

#define EMIF_EXT_PHY_CTRL_11 0x0250

Definition at line 219 of file emif.h.

#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254

Definition at line 220 of file emif.h.

#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000

Definition at line 102 of file emif.h.

#define EMIF_EXT_PHY_CTRL_12 0x0258

Definition at line 221 of file emif.h.

#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c

Definition at line 222 of file emif.h.

#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000

Definition at line 103 of file emif.h.

#define EMIF_EXT_PHY_CTRL_13 0x0260

Definition at line 223 of file emif.h.

#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264

Definition at line 224 of file emif.h.

#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000

Definition at line 104 of file emif.h.

#define EMIF_EXT_PHY_CTRL_14 0x0268

Definition at line 225 of file emif.h.

#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c

Definition at line 226 of file emif.h.

#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080

Definition at line 105 of file emif.h.

#define EMIF_EXT_PHY_CTRL_15 0x0270

Definition at line 227 of file emif.h.

#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274

Definition at line 228 of file emif.h.

#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800

Definition at line 106 of file emif.h.

#define EMIF_EXT_PHY_CTRL_16 0x0278

Definition at line 229 of file emif.h.

#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c

Definition at line 230 of file emif.h.

#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040

Definition at line 107 of file emif.h.

#define EMIF_EXT_PHY_CTRL_17 0x0280

Definition at line 231 of file emif.h.

#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284

Definition at line 232 of file emif.h.

#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001

Definition at line 108 of file emif.h.

#define EMIF_EXT_PHY_CTRL_18 0x0288

Definition at line 233 of file emif.h.

#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c

Definition at line 234 of file emif.h.

#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150

Definition at line 109 of file emif.h.

#define EMIF_EXT_PHY_CTRL_19 0x0290

Definition at line 235 of file emif.h.

#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294

Definition at line 236 of file emif.h.

#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0

Definition at line 110 of file emif.h.

#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204

Definition at line 200 of file emif.h.

#define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080

Definition at line 95 of file emif.h.

#define EMIF_EXT_PHY_CTRL_2 0x0208

Definition at line 201 of file emif.h.

#define EMIF_EXT_PHY_CTRL_20 0x0298

Definition at line 237 of file emif.h.

#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c

Definition at line 238 of file emif.h.

#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540

Definition at line 111 of file emif.h.

#define EMIF_EXT_PHY_CTRL_21 0x02a0

Definition at line 239 of file emif.h.

#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4

Definition at line 240 of file emif.h.

#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000

Definition at line 112 of file emif.h.

#define EMIF_EXT_PHY_CTRL_22 0x02a8

Definition at line 241 of file emif.h.

#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac

Definition at line 242 of file emif.h.

#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000

Definition at line 113 of file emif.h.

#define EMIF_EXT_PHY_CTRL_23 0x02b0

Definition at line 243 of file emif.h.

#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4

Definition at line 244 of file emif.h.

#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000

Definition at line 114 of file emif.h.

#define EMIF_EXT_PHY_CTRL_24 0x02b8

Definition at line 245 of file emif.h.

#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc

Definition at line 246 of file emif.h.

#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077

Definition at line 115 of file emif.h.

#define EMIF_EXT_PHY_CTRL_25 0x02c0

Definition at line 247 of file emif.h.

#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4

Definition at line 248 of file emif.h.

#define EMIF_EXT_PHY_CTRL_26 0x02c8

Definition at line 249 of file emif.h.

#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc

Definition at line 250 of file emif.h.

#define EMIF_EXT_PHY_CTRL_27 0x02d0

Definition at line 251 of file emif.h.

#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4

Definition at line 252 of file emif.h.

#define EMIF_EXT_PHY_CTRL_28 0x02d8

Definition at line 253 of file emif.h.

#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc

Definition at line 254 of file emif.h.

#define EMIF_EXT_PHY_CTRL_29 0x02e0

Definition at line 255 of file emif.h.

#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4

Definition at line 256 of file emif.h.

#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c

Definition at line 202 of file emif.h.

#define EMIF_EXT_PHY_CTRL_3 0x0210

Definition at line 203 of file emif.h.

#define EMIF_EXT_PHY_CTRL_30 0x02e8

Definition at line 257 of file emif.h.

#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec

Definition at line 258 of file emif.h.

#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214

Definition at line 204 of file emif.h.

#define EMIF_EXT_PHY_CTRL_4 0x0218

Definition at line 205 of file emif.h.

#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c

Definition at line 206 of file emif.h.

#define EMIF_EXT_PHY_CTRL_5 0x0220

Definition at line 207 of file emif.h.

#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224

Definition at line 208 of file emif.h.

#define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040

Definition at line 96 of file emif.h.

#define EMIF_EXT_PHY_CTRL_6 0x0228

Definition at line 209 of file emif.h.

#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c

Definition at line 210 of file emif.h.

#define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010

Definition at line 97 of file emif.h.

#define EMIF_EXT_PHY_CTRL_7 0x0230

Definition at line 211 of file emif.h.

#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234

Definition at line 212 of file emif.h.

#define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004

Definition at line 98 of file emif.h.

#define EMIF_EXT_PHY_CTRL_8 0x0238

Definition at line 213 of file emif.h.

#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c

Definition at line 214 of file emif.h.

#define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040

Definition at line 99 of file emif.h.

#define EMIF_EXT_PHY_CTRL_9 0x0240

Definition at line 215 of file emif.h.

#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244

Definition at line 216 of file emif.h.

#define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010

Definition at line 100 of file emif.h.

#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200

Definition at line 117 of file emif.h.

#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068

Definition at line 143 of file emif.h.

#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064

Definition at line 142 of file emif.h.

#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c

Definition at line 144 of file emif.h.

#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070

Definition at line 145 of file emif.h.

#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074

Definition at line 146 of file emif.h.

#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060

Definition at line 141 of file emif.h.

#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0

Definition at line 163 of file emif.h.

#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8

Definition at line 161 of file emif.h.

#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8

Definition at line 157 of file emif.h.

#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0

Definition at line 159 of file emif.h.

#define EMIF_LP_MODE_FREQ_THRESHOLD 400000000

Definition at line 76 of file emif.h.

#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048

Definition at line 74 of file emif.h.

#define EMIF_LP_MODE_TIMEOUT_POWER 512

Definition at line 75 of file emif.h.

#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050

Definition at line 137 of file emif.h.

#define EMIF_LPDDR2_MODE_REG_DATA 0x0040

Definition at line 136 of file emif.h.

#define EMIF_LPDDR2_NVM_TIMING 0x0030

Definition at line 132 of file emif.h.

#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034

Definition at line 133 of file emif.h.

#define EMIF_MAX_NUM_FREQUENCIES 6

Definition at line 20 of file emif.h.

#define EMIF_MISC_REG 0x0094

Definition at line 152 of file emif.h.

#define EMIF_MODULE_ID_AND_REVISION 0x0000

Definition at line 120 of file emif.h.

#define EMIF_NORMAL_TIMINGS 0

Definition at line 27 of file emif.h.

#define EMIF_OCP_CONFIG 0x0054

Definition at line 138 of file emif.h.

#define EMIF_OCP_CONFIG_VALUE_1 0x0058

Definition at line 139 of file emif.h.

#define EMIF_OCP_CONFIG_VALUE_2 0x005c

Definition at line 140 of file emif.h.

#define EMIF_OCP_ERROR_LOG 0x00d0

Definition at line 166 of file emif.h.

#define EMIF_PERFORMANCE_COUNTER_1 0x0080

Definition at line 147 of file emif.h.

#define EMIF_PERFORMANCE_COUNTER_2 0x0084

Definition at line 148 of file emif.h.

#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088

Definition at line 149 of file emif.h.

#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c

Definition at line 150 of file emif.h.

#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090

Definition at line 151 of file emif.h.

#define EMIF_PHY_STATUS_1 0x0140

Definition at line 178 of file emif.h.

#define EMIF_PHY_STATUS_10 0x0164

Definition at line 187 of file emif.h.

#define EMIF_PHY_STATUS_11 0x0168

Definition at line 188 of file emif.h.

#define EMIF_PHY_STATUS_12 0x016c

Definition at line 189 of file emif.h.

#define EMIF_PHY_STATUS_13 0x0170

Definition at line 190 of file emif.h.

#define EMIF_PHY_STATUS_14 0x0174

Definition at line 191 of file emif.h.

#define EMIF_PHY_STATUS_15 0x0178

Definition at line 192 of file emif.h.

#define EMIF_PHY_STATUS_16 0x017c

Definition at line 193 of file emif.h.

#define EMIF_PHY_STATUS_17 0x0180

Definition at line 194 of file emif.h.

#define EMIF_PHY_STATUS_18 0x0184

Definition at line 195 of file emif.h.

#define EMIF_PHY_STATUS_19 0x0188

Definition at line 196 of file emif.h.

#define EMIF_PHY_STATUS_2 0x0144

Definition at line 179 of file emif.h.

#define EMIF_PHY_STATUS_20 0x018c

Definition at line 197 of file emif.h.

#define EMIF_PHY_STATUS_21 0x0190

Definition at line 198 of file emif.h.

#define EMIF_PHY_STATUS_3 0x0148

Definition at line 180 of file emif.h.

#define EMIF_PHY_STATUS_4 0x014c

Definition at line 181 of file emif.h.

#define EMIF_PHY_STATUS_5 0x0150

Definition at line 182 of file emif.h.

#define EMIF_PHY_STATUS_6 0x0154

Definition at line 183 of file emif.h.

#define EMIF_PHY_STATUS_7 0x0158

Definition at line 184 of file emif.h.

#define EMIF_PHY_STATUS_8 0x015c

Definition at line 185 of file emif.h.

#define EMIF_PHY_STATUS_9 0x0160

Definition at line 186 of file emif.h.

#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000

Definition at line 86 of file emif.h.

#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038

Definition at line 134 of file emif.h.

#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c

Definition at line 135 of file emif.h.

#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100

Definition at line 173 of file emif.h.

#define EMIF_READ_IDLE_LEN_VAL 5

Definition at line 31 of file emif.h.

#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120

Definition at line 176 of file emif.h.

#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc

Definition at line 169 of file emif.h.

#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8

Definition at line 168 of file emif.h.

#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4

Definition at line 167 of file emif.h.

#define EMIF_SDRAM_CONFIG 0x0008

Definition at line 122 of file emif.h.

#define EMIF_SDRAM_CONFIG_2 0x000c

Definition at line 123 of file emif.h.

#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8

Definition at line 164 of file emif.h.

#define EMIF_SDRAM_REFRESH_CONTROL 0x0010

Definition at line 124 of file emif.h.

#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014

Definition at line 125 of file emif.h.

#define EMIF_SDRAM_TIMING_1 0x0018

Definition at line 126 of file emif.h.

#define EMIF_SDRAM_TIMING_1_SHDW 0x001c

Definition at line 127 of file emif.h.

#define EMIF_SDRAM_TIMING_2 0x0020

Definition at line 128 of file emif.h.

#define EMIF_SDRAM_TIMING_2_SHDW 0x0024

Definition at line 129 of file emif.h.

#define EMIF_SDRAM_TIMING_3 0x0028

Definition at line 130 of file emif.h.

#define EMIF_SDRAM_TIMING_3_SHDW 0x002c

Definition at line 131 of file emif.h.

#define EMIF_STATUS 0x0004

Definition at line 121 of file emif.h.

#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc

Definition at line 162 of file emif.h.

#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4

Definition at line 160 of file emif.h.

#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4

Definition at line 156 of file emif.h.

#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac

Definition at line 158 of file emif.h.

#define EMIF_T_CSTA 3

Definition at line 91 of file emif.h.

#define EMIF_T_PDLL_UL 128

Definition at line 92 of file emif.h.

#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc

Definition at line 165 of file emif.h.

#define EMIF_ZQCS_INTERVAL_US (50*1000)

Definition at line 51 of file emif.h.

#define EN_DNV_LL_MASK (1 << 2)

Definition at line 494 of file emif.h.

#define EN_DNV_LL_SHIFT 2

Definition at line 493 of file emif.h.

#define EN_DNV_SYS_MASK (1 << 2)

Definition at line 486 of file emif.h.

#define EN_DNV_SYS_SHIFT 2

Definition at line 485 of file emif.h.

#define EN_ERR_LL_MASK (1 << 0)

Definition at line 498 of file emif.h.

#define EN_ERR_LL_SHIFT 0

Definition at line 497 of file emif.h.

#define EN_ERR_SYS_MASK (1 << 0)

Definition at line 490 of file emif.h.

#define EN_ERR_SYS_SHIFT 0

Definition at line 489 of file emif.h.

#define EN_TA_LL_MASK (1 << 1)

Definition at line 496 of file emif.h.

#define EN_TA_LL_SHIFT 1

Definition at line 495 of file emif.h.

#define EN_TA_SYS_MASK (1 << 1)

Definition at line 488 of file emif.h.

#define EN_TA_SYS_SHIFT 1

Definition at line 487 of file emif.h.

#define EOI_MASK (1 << 0)

Definition at line 466 of file emif.h.

#define EOI_SHIFT 0

Definition at line 465 of file emif.h.

#define ERR_LL_MASK (1 << 0)

Definition at line 482 of file emif.h.

#define ERR_LL_SHIFT 0

Definition at line 481 of file emif.h.

#define ERR_SYS_MASK (1 << 0)

Definition at line 474 of file emif.h.

#define ERR_SYS_SHIFT 0

Definition at line 473 of file emif.h.

#define FAST_INIT_MASK (1 << 29)

Definition at line 280 of file emif.h.

#define FAST_INIT_SHIFT 29

Definition at line 279 of file emif.h.

#define IBANK_MASK (0x7 << 4)

Definition at line 314 of file emif.h.

#define IBANK_POS_MASK (0x3 << 27)

Definition at line 294 of file emif.h.

#define IBANK_POS_SHIFT 27

Definition at line 293 of file emif.h.

#define IBANK_SHIFT 4

Definition at line 313 of file emif.h.

#define INITREF_DIS_MASK (1 << 31)

Definition at line 332 of file emif.h.

#define INITREF_DIS_SHIFT 31

Definition at line 331 of file emif.h.

#define LL_THRESH_MAX_MASK (0xf << 16)

Definition at line 420 of file emif.h.

#define LL_THRESH_MAX_SHIFT 16

Definition at line 419 of file emif.h.

#define LP_MODE_MASK (0x7 << 8)

Definition at line 396 of file emif.h.

#define LP_MODE_SHIFT 8

Definition at line 395 of file emif.h.

#define MADDRSPACE_MASK (0x3 << 14)

Definition at line 532 of file emif.h.

#define MADDRSPACE_SHIFT 14

Definition at line 531 of file emif.h.

#define MAJOR_REVISION_MASK (0x7 << 8)

Definition at line 270 of file emif.h.

#define MAJOR_REVISION_SHIFT 8

Definition at line 269 of file emif.h.

#define MBURSTSEQ_MASK (0x7 << 11)

Definition at line 534 of file emif.h.

#define MBURSTSEQ_SHIFT 11

Definition at line 533 of file emif.h.

#define MCMD_MASK (0x7 << 8)

Definition at line 536 of file emif.h.

#define MCMD_SHIFT 8

Definition at line 535 of file emif.h.

#define MCONNID1_MASK (0xff << 8)

Definition at line 450 of file emif.h.

#define MCONNID1_SHIFT 8

Definition at line 449 of file emif.h.

#define MCONNID2_MASK (0xff << 24)

Definition at line 446 of file emif.h.

#define MCONNID2_SHIFT 24

Definition at line 445 of file emif.h.

#define MCONNID_MASK (0xff << 0)

Definition at line 538 of file emif.h.

#define MCONNID_SHIFT 0

Definition at line 537 of file emif.h.

#define MINOR_REVISION_MASK (0x3f << 0)

Definition at line 272 of file emif.h.

#define MINOR_REVISION_SHIFT 0

Definition at line 271 of file emif.h.

#define MODULE_ID_MASK (0xfff << 16)

Definition at line 266 of file emif.h.

#define MODULE_ID_SHIFT 16

Definition at line 265 of file emif.h.

#define MPU_THRESH_MAX_MASK (0xf << 20)

Definition at line 418 of file emif.h.

#define MPU_THRESH_MAX_SHIFT 20

Definition at line 417 of file emif.h.

#define NARROW_MODE_MASK (0x3 << 14)

Definition at line 308 of file emif.h.

#define NARROW_MODE_SHIFT 14

Definition at line 307 of file emif.h.

#define PAGESIZE_MASK (0x7 << 0)

Definition at line 318 of file emif.h.

#define PAGESIZE_SHIFT 0

Definition at line 317 of file emif.h.

#define PASR_MASK (0x7 << 24)

Definition at line 338 of file emif.h.

#define PASR_SHIFT 24

Definition at line 337 of file emif.h.

#define PD_TIM_MASK (0xf << 12)

Definition at line 392 of file emif.h.

#define PD_TIM_SHIFT 12

Definition at line 391 of file emif.h.

#define PHY_DLL_READY_MASK (1 << 2)

Definition at line 288 of file emif.h.

#define PHY_DLL_READY_SHIFT 2

Definition at line 287 of file emif.h.

#define RDBNUM_MASK (0x3 << 4)

Definition at line 326 of file emif.h.

#define RDBNUM_SHIFT 4

Definition at line 325 of file emif.h.

#define RDBSIZE_MASK (0x7 << 0)

Definition at line 328 of file emif.h.

#define RDBSIZE_SHIFT 0

Definition at line 327 of file emif.h.

#define RDLVLGATETO_MASK (1 << 6)

Definition at line 282 of file emif.h.

#define RDLVLGATETO_SHIFT 6

Definition at line 281 of file emif.h.

#define RDLVLTO_MASK (1 << 5)

Definition at line 284 of file emif.h.

#define RDLVLTO_SHIFT 5

Definition at line 283 of file emif.h.

#define READ_IDLE_INTERVAL_DVFS (1*1000000)

Definition at line 37 of file emif.h.

#define READ_IDLE_INTERVAL_NORMAL (50*1000000)

Definition at line 43 of file emif.h.

#define READ_LATENCY_MASK_4D (0xf << 0)

Definition at line 544 of file emif.h.

#define READ_LATENCY_MASK_4D5 (0x1f << 0)

Definition at line 550 of file emif.h.

#define READ_LATENCY_SHDW_MASK (0x1f << 0)

Definition at line 556 of file emif.h.

#define READ_LATENCY_SHDW_SHIFT 0

Definition at line 555 of file emif.h.

#define READ_LATENCY_SHIFT_4D 0

Definition at line 543 of file emif.h.

#define READ_LATENCY_SHIFT_4D5 0

Definition at line 549 of file emif.h.

#define REFRESH_EN_MASK (1 << 30)

Definition at line 410 of file emif.h.

#define REFRESH_EN_SHIFT 30

Definition at line 409 of file emif.h.

#define REFRESH_RATE_MASK (0xffff << 0)

Definition at line 340 of file emif.h.

#define REFRESH_RATE_SHIFT 0

Definition at line 339 of file emif.h.

#define REGION_SEL1_MASK (0x3 << 0)

Definition at line 452 of file emif.h.

#define REGION_SEL1_SHIFT 0

Definition at line 451 of file emif.h.

#define REGION_SEL2_MASK (0x3 << 16)

Definition at line 448 of file emif.h.

#define REGION_SEL2_SHIFT 16

Definition at line 447 of file emif.h.

#define ROWSIZE_MASK (0x7 << 7)

Definition at line 312 of file emif.h.

#define ROWSIZE_SHIFT 7

Definition at line 311 of file emif.h.

#define RTL_VERSION_MASK (0x1f << 11)

Definition at line 268 of file emif.h.

#define RTL_VERSION_SHIFT 11

Definition at line 267 of file emif.h.

#define SCHEME_MASK (0x3 << 30)

Definition at line 264 of file emif.h.

#define SCHEME_SHIFT 30

Definition at line 263 of file emif.h.

#define SDRAM_DRIVE_MASK (0x3 << 18)

Definition at line 304 of file emif.h.

#define SDRAM_DRIVE_SHIFT 18

Definition at line 303 of file emif.h.

#define SDRAM_TYPE_MASK (0x7 << 29)

Definition at line 292 of file emif.h.

#define SDRAM_TYPE_SHIFT 29

Definition at line 291 of file emif.h.

#define SR_TIM_MASK (0xf << 4)

Definition at line 398 of file emif.h.

#define SR_TIM_SHIFT 4

Definition at line 397 of file emif.h.

#define SRT_MASK (1 << 29)

Definition at line 334 of file emif.h.

#define SRT_SHIFT 29

Definition at line 333 of file emif.h.

#define SYS_THRESH_MAX_MASK (0xf << 24)

Definition at line 416 of file emif.h.

#define SYS_THRESH_MAX_SHIFT 24

Definition at line 415 of file emif.h.

#define T_CKE_MASK (0x7 << 0)

Definition at line 372 of file emif.h.

#define T_CKE_SHIFT 0

Definition at line 371 of file emif.h.

#define T_CKESR_MASK (0x7 << 21)

Definition at line 380 of file emif.h.

#define T_CKESR_SHIFT 21

Definition at line 379 of file emif.h.

#define T_CSTA_MASK (0xf << 24)

Definition at line 378 of file emif.h.

#define T_CSTA_SHIFT 24

Definition at line 377 of file emif.h.

#define T_ODT_MASK (0x7 << 25)

Definition at line 364 of file emif.h.

#define T_ODT_SHIFT 25

Definition at line 363 of file emif.h.

#define T_PDLL_UL_MASK (0xf << 28)

Definition at line 376 of file emif.h.

#define T_PDLL_UL_SHIFT 28

Definition at line 375 of file emif.h.

#define T_RAS_MASK (0x1f << 12)

Definition at line 352 of file emif.h.

#define T_RAS_MAX_MASK (0xf << 0)

Definition at line 388 of file emif.h.

#define T_RAS_MAX_SHIFT 0

Definition at line 387 of file emif.h.

#define T_RAS_SHIFT 12

Definition at line 351 of file emif.h.

#define T_RC_MASK (0x3f << 6)

Definition at line 354 of file emif.h.

#define T_RC_SHIFT 6

Definition at line 353 of file emif.h.

#define T_RCD_MASK (0xf << 21)

Definition at line 348 of file emif.h.

#define T_RCD_SHIFT 21

Definition at line 347 of file emif.h.

#define T_RFC_MASK (0x1ff << 4)

Definition at line 386 of file emif.h.

#define T_RFC_SHIFT 4

Definition at line 385 of file emif.h.

#define T_RP_MASK (0xf << 25)

Definition at line 346 of file emif.h.

#define T_RP_SHIFT 25

Definition at line 345 of file emif.h.

#define T_RRD_MASK (0x7 << 3)

Definition at line 356 of file emif.h.

#define T_RRD_SHIFT 3

Definition at line 355 of file emif.h.

#define T_RTP_MASK (0x7 << 3)

Definition at line 370 of file emif.h.

#define T_RTP_SHIFT 3

Definition at line 369 of file emif.h.

#define T_RTW_MASK (0x7 << 29)

Definition at line 344 of file emif.h.

#define T_RTW_SHIFT 29

Definition at line 343 of file emif.h.

#define T_TDQSCKMAX_MASK (0x3 << 13)

Definition at line 384 of file emif.h.

#define T_TDQSCKMAX_SHIFT 13

Definition at line 383 of file emif.h.

#define T_WR_MASK (0xf << 17)

Definition at line 350 of file emif.h.

#define T_WR_SHIFT 17

Definition at line 349 of file emif.h.

#define T_WTR_MASK (0x7 << 0)

Definition at line 358 of file emif.h.

#define T_WTR_SHIFT 0

Definition at line 357 of file emif.h.

#define T_XP_MASK (0x7 << 28)

Definition at line 362 of file emif.h.

#define T_XP_SHIFT 28

Definition at line 361 of file emif.h.

#define T_XSNR_MASK (0x1ff << 16)

Definition at line 366 of file emif.h.

#define T_XSNR_SHIFT 16

Definition at line 365 of file emif.h.

#define T_XSRD_MASK (0x3ff << 6)

Definition at line 368 of file emif.h.

#define T_XSRD_SHIFT 6

Definition at line 367 of file emif.h.

#define T_ZQCL_DEFAULT_NS 360

Definition at line 62 of file emif.h.

#define T_ZQCS_DEFAULT_NS 90

Definition at line 61 of file emif.h.

#define T_ZQINIT_DEFAULT_NS 1000

Definition at line 63 of file emif.h.

#define TA_CS0EN_MASK (1 << 30)

Definition at line 520 of file emif.h.

#define TA_CS0EN_SHIFT 30

Definition at line 519 of file emif.h.

#define TA_CS1EN_MASK (1 << 31)

Definition at line 518 of file emif.h.

#define TA_CS1EN_SHIFT 31

Definition at line 517 of file emif.h.

#define TA_DEVCNT_MASK (0x3 << 24)

Definition at line 526 of file emif.h.

#define TA_DEVCNT_SHIFT 24

Definition at line 525 of file emif.h.

#define TA_DEVWDT_MASK (0x3 << 26)

Definition at line 524 of file emif.h.

#define TA_DEVWDT_SHIFT 26

Definition at line 523 of file emif.h.

#define TA_LL_MASK (1 << 1)

Definition at line 480 of file emif.h.

#define TA_LL_SHIFT 1

Definition at line 479 of file emif.h.

#define TA_REFINTERVAL_MASK (0x3fffff << 0)

Definition at line 528 of file emif.h.

#define TA_REFINTERVAL_SHIFT 0

Definition at line 527 of file emif.h.

#define TA_SFEXITEN_MASK (1 << 28)

Definition at line 522 of file emif.h.

#define TA_SFEXITEN_SHIFT 28

Definition at line 521 of file emif.h.

#define TA_SYS_MASK (1 << 1)

Definition at line 472 of file emif.h.

#define TA_SYS_SHIFT 1

Definition at line 471 of file emif.h.

#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360

Definition at line 89 of file emif.h.

#define TOTAL_TIME_MASK (0xffffffff << 0)

Definition at line 456 of file emif.h.

#define TOTAL_TIME_SHIFT 0

Definition at line 455 of file emif.h.

#define VALUE_0_MASK (0x7f << 0)

Definition at line 404 of file emif.h.

#define VALUE_0_SHIFT 0

Definition at line 403 of file emif.h.

#define WRLVLTO_MASK (1 << 4)

Definition at line 286 of file emif.h.

#define WRLVLTO_SHIFT 4

Definition at line 285 of file emif.h.

#define ZQ_CS0EN_MASK (1 << 30)

Definition at line 504 of file emif.h.

#define ZQ_CS0EN_SHIFT 30

Definition at line 503 of file emif.h.

#define ZQ_CS1EN_MASK (1 << 31)

Definition at line 502 of file emif.h.

#define ZQ_CS1EN_SHIFT 31

Definition at line 501 of file emif.h.

#define ZQ_DUALCALEN_DISABLE 0

Definition at line 58 of file emif.h.

#define ZQ_DUALCALEN_ENABLE 1

Definition at line 59 of file emif.h.

#define ZQ_DUALCALEN_MASK (1 << 29)

Definition at line 506 of file emif.h.

#define ZQ_DUALCALEN_SHIFT 29

Definition at line 505 of file emif.h.

#define ZQ_REFINTERVAL_MASK (0xffff << 0)

Definition at line 514 of file emif.h.

#define ZQ_REFINTERVAL_SHIFT 0

Definition at line 513 of file emif.h.

#define ZQ_SFEXITEN_ENABLE 1

Definition at line 53 of file emif.h.

#define ZQ_SFEXITEN_MASK (1 << 28)

Definition at line 508 of file emif.h.

#define ZQ_SFEXITEN_SHIFT 28

Definition at line 507 of file emif.h.

#define ZQ_ZQCL_MULT_MASK (0x3 << 16)

Definition at line 512 of file emif.h.

#define ZQ_ZQCL_MULT_SHIFT 16

Definition at line 511 of file emif.h.

#define ZQ_ZQCS_MASK (0x3f << 15)

Definition at line 382 of file emif.h.

#define ZQ_ZQCS_SHIFT 15

Definition at line 381 of file emif.h.

#define ZQ_ZQINIT_MULT_MASK (0x3 << 18)

Definition at line 510 of file emif.h.

#define ZQ_ZQINIT_MULT_SHIFT 18

Definition at line 509 of file emif.h.

Data Structures

Macros

Macro Definition Documentation