35 nv50_disp_sclass[] = {
49 if (chan->
vblank.crtc != crtc)
52 if (nv_device(priv)->
chipset >= 0xc0) {
53 nv_wr32(priv, 0x001718, 0x80000000 | chan->
vblank.channel);
55 nv_wr32(priv, 0x06000c,
57 nv_wr32(priv, 0x060010,
59 nv_wr32(priv, 0x060014, chan->
vblank.value);
61 nv_wr32(priv, 0x001704, chan->
vblank.channel);
62 nv_wr32(priv, 0x001710, 0x80000000 | chan->
vblank.ctxdma);
64 if (nv_device(priv)->
chipset == 0x50) {
65 nv_wr32(priv, 0x001570, chan->
vblank.offset);
66 nv_wr32(priv, 0x001574, chan->
vblank.value);
68 nv_wr32(priv, 0x060010, chan->
vblank.offset);
69 nv_wr32(priv, 0x060014, chan->
vblank.value);
77 spin_unlock_irqrestore(&disp->
vblank.lock, flags);
87 u32 stat1 = nv_rd32(priv, 0x610024);
89 if (stat1 & 0x00000004) {
90 nv50_disp_intr_vblank(priv, 0);
91 nv_wr32(priv, 0x610024, 0x00000004);
95 if (stat1 & 0x00000008) {
96 nv50_disp_intr_vblank(priv, 1);
97 nv_wr32(priv, 0x610024, 0x00000008);
113 *pobject = nv_object(priv);
117 nv_engine(priv)->sclass = nv50_disp_sclass;
118 nv_subdev(priv)->intr = nv50_disp_intr;
120 INIT_LIST_HEAD(&priv->
base.vblank.list);
129 .ctor = nv50_disp_ctor,