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et131x.h
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1 /*
2  * Copyright © 2005 Agere Systems Inc.
3  * All rights reserved.
4  * http://www.agere.com
5  *
6  * SOFTWARE LICENSE
7  *
8  * This software is provided subject to the following terms and conditions,
9  * which you should read carefully before using the software. Using this
10  * software indicates your acceptance of these terms and conditions. If you do
11  * not agree with these terms and conditions, do not use the software.
12  *
13  * Copyright © 2005 Agere Systems Inc.
14  * All rights reserved.
15  *
16  * Redistribution and use in source or binary forms, with or without
17  * modifications, are permitted provided that the following conditions are met:
18  *
19  * . Redistributions of source code must retain the above copyright notice, this
20  * list of conditions and the following Disclaimer as comments in the code as
21  * well as in the documentation and/or other materials provided with the
22  * distribution.
23  *
24  * . Redistributions in binary form must reproduce the above copyright notice,
25  * this list of conditions and the following Disclaimer in the documentation
26  * and/or other materials provided with the distribution.
27  *
28  * . Neither the name of Agere Systems Inc. nor the names of the contributors
29  * may be used to endorse or promote products derived from this software
30  * without specific prior written permission.
31  *
32  * Disclaimer
33  *
34  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
35  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
36  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
37  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
38  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
39  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
42  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
43  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
44  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
45  * DAMAGE.
46  *
47  */
48 
49 #define DRIVER_NAME "et131x"
50 #define DRIVER_VERSION "v2.0"
51 
52 /* EEPROM registers */
53 
54 /* LBCIF Register Groups (addressed via 32-bit offsets) */
55 #define LBCIF_DWORD0_GROUP 0xAC
56 #define LBCIF_DWORD1_GROUP 0xB0
57 
58 /* LBCIF Registers (addressed via 8-bit offsets) */
59 #define LBCIF_ADDRESS_REGISTER 0xAC
60 #define LBCIF_DATA_REGISTER 0xB0
61 #define LBCIF_CONTROL_REGISTER 0xB1
62 #define LBCIF_STATUS_REGISTER 0xB2
63 
64 /* LBCIF Control Register Bits */
65 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
66 #define LBCIF_CONTROL_PAGE_WRITE 0x02
67 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
68 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
69 #define LBCIF_CONTROL_I2C_WRITE 0x40
70 #define LBCIF_CONTROL_LBCIF_ENABLE 0x80
71 
72 /* LBCIF Status Register Bits */
73 #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
74 #define LBCIF_STATUS_I2C_IDLE 0x02
75 #define LBCIF_STATUS_ACK_ERROR 0x04
76 #define LBCIF_STATUS_GENERAL_ERROR 0x08
77 #define LBCIF_STATUS_CHECKSUM_ERROR 0x40
78 #define LBCIF_STATUS_EEPROM_PRESENT 0x80
79 
80 /* START OF GLOBAL REGISTER ADDRESS MAP */
81 
82 /*
83  * 10bit registers
84  *
85  * Tx queue start address reg in global address map at address 0x0000
86  * tx queue end address reg in global address map at address 0x0004
87  * rx queue start address reg in global address map at address 0x0008
88  * rx queue end address reg in global address map at address 0x000C
89  */
90 
91 /*
92  * structure for power management control status reg in global address map
93  * located at address 0x0010
94  * jagcore_rx_rdy bit 9
95  * jagcore_tx_rdy bit 8
96  * phy_lped_en bit 7
97  * phy_sw_coma bit 6
98  * rxclk_gate bit 5
99  * txclk_gate bit 4
100  * sysclk_gate bit 3
101  * jagcore_rx_en bit 2
102  * jagcore_tx_en bit 1
103  * gigephy_en bit 0
104  */
105 
106 #define ET_PM_PHY_SW_COMA 0x40
107 #define ET_PMCSR_INIT 0x38
108 
109 /*
110  * Interrupt status reg at address 0x0018
111  */
112 
113 #define ET_INTR_TXDMA_ISR 0x00000008
114 #define ET_INTR_TXDMA_ERR 0x00000010
115 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
116 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
117 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
118 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
119 #define ET_INTR_RXDMA_ERR 0x00000200
120 #define ET_INTR_WATCHDOG 0x00004000
121 #define ET_INTR_WOL 0x00008000
122 #define ET_INTR_PHY 0x00010000
123 #define ET_INTR_TXMAC 0x00020000
124 #define ET_INTR_RXMAC 0x00040000
125 #define ET_INTR_MAC_STAT 0x00080000
126 #define ET_INTR_SLV_TIMEOUT 0x00100000
127 
128 /*
129  * Interrupt mask register at address 0x001C
130  * Interrupt alias clear mask reg at address 0x0020
131  * Interrupt status alias reg at address 0x0024
132  *
133  * Same masks as above
134  */
135 
136 /*
137  * Software reset reg at address 0x0028
138  * 0: txdma_sw_reset
139  * 1: rxdma_sw_reset
140  * 2: txmac_sw_reset
141  * 3: rxmac_sw_reset
142  * 4: mac_sw_reset
143  * 5: mac_stat_sw_reset
144  * 6: mmc_sw_reset
145  *31: selfclr_disable
146  */
147 
148 /*
149  * SLV Timer reg at address 0x002C (low 24 bits)
150  */
151 
152 /*
153  * MSI Configuration reg at address 0x0030
154  */
155 
156 #define ET_MSI_VECTOR 0x0000001F
157 #define ET_MSI_TC 0x00070000
158 
159 /*
160  * Loopback reg located at address 0x0034
161  */
162 
163 #define ET_LOOP_MAC 0x00000001
164 #define ET_LOOP_DMA 0x00000002
165 
166 /*
167  * GLOBAL Module of JAGCore Address Mapping
168  * Located at address 0x0000
169  */
170 struct global_regs { /* Location: */
171  u32 txq_start_addr; /* 0x0000 */
172  u32 txq_end_addr; /* 0x0004 */
173  u32 rxq_start_addr; /* 0x0008 */
174  u32 rxq_end_addr; /* 0x000C */
175  u32 pm_csr; /* 0x0010 */
176  u32 unused; /* 0x0014 */
177  u32 int_status; /* 0x0018 */
178  u32 int_mask; /* 0x001C */
179  u32 int_alias_clr_en; /* 0x0020 */
180  u32 int_status_alias; /* 0x0024 */
181  u32 sw_reset; /* 0x0028 */
182  u32 slv_timer; /* 0x002C */
183  u32 msi_config; /* 0x0030 */
184  u32 loopback; /* 0x0034 */
185  u32 watchdog_timer; /* 0x0038 */
186 };
187 
188 
189 /* START OF TXDMA REGISTER ADDRESS MAP */
190 
191 /*
192  * txdma control status reg at address 0x1000
193  */
194 
195 #define ET_TXDMA_CSR_HALT 0x00000001
196 #define ET_TXDMA_DROP_TLP 0x00000002
197 #define ET_TXDMA_CACHE_THRS 0x000000F0
198 #define ET_TXDMA_CACHE_SHIFT 4
199 #define ET_TXDMA_SNGL_EPKT 0x00000100
200 #define ET_TXDMA_CLASS 0x00001E00
201 
202 /*
203  * structure for txdma packet ring base address hi reg in txdma address map
204  * located at address 0x1004
205  * Defined earlier (u32)
206  */
207 
208 /*
209  * structure for txdma packet ring base address low reg in txdma address map
210  * located at address 0x1008
211  * Defined earlier (u32)
212  */
213 
214 /*
215  * structure for txdma packet ring number of descriptor reg in txdma address
216  * map. Located at address 0x100C
217  *
218  * 31-10: unused
219  * 9-0: pr ndes
220  */
221 
222 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
223 #define ET_DMA12_WRAP 0x1000
224 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
225 #define ET_DMA10_WRAP 0x0400
226 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
227 #define ET_DMA4_WRAP 0x0010
228 
229 #define INDEX12(x) ((x) & ET_DMA12_MASK)
230 #define INDEX10(x) ((x) & ET_DMA10_MASK)
231 #define INDEX4(x) ((x) & ET_DMA4_MASK)
232 
233 /*
234  * 10bit DMA with wrap
235  * txdma tx queue write address reg in txdma address map at 0x1010
236  * txdma tx queue write address external reg in txdma address map at 0x1014
237  * txdma tx queue read address reg in txdma address map at 0x1018
238  *
239  * u32
240  * txdma status writeback address hi reg in txdma address map at0x101C
241  * txdma status writeback address lo reg in txdma address map at 0x1020
242  *
243  * 10bit DMA with wrap
244  * txdma service request reg in txdma address map at 0x1024
245  * structure for txdma service complete reg in txdma address map at 0x1028
246  *
247  * 4bit DMA with wrap
248  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
249  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
250  *
251  * txdma error reg in txdma address map at address 0x1034
252  * 0: PyldResend
253  * 1: PyldRewind
254  * 4: DescrResend
255  * 5: DescrRewind
256  * 8: WrbkResend
257  * 9: WrbkRewind
258  */
259 
260 /*
261  * Tx DMA Module of JAGCore Address Mapping
262  * Located at address 0x1000
263  */
264 struct txdma_regs { /* Location: */
265  u32 csr; /* 0x1000 */
266  u32 pr_base_hi; /* 0x1004 */
267  u32 pr_base_lo; /* 0x1008 */
268  u32 pr_num_des; /* 0x100C */
269  u32 txq_wr_addr; /* 0x1010 */
270  u32 txq_wr_addr_ext; /* 0x1014 */
271  u32 txq_rd_addr; /* 0x1018 */
272  u32 dma_wb_base_hi; /* 0x101C */
273  u32 dma_wb_base_lo; /* 0x1020 */
274  u32 service_request; /* 0x1024 */
275  u32 service_complete; /* 0x1028 */
276  u32 cache_rd_index; /* 0x102C */
277  u32 cache_wr_index; /* 0x1030 */
278  u32 tx_dma_error; /* 0x1034 */
279  u32 desc_abort_cnt; /* 0x1038 */
280  u32 payload_abort_cnt; /* 0x103c */
281  u32 writeback_abort_cnt; /* 0x1040 */
282  u32 desc_timeout_cnt; /* 0x1044 */
283  u32 payload_timeout_cnt; /* 0x1048 */
284  u32 writeback_timeout_cnt; /* 0x104c */
285  u32 desc_error_cnt; /* 0x1050 */
286  u32 payload_error_cnt; /* 0x1054 */
287  u32 writeback_error_cnt; /* 0x1058 */
288  u32 dropped_tlp_cnt; /* 0x105c */
289  u32 new_service_complete; /* 0x1060 */
290  u32 ethernet_packet_cnt; /* 0x1064 */
291 };
292 
293 /* END OF TXDMA REGISTER ADDRESS MAP */
294 
295 
296 /* START OF RXDMA REGISTER ADDRESS MAP */
297 
298 /*
299  * structure for control status reg in rxdma address map
300  * Located at address 0x2000
301  *
302  * CSR
303  * 0: halt
304  * 1-3: tc
305  * 4: fbr_big_endian
306  * 5: psr_big_endian
307  * 6: pkt_big_endian
308  * 7: dma_big_endian
309  * 8-9: fbr0_size
310  * 10: fbr0_enable
311  * 11-12: fbr1_size
312  * 13: fbr1_enable
313  * 14: unused
314  * 15: pkt_drop_disable
315  * 16: pkt_done_flush
316  * 17: halt_status
317  * 18-31: unused
318  */
319 
320 
321 /*
322  * structure for dma writeback lo reg in rxdma address map
323  * located at address 0x2004
324  * Defined earlier (u32)
325  */
326 
327 /*
328  * structure for dma writeback hi reg in rxdma address map
329  * located at address 0x2008
330  * Defined earlier (u32)
331  */
332 
333 /*
334  * structure for number of packets done reg in rxdma address map
335  * located at address 0x200C
336  *
337  * 31-8: unused
338  * 7-0: num done
339  */
340 
341 /*
342  * structure for max packet time reg in rxdma address map
343  * located at address 0x2010
344  *
345  * 31-18: unused
346  * 17-0: time done
347  */
348 
349 /*
350  * structure for rx queue read address reg in rxdma address map
351  * located at address 0x2014
352  * Defined earlier (u32)
353  */
354 
355 /*
356  * structure for rx queue read address external reg in rxdma address map
357  * located at address 0x2018
358  * Defined earlier (u32)
359  */
360 
361 /*
362  * structure for rx queue write address reg in rxdma address map
363  * located at address 0x201C
364  * Defined earlier (u32)
365  */
366 
367 /*
368  * structure for packet status ring base address lo reg in rxdma address map
369  * located at address 0x2020
370  * Defined earlier (u32)
371  */
372 
373 /*
374  * structure for packet status ring base address hi reg in rxdma address map
375  * located at address 0x2024
376  * Defined earlier (u32)
377  */
378 
379 /*
380  * structure for packet status ring number of descriptors reg in rxdma address
381  * map. Located at address 0x2028
382  *
383  * 31-12: unused
384  * 11-0: psr ndes
385  */
386 
387 /*
388  * structure for packet status ring available offset reg in rxdma address map
389  * located at address 0x202C
390  *
391  * 31-13: unused
392  * 12: psr avail wrap
393  * 11-0: psr avail
394  */
395 
396 /*
397  * structure for packet status ring full offset reg in rxdma address map
398  * located at address 0x2030
399  *
400  * 31-13: unused
401  * 12: psr full wrap
402  * 11-0: psr full
403  */
404 
405 /*
406  * structure for packet status ring access index reg in rxdma address map
407  * located at address 0x2034
408  *
409  * 31-5: unused
410  * 4-0: psr_ai
411  */
412 
413 /*
414  * structure for packet status ring minimum descriptors reg in rxdma address
415  * map. Located at address 0x2038
416  *
417  * 31-12: unused
418  * 11-0: psr_min
419  */
420 
421 /*
422  * structure for free buffer ring base lo address reg in rxdma address map
423  * located at address 0x203C
424  * Defined earlier (u32)
425  */
426 
427 /*
428  * structure for free buffer ring base hi address reg in rxdma address map
429  * located at address 0x2040
430  * Defined earlier (u32)
431  */
432 
433 /*
434  * structure for free buffer ring number of descriptors reg in rxdma address
435  * map. Located at address 0x2044
436  *
437  * 31-10: unused
438  * 9-0: fbr ndesc
439  */
440 
441 /*
442  * structure for free buffer ring 0 available offset reg in rxdma address map
443  * located at address 0x2048
444  * Defined earlier (u32)
445  */
446 
447 /*
448  * structure for free buffer ring 0 full offset reg in rxdma address map
449  * located at address 0x204C
450  * Defined earlier (u32)
451  */
452 
453 /*
454  * structure for free buffer cache 0 full offset reg in rxdma address map
455  * located at address 0x2050
456  *
457  * 31-5: unused
458  * 4-0: fbc rdi
459  */
460 
461 /*
462  * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
463  * located at address 0x2054
464  *
465  * 31-10: unused
466  * 9-0: fbr min
467  */
468 
469 /*
470  * structure for free buffer ring 1 base address lo reg in rxdma address map
471  * located at address 0x2058 - 0x205C
472  * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
473  */
474 
475 /*
476  * structure for free buffer ring 1 number of descriptors reg in rxdma address
477  * map. Located at address 0x2060
478  * Defined earlier (RXDMA_FBR_NUM_DES_t)
479  */
480 
481 /*
482  * structure for free buffer ring 1 available offset reg in rxdma address map
483  * located at address 0x2064
484  * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
485  */
486 
487 /*
488  * structure for free buffer ring 1 full offset reg in rxdma address map
489  * located at address 0x2068
490  * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
491  */
492 
493 /*
494  * structure for free buffer cache 1 read index reg in rxdma address map
495  * located at address 0x206C
496  * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
497  */
498 
499 /*
500  * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
501  * located at address 0x2070
502  * Defined Earlier (RXDMA_FBR_MIN_DES_t)
503  */
504 
505 /*
506  * Rx DMA Module of JAGCore Address Mapping
507  * Located at address 0x2000
508  */
509 struct rxdma_regs { /* Location: */
510  u32 csr; /* 0x2000 */
511  u32 dma_wb_base_lo; /* 0x2004 */
512  u32 dma_wb_base_hi; /* 0x2008 */
513  u32 num_pkt_done; /* 0x200C */
514  u32 max_pkt_time; /* 0x2010 */
515  u32 rxq_rd_addr; /* 0x2014 */
516  u32 rxq_rd_addr_ext; /* 0x2018 */
517  u32 rxq_wr_addr; /* 0x201C */
518  u32 psr_base_lo; /* 0x2020 */
519  u32 psr_base_hi; /* 0x2024 */
520  u32 psr_num_des; /* 0x2028 */
521  u32 psr_avail_offset; /* 0x202C */
522  u32 psr_full_offset; /* 0x2030 */
523  u32 psr_access_index; /* 0x2034 */
524  u32 psr_min_des; /* 0x2038 */
525  u32 fbr0_base_lo; /* 0x203C */
526  u32 fbr0_base_hi; /* 0x2040 */
527  u32 fbr0_num_des; /* 0x2044 */
528  u32 fbr0_avail_offset; /* 0x2048 */
529  u32 fbr0_full_offset; /* 0x204C */
530  u32 fbr0_rd_index; /* 0x2050 */
531  u32 fbr0_min_des; /* 0x2054 */
532  u32 fbr1_base_lo; /* 0x2058 */
533  u32 fbr1_base_hi; /* 0x205C */
534  u32 fbr1_num_des; /* 0x2060 */
535  u32 fbr1_avail_offset; /* 0x2064 */
536  u32 fbr1_full_offset; /* 0x2068 */
537  u32 fbr1_rd_index; /* 0x206C */
538  u32 fbr1_min_des; /* 0x2070 */
539 };
540 
541 /* END OF RXDMA REGISTER ADDRESS MAP */
542 
543 
544 /* START OF TXMAC REGISTER ADDRESS MAP */
545 
546 /*
547  * structure for control reg in txmac address map
548  * located at address 0x3000
549  *
550  * bits
551  * 31-8: unused
552  * 7: cklseg_disable
553  * 6: ckbcnt_disable
554  * 5: cksegnum
555  * 4: async_disable
556  * 3: fc_disable
557  * 2: mcif_disable
558  * 1: mif_disable
559  * 0: txmac_en
560  */
561 
562 /*
563  * structure for shadow pointer reg in txmac address map
564  * located at address 0x3004
565  * 31-27: reserved
566  * 26-16: txq rd ptr
567  * 15-11: reserved
568  * 10-0: txq wr ptr
569  */
570 
571 /*
572  * structure for error count reg in txmac address map
573  * located at address 0x3008
574  *
575  * 31-12: unused
576  * 11-8: reserved
577  * 7-4: txq_underrun
578  * 3-0: fifo_underrun
579  */
580 
581 /*
582  * structure for max fill reg in txmac address map
583  * located at address 0x300C
584  * 31-12: unused
585  * 11-0: max fill
586  */
587 
588 /*
589  * structure for cf parameter reg in txmac address map
590  * located at address 0x3010
591  * 31-16: cfep
592  * 15-0: cfpt
593  */
594 
595 /*
596  * structure for tx test reg in txmac address map
597  * located at address 0x3014
598  * 31-17: unused
599  * 16: reserved
600  * 15: txtest_en
601  * 14-11: unused
602  * 10-0: txq test pointer
603  */
604 
605 /*
606  * structure for error reg in txmac address map
607  * located at address 0x3018
608  *
609  * 31-9: unused
610  * 8: fifo_underrun
611  * 7-6: unused
612  * 5: ctrl2_err
613  * 4: txq_underrun
614  * 3: bcnt_err
615  * 2: lseg_err
616  * 1: segnum_err
617  * 0: seg0_err
618  */
619 
620 /*
621  * structure for error interrupt reg in txmac address map
622  * located at address 0x301C
623  *
624  * 31-9: unused
625  * 8: fifo_underrun
626  * 7-6: unused
627  * 5: ctrl2_err
628  * 4: txq_underrun
629  * 3: bcnt_err
630  * 2: lseg_err
631  * 1: segnum_err
632  * 0: seg0_err
633  */
634 
635 /*
636  * structure for error interrupt reg in txmac address map
637  * located at address 0x3020
638  *
639  * 31-2: unused
640  * 1: bp_req
641  * 0: bp_xonxoff
642  */
643 
644 /*
645  * Tx MAC Module of JAGCore Address Mapping
646  */
647 struct txmac_regs { /* Location: */
648  u32 ctl; /* 0x3000 */
649  u32 shadow_ptr; /* 0x3004 */
650  u32 err_cnt; /* 0x3008 */
651  u32 max_fill; /* 0x300C */
652  u32 cf_param; /* 0x3010 */
653  u32 tx_test; /* 0x3014 */
654  u32 err; /* 0x3018 */
655  u32 err_int; /* 0x301C */
656  u32 bp_ctrl; /* 0x3020 */
657 };
658 
659 /* END OF TXMAC REGISTER ADDRESS MAP */
660 
661 /* START OF RXMAC REGISTER ADDRESS MAP */
662 
663 /*
664  * structure for rxmac control reg in rxmac address map
665  * located at address 0x4000
666  *
667  * 31-7: reserved
668  * 6: rxmac_int_disable
669  * 5: async_disable
670  * 4: mif_disable
671  * 3: wol_disable
672  * 2: pkt_filter_disable
673  * 1: mcif_disable
674  * 0: rxmac_en
675  */
676 
677 /*
678  * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
679  * located at address 0x4004
680  * 31-16: crc
681  * 15-12: reserved
682  * 11: ignore_pp
683  * 10: ignore_mp
684  * 9: clr_intr
685  * 8: ignore_link_chg
686  * 7: ignore_uni
687  * 6: ignore_multi
688  * 5: ignore_broad
689  * 4-0: valid_crc 4-0
690  */
691 
692 /*
693  * structure for CRC 1 and CRC 2 reg in rxmac address map
694  * located at address 0x4008
695  *
696  * 31-16: crc2
697  * 15-0: crc1
698  */
699 
700 /*
701  * structure for CRC 3 and CRC 4 reg in rxmac address map
702  * located at address 0x400C
703  *
704  * 31-16: crc4
705  * 15-0: crc3
706  */
707 
708 /*
709  * structure for Wake On Lan Source Address Lo reg in rxmac address map
710  * located at address 0x4010
711  *
712  * 31-24: sa3
713  * 23-16: sa4
714  * 15-8: sa5
715  * 7-0: sa6
716  */
717 
718 #define ET_WOL_LO_SA3_SHIFT 24
719 #define ET_WOL_LO_SA4_SHIFT 16
720 #define ET_WOL_LO_SA5_SHIFT 8
721 
722 /*
723  * structure for Wake On Lan Source Address Hi reg in rxmac address map
724  * located at address 0x4014
725  *
726  * 31-16: reserved
727  * 15-8: sa1
728  * 7-0: sa2
729  */
730 
731 #define ET_WOL_HI_SA1_SHIFT 8
732 
733 /*
734  * structure for Wake On Lan mask reg in rxmac address map
735  * located at address 0x4018 - 0x4064
736  * Defined earlier (u32)
737  */
738 
739 /*
740  * structure for Unicast Paket Filter Address 1 reg in rxmac address map
741  * located at address 0x4068
742  *
743  * 31-24: addr1_3
744  * 23-16: addr1_4
745  * 15-8: addr1_5
746  * 7-0: addr1_6
747  */
748 
749 #define ET_UNI_PF_ADDR1_3_SHIFT 24
750 #define ET_UNI_PF_ADDR1_4_SHIFT 16
751 #define ET_UNI_PF_ADDR1_5_SHIFT 8
752 
753 /*
754  * structure for Unicast Paket Filter Address 2 reg in rxmac address map
755  * located at address 0x406C
756  *
757  * 31-24: addr2_3
758  * 23-16: addr2_4
759  * 15-8: addr2_5
760  * 7-0: addr2_6
761  */
762 
763 #define ET_UNI_PF_ADDR2_3_SHIFT 24
764 #define ET_UNI_PF_ADDR2_4_SHIFT 16
765 #define ET_UNI_PF_ADDR2_5_SHIFT 8
766 
767 /*
768  * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
769  * located at address 0x4070
770  *
771  * 31-24: addr2_1
772  * 23-16: addr2_2
773  * 15-8: addr1_1
774  * 7-0: addr1_2
775  */
776 
777 #define ET_UNI_PF_ADDR2_1_SHIFT 24
778 #define ET_UNI_PF_ADDR2_2_SHIFT 16
779 #define ET_UNI_PF_ADDR1_1_SHIFT 8
780 
781 
782 /*
783  * structure for Multicast Hash reg in rxmac address map
784  * located at address 0x4074 - 0x4080
785  * Defined earlier (u32)
786  */
787 
788 /*
789  * structure for Packet Filter Control reg in rxmac address map
790  * located at address 0x4084
791  *
792  * 31-23: unused
793  * 22-16: min_pkt_size
794  * 15-4: unused
795  * 3: filter_frag_en
796  * 2: filter_uni_en
797  * 1: filter_multi_en
798  * 0: filter_broad_en
799  */
800 
801 /*
802  * structure for Memory Controller Interface Control Max Segment reg in rxmac
803  * address map. Located at address 0x4088
804  *
805  * 31-10: reserved
806  * 9-2: max_size
807  * 1: fc_en
808  * 0: seg_en
809  */
810 
811 /*
812  * structure for Memory Controller Interface Water Mark reg in rxmac address
813  * map. Located at address 0x408C
814  *
815  * 31-26: unused
816  * 25-16: mark_hi
817  * 15-10: unused
818  * 9-0: mark_lo
819  */
820 
821 /*
822  * structure for Rx Queue Dialog reg in rxmac address map.
823  * located at address 0x4090
824  *
825  * 31-26: reserved
826  * 25-16: rd_ptr
827  * 15-10: reserved
828  * 9-0: wr_ptr
829  */
830 
831 /*
832  * structure for space available reg in rxmac address map.
833  * located at address 0x4094
834  *
835  * 31-17: reserved
836  * 16: space_avail_en
837  * 15-10: reserved
838  * 9-0: space_avail
839  */
840 
841 /*
842  * structure for management interface reg in rxmac address map.
843  * located at address 0x4098
844  *
845  * 31-18: reserved
846  * 17: drop_pkt_en
847  * 16-0: drop_pkt_mask
848  */
849 
850 /*
851  * structure for Error reg in rxmac address map.
852  * located at address 0x409C
853  *
854  * 31-4: unused
855  * 3: mif
856  * 2: async
857  * 1: pkt_filter
858  * 0: mcif
859  */
860 
861 /*
862  * Rx MAC Module of JAGCore Address Mapping
863  */
864 struct rxmac_regs { /* Location: */
865  u32 ctrl; /* 0x4000 */
866  u32 crc0; /* 0x4004 */
867  u32 crc12; /* 0x4008 */
868  u32 crc34; /* 0x400C */
869  u32 sa_lo; /* 0x4010 */
870  u32 sa_hi; /* 0x4014 */
871  u32 mask0_word0; /* 0x4018 */
872  u32 mask0_word1; /* 0x401C */
873  u32 mask0_word2; /* 0x4020 */
874  u32 mask0_word3; /* 0x4024 */
875  u32 mask1_word0; /* 0x4028 */
876  u32 mask1_word1; /* 0x402C */
877  u32 mask1_word2; /* 0x4030 */
878  u32 mask1_word3; /* 0x4034 */
879  u32 mask2_word0; /* 0x4038 */
880  u32 mask2_word1; /* 0x403C */
881  u32 mask2_word2; /* 0x4040 */
882  u32 mask2_word3; /* 0x4044 */
883  u32 mask3_word0; /* 0x4048 */
884  u32 mask3_word1; /* 0x404C */
885  u32 mask3_word2; /* 0x4050 */
886  u32 mask3_word3; /* 0x4054 */
887  u32 mask4_word0; /* 0x4058 */
888  u32 mask4_word1; /* 0x405C */
889  u32 mask4_word2; /* 0x4060 */
890  u32 mask4_word3; /* 0x4064 */
891  u32 uni_pf_addr1; /* 0x4068 */
892  u32 uni_pf_addr2; /* 0x406C */
893  u32 uni_pf_addr3; /* 0x4070 */
894  u32 multi_hash1; /* 0x4074 */
895  u32 multi_hash2; /* 0x4078 */
896  u32 multi_hash3; /* 0x407C */
897  u32 multi_hash4; /* 0x4080 */
898  u32 pf_ctrl; /* 0x4084 */
899  u32 mcif_ctrl_max_seg; /* 0x4088 */
900  u32 mcif_water_mark; /* 0x408C */
901  u32 rxq_diag; /* 0x4090 */
902  u32 space_avail; /* 0x4094 */
903 
904  u32 mif_ctrl; /* 0x4098 */
905  u32 err_reg; /* 0x409C */
906 };
907 
908 /* END OF RXMAC REGISTER ADDRESS MAP */
909 
910 
911 /* START OF MAC REGISTER ADDRESS MAP */
912 
913 /*
914  * structure for configuration #1 reg in mac address map.
915  * located at address 0x5000
916  *
917  * 31: soft reset
918  * 30: sim reset
919  * 29-20: reserved
920  * 19: reset rx mc
921  * 18: reset tx mc
922  * 17: reset rx func
923  * 16: reset tx fnc
924  * 15-9: reserved
925  * 8: loopback
926  * 7-6: reserved
927  * 5: rx flow
928  * 4: tx flow
929  * 3: syncd rx en
930  * 2: rx enable
931  * 1: syncd tx en
932  * 0: tx enable
933  */
934 
935 #define CFG1_LOOPBACK 0x00000100
936 #define CFG1_RX_FLOW 0x00000020
937 #define CFG1_TX_FLOW 0x00000010
938 #define CFG1_RX_ENABLE 0x00000004
939 #define CFG1_TX_ENABLE 0x00000001
940 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
941 
942 /*
943  * structure for configuration #2 reg in mac address map.
944  * located at address 0x5004
945  * 31-16: reserved
946  * 15-12: preamble
947  * 11-10: reserved
948  * 9-8: if mode
949  * 7-6: reserved
950  * 5: huge frame
951  * 4: length check
952  * 3: undefined
953  * 2: pad crc
954  * 1: crc enable
955  * 0: full duplex
956  */
957 
958 
959 /*
960  * structure for Interpacket gap reg in mac address map.
961  * located at address 0x5008
962  *
963  * 31: reserved
964  * 30-24: non B2B ipg 1
965  * 23: undefined
966  * 22-16: non B2B ipg 2
967  * 15-8: Min ifg enforce
968  * 7-0: B2B ipg
969  *
970  * structure for half duplex reg in mac address map.
971  * located at address 0x500C
972  * 31-24: reserved
973  * 23-20: Alt BEB trunc
974  * 19: Alt BEB enable
975  * 18: BP no backoff
976  * 17: no backoff
977  * 16: excess defer
978  * 15-12: re-xmit max
979  * 11-10: reserved
980  * 9-0: collision window
981  */
982 
983 /*
984  * structure for Maximum Frame Length reg in mac address map.
985  * located at address 0x5010: bits 0-15 hold the length.
986  */
987 
988 /*
989  * structure for Reserve 1 reg in mac address map.
990  * located at address 0x5014 - 0x5018
991  * Defined earlier (u32)
992  */
993 
994 /*
995  * structure for Test reg in mac address map.
996  * located at address 0x501C
997  * test: bits 0-2, rest unused
998  */
999 
1000 /*
1001  * structure for MII Management Configuration reg in mac address map.
1002  * located at address 0x5020
1003  *
1004  * 31: reset MII mgmt
1005  * 30-6: unused
1006  * 5: scan auto increment
1007  * 4: preamble suppress
1008  * 3: undefined
1009  * 2-0: mgmt clock reset
1010  */
1011 
1012 /*
1013  * structure for MII Management Command reg in mac address map.
1014  * located at address 0x5024
1015  * bit 1: scan cycle
1016  * bit 0: read cycle
1017  */
1018 
1019 /*
1020  * structure for MII Management Address reg in mac address map.
1021  * located at address 0x5028
1022  * 31-13: reserved
1023  * 12-8: phy addr
1024  * 7-5: reserved
1025  * 4-0: register
1026  */
1027 
1028 #define MII_ADDR(phy, reg) ((phy) << 8 | (reg))
1029 
1030 /*
1031  * structure for MII Management Control reg in mac address map.
1032  * located at address 0x502C
1033  * 31-16: reserved
1034  * 15-0: phy control
1035  */
1036 
1037 /*
1038  * structure for MII Management Status reg in mac address map.
1039  * located at address 0x5030
1040  * 31-16: reserved
1041  * 15-0: phy control
1042  */
1043 
1044 /*
1045  * structure for MII Management Indicators reg in mac address map.
1046  * located at address 0x5034
1047  * 31-3: reserved
1048  * 2: not valid
1049  * 1: scanning
1050  * 0: busy
1051  */
1052 
1053 #define MGMT_BUSY 0x00000001 /* busy */
1054 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1055 
1056 /*
1057  * structure for Interface Control reg in mac address map.
1058  * located at address 0x5038
1059  *
1060  * 31: reset if module
1061  * 30-28: reserved
1062  * 27: tbi mode
1063  * 26: ghd mode
1064  * 25: lhd mode
1065  * 24: phy mode
1066  * 23: reset per mii
1067  * 22-17: reserved
1068  * 16: speed
1069  * 15: reset pe100x
1070  * 14-11: reserved
1071  * 10: force quiet
1072  * 9: no cipher
1073  * 8: disable link fail
1074  * 7: reset gpsi
1075  * 6-1: reserved
1076  * 0: enable jabber protection
1077  */
1078 
1079 /*
1080  * structure for Interface Status reg in mac address map.
1081  * located at address 0x503C
1082  *
1083  * 31-10: reserved
1084  * 9: excess_defer
1085  * 8: clash
1086  * 7: phy_jabber
1087  * 6: phy_link_ok
1088  * 5: phy_full_duplex
1089  * 4: phy_speed
1090  * 3: pe100x_link_fail
1091  * 2: pe10t_loss_carrier
1092  * 1: pe10t_sqe_error
1093  * 0: pe10t_jabber
1094  */
1095 
1096 /*
1097  * structure for Mac Station Address, Part 1 reg in mac address map.
1098  * located at address 0x5040
1099  *
1100  * 31-24: Octet6
1101  * 23-16: Octet5
1102  * 15-8: Octet4
1103  * 7-0: Octet3
1104  */
1105 
1106 #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
1107 #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
1108 #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
1109 
1110 /*
1111  * structure for Mac Station Address, Part 2 reg in mac address map.
1112  * located at address 0x5044
1113  *
1114  * 31-24: Octet2
1115  * 23-16: Octet1
1116  * 15-0: reserved
1117  */
1118 
1119 #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
1120 #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
1121 
1122 /*
1123  * MAC Module of JAGCore Address Mapping
1124  */
1125 struct mac_regs { /* Location: */
1126  u32 cfg1; /* 0x5000 */
1127  u32 cfg2; /* 0x5004 */
1128  u32 ipg; /* 0x5008 */
1129  u32 hfdp; /* 0x500C */
1130  u32 max_fm_len; /* 0x5010 */
1131  u32 rsv1; /* 0x5014 */
1132  u32 rsv2; /* 0x5018 */
1133  u32 mac_test; /* 0x501C */
1134  u32 mii_mgmt_cfg; /* 0x5020 */
1135  u32 mii_mgmt_cmd; /* 0x5024 */
1136  u32 mii_mgmt_addr; /* 0x5028 */
1137  u32 mii_mgmt_ctrl; /* 0x502C */
1138  u32 mii_mgmt_stat; /* 0x5030 */
1139  u32 mii_mgmt_indicator; /* 0x5034 */
1140  u32 if_ctrl; /* 0x5038 */
1141  u32 if_stat; /* 0x503C */
1142  u32 station_addr_1; /* 0x5040 */
1143  u32 station_addr_2; /* 0x5044 */
1144 };
1145 
1146 /* END OF MAC REGISTER ADDRESS MAP */
1147 
1148 /* START OF MAC STAT REGISTER ADDRESS MAP */
1149 
1150 /*
1151  * structure for Carry Register One and it's Mask Register reg located in mac
1152  * stat address map address 0x6130 and 0x6138.
1153  *
1154  * 31: tr64
1155  * 30: tr127
1156  * 29: tr255
1157  * 28: tr511
1158  * 27: tr1k
1159  * 26: trmax
1160  * 25: trmgv
1161  * 24-17: unused
1162  * 16: rbyt
1163  * 15: rpkt
1164  * 14: rfcs
1165  * 13: rmca
1166  * 12: rbca
1167  * 11: rxcf
1168  * 10: rxpf
1169  * 9: rxuo
1170  * 8: raln
1171  * 7: rflr
1172  * 6: rcde
1173  * 5: rcse
1174  * 4: rund
1175  * 3: rovr
1176  * 2: rfrg
1177  * 1: rjbr
1178  * 0: rdrp
1179  */
1180 
1181 /*
1182  * structure for Carry Register Two Mask Register reg in mac stat address map.
1183  * located at address 0x613C
1184  *
1185  * 31-20: unused
1186  * 19: tjbr
1187  * 18: tfcs
1188  * 17: txcf
1189  * 16: tovr
1190  * 15: tund
1191  * 14: trfg
1192  * 13: tbyt
1193  * 12: tpkt
1194  * 11: tmca
1195  * 10: tbca
1196  * 9: txpf
1197  * 8: tdfr
1198  * 7: tedf
1199  * 6: tscl
1200  * 5: tmcl
1201  * 4: tlcl
1202  * 3: txcl
1203  * 2: tncl
1204  * 1: tpfh
1205  * 0: tdrp
1206  */
1207 
1208 /*
1209  * MAC STATS Module of JAGCore Address Mapping
1210  */
1211 struct macstat_regs { /* Location: */
1212  u32 pad[32]; /* 0x6000 - 607C */
1213 
1214  /* Tx/Rx 0-64 Byte Frame Counter */
1215  u32 txrx_0_64_byte_frames; /* 0x6080 */
1216 
1217  /* Tx/Rx 65-127 Byte Frame Counter */
1218  u32 txrx_65_127_byte_frames; /* 0x6084 */
1219 
1220  /* Tx/Rx 128-255 Byte Frame Counter */
1221  u32 txrx_128_255_byte_frames; /* 0x6088 */
1222 
1223  /* Tx/Rx 256-511 Byte Frame Counter */
1224  u32 txrx_256_511_byte_frames; /* 0x608C */
1225 
1226  /* Tx/Rx 512-1023 Byte Frame Counter */
1227  u32 txrx_512_1023_byte_frames; /* 0x6090 */
1228 
1229  /* Tx/Rx 1024-1518 Byte Frame Counter */
1230  u32 txrx_1024_1518_byte_frames; /* 0x6094 */
1231 
1232  /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1233  u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
1234 
1235  /* Rx Byte Counter */
1236  u32 rx_bytes; /* 0x609C */
1237 
1238  /* Rx Packet Counter */
1239  u32 rx_packets; /* 0x60A0 */
1240 
1241  /* Rx FCS Error Counter */
1242  u32 rx_fcs_errs; /* 0x60A4 */
1243 
1244  /* Rx Multicast Packet Counter */
1245  u32 rx_multicast_packets; /* 0x60A8 */
1246 
1247  /* Rx Broadcast Packet Counter */
1248  u32 rx_broadcast_packets; /* 0x60AC */
1249 
1250  /* Rx Control Frame Packet Counter */
1251  u32 rx_control_frames; /* 0x60B0 */
1252 
1253  /* Rx Pause Frame Packet Counter */
1254  u32 rx_pause_frames; /* 0x60B4 */
1255 
1256  /* Rx Unknown OP Code Counter */
1257  u32 rx_unknown_opcodes; /* 0x60B8 */
1258 
1259  /* Rx Alignment Error Counter */
1260  u32 rx_align_errs; /* 0x60BC */
1261 
1262  /* Rx Frame Length Error Counter */
1263  u32 rx_frame_len_errs; /* 0x60C0 */
1264 
1265  /* Rx Code Error Counter */
1266  u32 rx_code_errs; /* 0x60C4 */
1267 
1268  /* Rx Carrier Sense Error Counter */
1269  u32 rx_carrier_sense_errs; /* 0x60C8 */
1270 
1271  /* Rx Undersize Packet Counter */
1272  u32 rx_undersize_packets; /* 0x60CC */
1273 
1274  /* Rx Oversize Packet Counter */
1275  u32 rx_oversize_packets; /* 0x60D0 */
1276 
1277  /* Rx Fragment Counter */
1278  u32 rx_fragment_packets; /* 0x60D4 */
1279 
1280  /* Rx Jabber Counter */
1281  u32 rx_jabbers; /* 0x60D8 */
1282 
1283  /* Rx Drop */
1284  u32 rx_drops; /* 0x60DC */
1285 
1286  /* Tx Byte Counter */
1287  u32 tx_bytes; /* 0x60E0 */
1288 
1289  /* Tx Packet Counter */
1290  u32 tx_packets; /* 0x60E4 */
1291 
1292  /* Tx Multicast Packet Counter */
1293  u32 tx_multicast_packets; /* 0x60E8 */
1294 
1295  /* Tx Broadcast Packet Counter */
1296  u32 tx_broadcast_packets; /* 0x60EC */
1297 
1298  /* Tx Pause Control Frame Counter */
1299  u32 tx_pause_frames; /* 0x60F0 */
1300 
1301  /* Tx Deferral Packet Counter */
1302  u32 tx_deferred; /* 0x60F4 */
1303 
1304  /* Tx Excessive Deferral Packet Counter */
1305  u32 tx_excessive_deferred; /* 0x60F8 */
1306 
1307  /* Tx Single Collision Packet Counter */
1308  u32 tx_single_collisions; /* 0x60FC */
1309 
1310  /* Tx Multiple Collision Packet Counter */
1311  u32 tx_multiple_collisions; /* 0x6100 */
1312 
1313  /* Tx Late Collision Packet Counter */
1314  u32 tx_late_collisions; /* 0x6104 */
1315 
1316  /* Tx Excessive Collision Packet Counter */
1317  u32 tx_excessive_collisions; /* 0x6108 */
1318 
1319  /* Tx Total Collision Packet Counter */
1320  u32 tx_total_collisions; /* 0x610C */
1321 
1322  /* Tx Pause Frame Honored Counter */
1323  u32 tx_pause_honored_frames; /* 0x6110 */
1324 
1325  /* Tx Drop Frame Counter */
1326  u32 tx_drops; /* 0x6114 */
1327 
1328  /* Tx Jabber Frame Counter */
1329  u32 tx_jabbers; /* 0x6118 */
1330 
1331  /* Tx FCS Error Counter */
1332  u32 tx_fcs_errs; /* 0x611C */
1333 
1334  /* Tx Control Frame Counter */
1335  u32 tx_control_frames; /* 0x6120 */
1336 
1337  /* Tx Oversize Frame Counter */
1338  u32 tx_oversize_frames; /* 0x6124 */
1339 
1340  /* Tx Undersize Frame Counter */
1341  u32 tx_undersize_frames; /* 0x6128 */
1342 
1343  /* Tx Fragments Frame Counter */
1344  u32 tx_fragments; /* 0x612C */
1345 
1346  /* Carry Register One Register */
1347  u32 carry_reg1; /* 0x6130 */
1348 
1349  /* Carry Register Two Register */
1350  u32 carry_reg2; /* 0x6134 */
1351 
1352  /* Carry Register One Mask Register */
1353  u32 carry_reg1_mask; /* 0x6138 */
1354 
1355  /* Carry Register Two Mask Register */
1356  u32 carry_reg2_mask; /* 0x613C */
1357 };
1358 
1359 /* END OF MAC STAT REGISTER ADDRESS MAP */
1360 
1361 /* START OF MMC REGISTER ADDRESS MAP */
1362 
1363 /*
1364  * Main Memory Controller Control reg in mmc address map.
1365  * located at address 0x7000
1366  */
1367 
1368 #define ET_MMC_ENABLE 1
1369 #define ET_MMC_ARB_DISABLE 2
1370 #define ET_MMC_RXMAC_DISABLE 4
1371 #define ET_MMC_TXMAC_DISABLE 8
1372 #define ET_MMC_TXDMA_DISABLE 16
1373 #define ET_MMC_RXDMA_DISABLE 32
1374 #define ET_MMC_FORCE_CE 64
1375 
1376 /*
1377  * Main Memory Controller Host Memory Access Address reg in mmc
1378  * address map. Located at address 0x7004. Top 16 bits hold the address bits
1379  */
1380 
1381 #define ET_SRAM_REQ_ACCESS 1
1382 #define ET_SRAM_WR_ACCESS 2
1383 #define ET_SRAM_IS_CTRL 4
1384 
1385 /*
1386  * structure for Main Memory Controller Host Memory Access Data reg in mmc
1387  * address map. Located at address 0x7008 - 0x7014
1388  * Defined earlier (u32)
1389  */
1390 
1391 /*
1392  * Memory Control Module of JAGCore Address Mapping
1393  */
1394 struct mmc_regs { /* Location: */
1395  u32 mmc_ctrl; /* 0x7000 */
1396  u32 sram_access; /* 0x7004 */
1397  u32 sram_word1; /* 0x7008 */
1398  u32 sram_word2; /* 0x700C */
1399  u32 sram_word3; /* 0x7010 */
1400  u32 sram_word4; /* 0x7014 */
1401 };
1402 
1403 /* END OF MMC REGISTER ADDRESS MAP */
1404 
1405 
1406 /*
1407  * JAGCore Address Mapping
1408  */
1409 struct address_map {
1410  struct global_regs global;
1411  /* unused section of global address map */
1412  u8 unused_global[4096 - sizeof(struct global_regs)];
1413  struct txdma_regs txdma;
1414  /* unused section of txdma address map */
1415  u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1416  struct rxdma_regs rxdma;
1417  /* unused section of rxdma address map */
1418  u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1419  struct txmac_regs txmac;
1420  /* unused section of txmac address map */
1421  u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1422  struct rxmac_regs rxmac;
1423  /* unused section of rxmac address map */
1424  u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1425  struct mac_regs mac;
1426  /* unused section of mac address map */
1427  u8 unused_mac[4096 - sizeof(struct mac_regs)];
1428  struct macstat_regs macstat;
1429  /* unused section of mac stat address map */
1430  u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1431  struct mmc_regs mmc;
1432  /* unused section of mmc address map */
1433  u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1434  /* unused section of address map */
1435  u8 unused_[1015808];
1436 
1437  u8 unused_exp_rom[4096]; /* MGS-size TBD */
1438  u8 unused__[524288]; /* unused section of address map */
1439 };
1440 
1441 /*
1442  * Defines for generic MII registers 0x00 -> 0x0F can be found in
1443  * include/linux/mii.h
1444  */
1445 
1446 /* some defines for modem registers that seem to be 'reserved' */
1447 #define PHY_INDEX_REG 0x10
1448 #define PHY_DATA_REG 0x11
1449 #define PHY_MPHY_CONTROL_REG 0x12
1450 
1451 /* defines for specified registers */
1452 #define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
1453  /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
1454 #define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
1455 #define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
1456 #define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
1457 #define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
1458 #define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
1459 #define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
1460 #define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
1461 #define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
1462  /* TRU_VMI_LINK_CONTROL_REG 29 */
1463  /* TRU_VMI_TIMING_CONTROL_REG */
1464 
1465 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
1466 #define ET_1000BT_MSTR_SLV 0x4000
1467 
1468 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1469 
1470 /* MI Register 19: Loopback Control Reg(0x13)
1471  * 15: mii_en
1472  * 14: pcs_en
1473  * 13: pmd_en
1474  * 12: all_digital_en
1475  * 11: replica_en
1476  * 10: line_driver_en
1477  * 9-0: reserved
1478  */
1479 
1480 /* MI Register 20: Reserved Reg(0x14) */
1481 
1482 /* MI Register 21: Management Interface Control Reg(0x15)
1483  * 15-11: reserved
1484  * 10-4: mi_error_count
1485  * 3: reserved
1486  * 2: ignore_10g_fr
1487  * 1: reserved
1488  * 0: preamble_suppress_en
1489  */
1490 
1491 /* MI Register 22: PHY Configuration Reg(0x16)
1492  * 15: crs_tx_en
1493  * 14: reserved
1494  * 13-12: tx_fifo_depth
1495  * 11-10: speed_downshift
1496  * 9: pbi_detect
1497  * 8: tbi_rate
1498  * 7: alternate_np
1499  * 6: group_mdio_en
1500  * 5: tx_clock_en
1501  * 4: sys_clock_en
1502  * 3: reserved
1503  * 2-0: mac_if_mode
1504  */
1505 
1506 #define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
1507 
1508 #define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
1509 #define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
1510 #define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
1511 #define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
1512 
1513 /* MI Register 23: PHY CONTROL Reg(0x17)
1514  * 15: reserved
1515  * 14: tdr_en
1516  * 13: reserved
1517  * 12-11: downshift_attempts
1518  * 10-6: reserved
1519  * 5: jabber_10baseT
1520  * 4: sqe_10baseT
1521  * 3: tp_loopback_10baseT
1522  * 2: preamble_gen_en
1523  * 1: reserved
1524  * 0: force_int
1525  */
1526 
1527 /* MI Register 24: Interrupt Mask Reg(0x18)
1528  * 15-10: reserved
1529  * 9: mdio_sync_lost
1530  * 8: autoneg_status
1531  * 7: hi_bit_err
1532  * 6: np_rx
1533  * 5: err_counter_full
1534  * 4: fifo_over_underflow
1535  * 3: rx_status
1536  * 2: link_status
1537  * 1: automatic_speed
1538  * 0: int_en
1539  */
1540 
1541 #define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
1542 #define ET_PHY_INT_MASK_LINKSTAT 0x0004
1543 #define ET_PHY_INT_MASK_ENABLE 0x0001
1544 
1545 /* MI Register 25: Interrupt Status Reg(0x19)
1546  * 15-10: reserved
1547  * 9: mdio_sync_lost
1548  * 8: autoneg_status
1549  * 7: hi_bit_err
1550  * 6: np_rx
1551  * 5: err_counter_full
1552  * 4: fifo_over_underflow
1553  * 3: rx_status
1554  * 2: link_status
1555  * 1: automatic_speed
1556  * 0: int_en
1557  */
1558 
1559 /* MI Register 26: PHY Status Reg(0x1A)
1560  * 15: reserved
1561  * 14-13: autoneg_fault
1562  * 12: autoneg_status
1563  * 11: mdi_x_status
1564  * 10: polarity_status
1565  * 9-8: speed_status
1566  * 7: duplex_status
1567  * 6: link_status
1568  * 5: tx_status
1569  * 4: rx_status
1570  * 3: collision_status
1571  * 2: autoneg_en
1572  * 1: pause_en
1573  * 0: asymmetric_dir
1574  */
1575 #define ET_PHY_AUTONEG_STATUS 0x1000
1576 #define ET_PHY_POLARITY_STATUS 0x0400
1577 #define ET_PHY_SPEED_STATUS 0x0300
1578 #define ET_PHY_DUPLEX_STATUS 0x0080
1579 #define ET_PHY_LSTATUS 0x0040
1580 #define ET_PHY_AUTONEG_ENABLE 0x0020
1581 
1582 /* MI Register 27: LED Control Reg 1(0x1B)
1583  * 15-14: reserved
1584  * 13-12: led_dup_indicate
1585  * 11-10: led_10baseT
1586  * 9-8: led_collision
1587  * 7-4: reserved
1588  * 3-2: pulse_dur
1589  * 1: pulse_stretch1
1590  * 0: pulse_stretch0
1591  */
1592 
1593 /* MI Register 28: LED Control Reg 2(0x1C)
1594  * 15-12: led_link
1595  * 11-8: led_tx_rx
1596  * 7-4: led_100BaseTX
1597  * 3-0: led_1000BaseT
1598  */
1599 #define ET_LED2_LED_LINK 0xF000
1600 #define ET_LED2_LED_TXRX 0x0F00
1601 #define ET_LED2_LED_100TX 0x00F0
1602 #define ET_LED2_LED_1000T 0x000F
1603 
1604 /* defines for LED control reg 2 values */
1605 #define LED_VAL_1000BT 0x0
1606 #define LED_VAL_100BTX 0x1
1607 #define LED_VAL_10BT 0x2
1608 #define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
1609 #define LED_VAL_LINKON 0x4
1610 #define LED_VAL_TX 0x5
1611 #define LED_VAL_RX 0x6
1612 #define LED_VAL_TXRX 0x7 /* TX or RX */
1613 #define LED_VAL_DUPLEXFULL 0x8
1614 #define LED_VAL_COLLISION 0x9
1615 #define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
1616 #define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
1617 #define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
1618 #define LED_VAL_BLINK 0xD
1619 #define LED_VAL_ON 0xE
1620 #define LED_VAL_OFF 0xF
1621 
1622 #define LED_LINK_SHIFT 12
1623 #define LED_TXRX_SHIFT 8
1624 #define LED_100TX_SHIFT 4
1625 
1626 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
1627 
1628 /* Defines for PHY access routines */
1629 
1630 /* Define bit operation flags */
1631 #define TRUEPHY_BIT_CLEAR 0
1632 #define TRUEPHY_BIT_SET 1
1633 #define TRUEPHY_BIT_READ 2
1634 
1635 /* Define read/write operation flags */
1636 #ifndef TRUEPHY_READ
1637 #define TRUEPHY_READ 0
1638 #define TRUEPHY_WRITE 1
1639 #define TRUEPHY_MASK 2
1640 #endif
1641 
1642 /* Define master/slave configuration values */
1643 #define TRUEPHY_CFG_SLAVE 0
1644 #define TRUEPHY_CFG_MASTER 1
1645 
1646 /* Define MDI/MDI-X settings */
1647 #define TRUEPHY_MDI 0
1648 #define TRUEPHY_MDIX 1
1649 #define TRUEPHY_AUTO_MDI_MDIX 2
1650 
1651 /* Define 10Base-T link polarities */
1652 #define TRUEPHY_POLARITY_NORMAL 0
1653 #define TRUEPHY_POLARITY_INVERTED 1
1654 
1655 /* Define auto-negotiation results */
1656 #define TRUEPHY_ANEG_NOT_COMPLETE 0
1657 #define TRUEPHY_ANEG_COMPLETE 1
1658 #define TRUEPHY_ANEG_DISABLED 2
1659 
1660 /* Define duplex advertisement flags */
1661 #define TRUEPHY_ADV_DUPLEX_NONE 0x00
1662 #define TRUEPHY_ADV_DUPLEX_FULL 0x01
1663 #define TRUEPHY_ADV_DUPLEX_HALF 0x02
1664 #define TRUEPHY_ADV_DUPLEX_BOTH \
1665  (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
1666 
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