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Data Structures | Macros
et131x.h File Reference

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Data Structures

struct  global_regs
 
struct  txdma_regs
 
struct  rxdma_regs
 
struct  txmac_regs
 
struct  rxmac_regs
 
struct  mac_regs
 
struct  macstat_regs
 
struct  mmc_regs
 
struct  address_map
 

Macros

#define DRIVER_NAME   "et131x"
 
#define DRIVER_VERSION   "v2.0"
 
#define LBCIF_DWORD0_GROUP   0xAC
 
#define LBCIF_DWORD1_GROUP   0xB0
 
#define LBCIF_ADDRESS_REGISTER   0xAC
 
#define LBCIF_DATA_REGISTER   0xB0
 
#define LBCIF_CONTROL_REGISTER   0xB1
 
#define LBCIF_STATUS_REGISTER   0xB2
 
#define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
 
#define LBCIF_CONTROL_PAGE_WRITE   0x02
 
#define LBCIF_CONTROL_EEPROM_RELOAD   0x08
 
#define LBCIF_CONTROL_TWO_BYTE_ADDR   0x20
 
#define LBCIF_CONTROL_I2C_WRITE   0x40
 
#define LBCIF_CONTROL_LBCIF_ENABLE   0x80
 
#define LBCIF_STATUS_PHY_QUEUE_AVAIL   0x01
 
#define LBCIF_STATUS_I2C_IDLE   0x02
 
#define LBCIF_STATUS_ACK_ERROR   0x04
 
#define LBCIF_STATUS_GENERAL_ERROR   0x08
 
#define LBCIF_STATUS_CHECKSUM_ERROR   0x40
 
#define LBCIF_STATUS_EEPROM_PRESENT   0x80
 
#define ET_PM_PHY_SW_COMA   0x40
 
#define ET_PMCSR_INIT   0x38
 
#define ET_INTR_TXDMA_ISR   0x00000008
 
#define ET_INTR_TXDMA_ERR   0x00000010
 
#define ET_INTR_RXDMA_XFR_DONE   0x00000020
 
#define ET_INTR_RXDMA_FB_R0_LOW   0x00000040
 
#define ET_INTR_RXDMA_FB_R1_LOW   0x00000080
 
#define ET_INTR_RXDMA_STAT_LOW   0x00000100
 
#define ET_INTR_RXDMA_ERR   0x00000200
 
#define ET_INTR_WATCHDOG   0x00004000
 
#define ET_INTR_WOL   0x00008000
 
#define ET_INTR_PHY   0x00010000
 
#define ET_INTR_TXMAC   0x00020000
 
#define ET_INTR_RXMAC   0x00040000
 
#define ET_INTR_MAC_STAT   0x00080000
 
#define ET_INTR_SLV_TIMEOUT   0x00100000
 
#define ET_MSI_VECTOR   0x0000001F
 
#define ET_MSI_TC   0x00070000
 
#define ET_LOOP_MAC   0x00000001
 
#define ET_LOOP_DMA   0x00000002
 
#define ET_TXDMA_CSR_HALT   0x00000001
 
#define ET_TXDMA_DROP_TLP   0x00000002
 
#define ET_TXDMA_CACHE_THRS   0x000000F0
 
#define ET_TXDMA_CACHE_SHIFT   4
 
#define ET_TXDMA_SNGL_EPKT   0x00000100
 
#define ET_TXDMA_CLASS   0x00001E00
 
#define ET_DMA12_MASK   0x0FFF /* 12 bit mask for DMA12W types */
 
#define ET_DMA12_WRAP   0x1000
 
#define ET_DMA10_MASK   0x03FF /* 10 bit mask for DMA10W types */
 
#define ET_DMA10_WRAP   0x0400
 
#define ET_DMA4_MASK   0x000F /* 4 bit mask for DMA4W types */
 
#define ET_DMA4_WRAP   0x0010
 
#define INDEX12(x)   ((x) & ET_DMA12_MASK)
 
#define INDEX10(x)   ((x) & ET_DMA10_MASK)
 
#define INDEX4(x)   ((x) & ET_DMA4_MASK)
 
#define ET_WOL_LO_SA3_SHIFT   24
 
#define ET_WOL_LO_SA4_SHIFT   16
 
#define ET_WOL_LO_SA5_SHIFT   8
 
#define ET_WOL_HI_SA1_SHIFT   8
 
#define ET_UNI_PF_ADDR1_3_SHIFT   24
 
#define ET_UNI_PF_ADDR1_4_SHIFT   16
 
#define ET_UNI_PF_ADDR1_5_SHIFT   8
 
#define ET_UNI_PF_ADDR2_3_SHIFT   24
 
#define ET_UNI_PF_ADDR2_4_SHIFT   16
 
#define ET_UNI_PF_ADDR2_5_SHIFT   8
 
#define ET_UNI_PF_ADDR2_1_SHIFT   24
 
#define ET_UNI_PF_ADDR2_2_SHIFT   16
 
#define ET_UNI_PF_ADDR1_1_SHIFT   8
 
#define CFG1_LOOPBACK   0x00000100
 
#define CFG1_RX_FLOW   0x00000020
 
#define CFG1_TX_FLOW   0x00000010
 
#define CFG1_RX_ENABLE   0x00000004
 
#define CFG1_TX_ENABLE   0x00000001
 
#define CFG1_WAIT   0x0000000A /* RX & TX syncd */
 
#define MII_ADDR(phy, reg)   ((phy) << 8 | (reg))
 
#define MGMT_BUSY   0x00000001 /* busy */
 
#define MGMT_WAIT   0x00000005 /* busy | not valid */
 
#define ET_MAC_STATION_ADDR1_OC6_SHIFT   24
 
#define ET_MAC_STATION_ADDR1_OC5_SHIFT   16
 
#define ET_MAC_STATION_ADDR1_OC4_SHIFT   8
 
#define ET_MAC_STATION_ADDR2_OC2_SHIFT   24
 
#define ET_MAC_STATION_ADDR2_OC1_SHIFT   16
 
#define ET_MMC_ENABLE   1
 
#define ET_MMC_ARB_DISABLE   2
 
#define ET_MMC_RXMAC_DISABLE   4
 
#define ET_MMC_TXMAC_DISABLE   8
 
#define ET_MMC_TXDMA_DISABLE   16
 
#define ET_MMC_RXDMA_DISABLE   32
 
#define ET_MMC_FORCE_CE   64
 
#define ET_SRAM_REQ_ACCESS   1
 
#define ET_SRAM_WR_ACCESS   2
 
#define ET_SRAM_IS_CTRL   4
 
#define PHY_INDEX_REG   0x10
 
#define PHY_DATA_REG   0x11
 
#define PHY_MPHY_CONTROL_REG   0x12
 
#define PHY_LOOPBACK_CONTROL   0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
 
#define PHY_REGISTER_MGMT_CONTROL   0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
 
#define PHY_CONFIG   0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
 
#define PHY_PHY_CONTROL   0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
 
#define PHY_INTERRUPT_MASK   0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
 
#define PHY_INTERRUPT_STATUS   0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
 
#define PHY_PHY_STATUS   0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
 
#define PHY_LED_1   0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
 
#define PHY_LED_2   0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
 
#define ET_1000BT_MSTR_SLV   0x4000
 
#define ET_PHY_CONFIG_TX_FIFO_DEPTH   0x3000
 
#define ET_PHY_CONFIG_FIFO_DEPTH_8   0x0000
 
#define ET_PHY_CONFIG_FIFO_DEPTH_16   0x1000
 
#define ET_PHY_CONFIG_FIFO_DEPTH_32   0x2000
 
#define ET_PHY_CONFIG_FIFO_DEPTH_64   0x3000
 
#define ET_PHY_INT_MASK_AUTONEGSTAT   0x0100
 
#define ET_PHY_INT_MASK_LINKSTAT   0x0004
 
#define ET_PHY_INT_MASK_ENABLE   0x0001
 
#define ET_PHY_AUTONEG_STATUS   0x1000
 
#define ET_PHY_POLARITY_STATUS   0x0400
 
#define ET_PHY_SPEED_STATUS   0x0300
 
#define ET_PHY_DUPLEX_STATUS   0x0080
 
#define ET_PHY_LSTATUS   0x0040
 
#define ET_PHY_AUTONEG_ENABLE   0x0020
 
#define ET_LED2_LED_LINK   0xF000
 
#define ET_LED2_LED_TXRX   0x0F00
 
#define ET_LED2_LED_100TX   0x00F0
 
#define ET_LED2_LED_1000T   0x000F
 
#define LED_VAL_1000BT   0x0
 
#define LED_VAL_100BTX   0x1
 
#define LED_VAL_10BT   0x2
 
#define LED_VAL_1000BT_100BTX   0x3 /* 1000BT on, 100BTX blink */
 
#define LED_VAL_LINKON   0x4
 
#define LED_VAL_TX   0x5
 
#define LED_VAL_RX   0x6
 
#define LED_VAL_TXRX   0x7 /* TX or RX */
 
#define LED_VAL_DUPLEXFULL   0x8
 
#define LED_VAL_COLLISION   0x9
 
#define LED_VAL_LINKON_ACTIVE   0xA /* Link on, activity blink */
 
#define LED_VAL_LINKON_RECV   0xB /* Link on, receive blink */
 
#define LED_VAL_DUPLEXFULL_COLLISION   0xC /* Duplex on, collision blink */
 
#define LED_VAL_BLINK   0xD
 
#define LED_VAL_ON   0xE
 
#define LED_VAL_OFF   0xF
 
#define LED_LINK_SHIFT   12
 
#define LED_TXRX_SHIFT   8
 
#define LED_100TX_SHIFT   4
 
#define TRUEPHY_BIT_CLEAR   0
 
#define TRUEPHY_BIT_SET   1
 
#define TRUEPHY_BIT_READ   2
 
#define TRUEPHY_READ   0
 
#define TRUEPHY_WRITE   1
 
#define TRUEPHY_MASK   2
 
#define TRUEPHY_CFG_SLAVE   0
 
#define TRUEPHY_CFG_MASTER   1
 
#define TRUEPHY_MDI   0
 
#define TRUEPHY_MDIX   1
 
#define TRUEPHY_AUTO_MDI_MDIX   2
 
#define TRUEPHY_POLARITY_NORMAL   0
 
#define TRUEPHY_POLARITY_INVERTED   1
 
#define TRUEPHY_ANEG_NOT_COMPLETE   0
 
#define TRUEPHY_ANEG_COMPLETE   1
 
#define TRUEPHY_ANEG_DISABLED   2
 
#define TRUEPHY_ADV_DUPLEX_NONE   0x00
 
#define TRUEPHY_ADV_DUPLEX_FULL   0x01
 
#define TRUEPHY_ADV_DUPLEX_HALF   0x02
 
#define TRUEPHY_ADV_DUPLEX_BOTH   (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
 

Macro Definition Documentation

#define CFG1_LOOPBACK   0x00000100

Definition at line 935 of file et131x.h.

#define CFG1_RX_ENABLE   0x00000004

Definition at line 938 of file et131x.h.

#define CFG1_RX_FLOW   0x00000020

Definition at line 936 of file et131x.h.

#define CFG1_TX_ENABLE   0x00000001

Definition at line 939 of file et131x.h.

#define CFG1_TX_FLOW   0x00000010

Definition at line 937 of file et131x.h.

#define CFG1_WAIT   0x0000000A /* RX & TX syncd */

Definition at line 940 of file et131x.h.

#define DRIVER_NAME   "et131x"

Definition at line 49 of file et131x.h.

#define DRIVER_VERSION   "v2.0"

Definition at line 50 of file et131x.h.

#define ET_1000BT_MSTR_SLV   0x4000

Definition at line 1466 of file et131x.h.

#define ET_DMA10_MASK   0x03FF /* 10 bit mask for DMA10W types */

Definition at line 224 of file et131x.h.

#define ET_DMA10_WRAP   0x0400

Definition at line 225 of file et131x.h.

#define ET_DMA12_MASK   0x0FFF /* 12 bit mask for DMA12W types */

Definition at line 222 of file et131x.h.

#define ET_DMA12_WRAP   0x1000

Definition at line 223 of file et131x.h.

#define ET_DMA4_MASK   0x000F /* 4 bit mask for DMA4W types */

Definition at line 226 of file et131x.h.

#define ET_DMA4_WRAP   0x0010

Definition at line 227 of file et131x.h.

#define ET_INTR_MAC_STAT   0x00080000

Definition at line 125 of file et131x.h.

#define ET_INTR_PHY   0x00010000

Definition at line 122 of file et131x.h.

#define ET_INTR_RXDMA_ERR   0x00000200

Definition at line 119 of file et131x.h.

#define ET_INTR_RXDMA_FB_R0_LOW   0x00000040

Definition at line 116 of file et131x.h.

#define ET_INTR_RXDMA_FB_R1_LOW   0x00000080

Definition at line 117 of file et131x.h.

#define ET_INTR_RXDMA_STAT_LOW   0x00000100

Definition at line 118 of file et131x.h.

#define ET_INTR_RXDMA_XFR_DONE   0x00000020

Definition at line 115 of file et131x.h.

#define ET_INTR_RXMAC   0x00040000

Definition at line 124 of file et131x.h.

#define ET_INTR_SLV_TIMEOUT   0x00100000

Definition at line 126 of file et131x.h.

#define ET_INTR_TXDMA_ERR   0x00000010

Definition at line 114 of file et131x.h.

#define ET_INTR_TXDMA_ISR   0x00000008

Definition at line 113 of file et131x.h.

#define ET_INTR_TXMAC   0x00020000

Definition at line 123 of file et131x.h.

#define ET_INTR_WATCHDOG   0x00004000

Definition at line 120 of file et131x.h.

#define ET_INTR_WOL   0x00008000

Definition at line 121 of file et131x.h.

#define ET_LED2_LED_1000T   0x000F

Definition at line 1602 of file et131x.h.

#define ET_LED2_LED_100TX   0x00F0

Definition at line 1601 of file et131x.h.

#define ET_LED2_LED_LINK   0xF000

Definition at line 1599 of file et131x.h.

#define ET_LED2_LED_TXRX   0x0F00

Definition at line 1600 of file et131x.h.

#define ET_LOOP_DMA   0x00000002

Definition at line 164 of file et131x.h.

#define ET_LOOP_MAC   0x00000001

Definition at line 163 of file et131x.h.

#define ET_MAC_STATION_ADDR1_OC4_SHIFT   8

Definition at line 1108 of file et131x.h.

#define ET_MAC_STATION_ADDR1_OC5_SHIFT   16

Definition at line 1107 of file et131x.h.

#define ET_MAC_STATION_ADDR1_OC6_SHIFT   24

Definition at line 1106 of file et131x.h.

#define ET_MAC_STATION_ADDR2_OC1_SHIFT   16

Definition at line 1120 of file et131x.h.

#define ET_MAC_STATION_ADDR2_OC2_SHIFT   24

Definition at line 1119 of file et131x.h.

#define ET_MMC_ARB_DISABLE   2

Definition at line 1369 of file et131x.h.

#define ET_MMC_ENABLE   1

Definition at line 1368 of file et131x.h.

#define ET_MMC_FORCE_CE   64

Definition at line 1374 of file et131x.h.

#define ET_MMC_RXDMA_DISABLE   32

Definition at line 1373 of file et131x.h.

#define ET_MMC_RXMAC_DISABLE   4

Definition at line 1370 of file et131x.h.

#define ET_MMC_TXDMA_DISABLE   16

Definition at line 1372 of file et131x.h.

#define ET_MMC_TXMAC_DISABLE   8

Definition at line 1371 of file et131x.h.

#define ET_MSI_TC   0x00070000

Definition at line 157 of file et131x.h.

#define ET_MSI_VECTOR   0x0000001F

Definition at line 156 of file et131x.h.

#define ET_PHY_AUTONEG_ENABLE   0x0020

Definition at line 1580 of file et131x.h.

#define ET_PHY_AUTONEG_STATUS   0x1000

Definition at line 1575 of file et131x.h.

#define ET_PHY_CONFIG_FIFO_DEPTH_16   0x1000

Definition at line 1509 of file et131x.h.

#define ET_PHY_CONFIG_FIFO_DEPTH_32   0x2000

Definition at line 1510 of file et131x.h.

#define ET_PHY_CONFIG_FIFO_DEPTH_64   0x3000

Definition at line 1511 of file et131x.h.

#define ET_PHY_CONFIG_FIFO_DEPTH_8   0x0000

Definition at line 1508 of file et131x.h.

#define ET_PHY_CONFIG_TX_FIFO_DEPTH   0x3000

Definition at line 1506 of file et131x.h.

#define ET_PHY_DUPLEX_STATUS   0x0080

Definition at line 1578 of file et131x.h.

#define ET_PHY_INT_MASK_AUTONEGSTAT   0x0100

Definition at line 1541 of file et131x.h.

#define ET_PHY_INT_MASK_ENABLE   0x0001

Definition at line 1543 of file et131x.h.

#define ET_PHY_INT_MASK_LINKSTAT   0x0004

Definition at line 1542 of file et131x.h.

#define ET_PHY_LSTATUS   0x0040

Definition at line 1579 of file et131x.h.

#define ET_PHY_POLARITY_STATUS   0x0400

Definition at line 1576 of file et131x.h.

#define ET_PHY_SPEED_STATUS   0x0300

Definition at line 1577 of file et131x.h.

#define ET_PM_PHY_SW_COMA   0x40

Definition at line 106 of file et131x.h.

#define ET_PMCSR_INIT   0x38

Definition at line 107 of file et131x.h.

#define ET_SRAM_IS_CTRL   4

Definition at line 1383 of file et131x.h.

#define ET_SRAM_REQ_ACCESS   1

Definition at line 1381 of file et131x.h.

#define ET_SRAM_WR_ACCESS   2

Definition at line 1382 of file et131x.h.

#define ET_TXDMA_CACHE_SHIFT   4

Definition at line 198 of file et131x.h.

#define ET_TXDMA_CACHE_THRS   0x000000F0

Definition at line 197 of file et131x.h.

#define ET_TXDMA_CLASS   0x00001E00

Definition at line 200 of file et131x.h.

#define ET_TXDMA_CSR_HALT   0x00000001

Definition at line 195 of file et131x.h.

#define ET_TXDMA_DROP_TLP   0x00000002

Definition at line 196 of file et131x.h.

#define ET_TXDMA_SNGL_EPKT   0x00000100

Definition at line 199 of file et131x.h.

#define ET_UNI_PF_ADDR1_1_SHIFT   8

Definition at line 779 of file et131x.h.

#define ET_UNI_PF_ADDR1_3_SHIFT   24

Definition at line 749 of file et131x.h.

#define ET_UNI_PF_ADDR1_4_SHIFT   16

Definition at line 750 of file et131x.h.

#define ET_UNI_PF_ADDR1_5_SHIFT   8

Definition at line 751 of file et131x.h.

#define ET_UNI_PF_ADDR2_1_SHIFT   24

Definition at line 777 of file et131x.h.

#define ET_UNI_PF_ADDR2_2_SHIFT   16

Definition at line 778 of file et131x.h.

#define ET_UNI_PF_ADDR2_3_SHIFT   24

Definition at line 763 of file et131x.h.

#define ET_UNI_PF_ADDR2_4_SHIFT   16

Definition at line 764 of file et131x.h.

#define ET_UNI_PF_ADDR2_5_SHIFT   8

Definition at line 765 of file et131x.h.

#define ET_WOL_HI_SA1_SHIFT   8

Definition at line 731 of file et131x.h.

#define ET_WOL_LO_SA3_SHIFT   24

Definition at line 718 of file et131x.h.

#define ET_WOL_LO_SA4_SHIFT   16

Definition at line 719 of file et131x.h.

#define ET_WOL_LO_SA5_SHIFT   8

Definition at line 720 of file et131x.h.

#define INDEX10 (   x)    ((x) & ET_DMA10_MASK)

Definition at line 230 of file et131x.h.

#define INDEX12 (   x)    ((x) & ET_DMA12_MASK)

Definition at line 229 of file et131x.h.

#define INDEX4 (   x)    ((x) & ET_DMA4_MASK)

Definition at line 231 of file et131x.h.

#define LBCIF_ADDRESS_REGISTER   0xAC

Definition at line 59 of file et131x.h.

#define LBCIF_CONTROL_EEPROM_RELOAD   0x08

Definition at line 67 of file et131x.h.

#define LBCIF_CONTROL_I2C_WRITE   0x40

Definition at line 69 of file et131x.h.

#define LBCIF_CONTROL_LBCIF_ENABLE   0x80

Definition at line 70 of file et131x.h.

#define LBCIF_CONTROL_PAGE_WRITE   0x02

Definition at line 66 of file et131x.h.

#define LBCIF_CONTROL_REGISTER   0xB1

Definition at line 61 of file et131x.h.

#define LBCIF_CONTROL_SEQUENTIAL_READ   0x01

Definition at line 65 of file et131x.h.

#define LBCIF_CONTROL_TWO_BYTE_ADDR   0x20

Definition at line 68 of file et131x.h.

#define LBCIF_DATA_REGISTER   0xB0

Definition at line 60 of file et131x.h.

#define LBCIF_DWORD0_GROUP   0xAC

Definition at line 55 of file et131x.h.

#define LBCIF_DWORD1_GROUP   0xB0

Definition at line 56 of file et131x.h.

#define LBCIF_STATUS_ACK_ERROR   0x04

Definition at line 75 of file et131x.h.

#define LBCIF_STATUS_CHECKSUM_ERROR   0x40

Definition at line 77 of file et131x.h.

#define LBCIF_STATUS_EEPROM_PRESENT   0x80

Definition at line 78 of file et131x.h.

#define LBCIF_STATUS_GENERAL_ERROR   0x08

Definition at line 76 of file et131x.h.

#define LBCIF_STATUS_I2C_IDLE   0x02

Definition at line 74 of file et131x.h.

#define LBCIF_STATUS_PHY_QUEUE_AVAIL   0x01

Definition at line 73 of file et131x.h.

#define LBCIF_STATUS_REGISTER   0xB2

Definition at line 62 of file et131x.h.

#define LED_100TX_SHIFT   4

Definition at line 1624 of file et131x.h.

#define LED_LINK_SHIFT   12

Definition at line 1622 of file et131x.h.

#define LED_TXRX_SHIFT   8

Definition at line 1623 of file et131x.h.

#define LED_VAL_1000BT   0x0

Definition at line 1605 of file et131x.h.

#define LED_VAL_1000BT_100BTX   0x3 /* 1000BT on, 100BTX blink */

Definition at line 1608 of file et131x.h.

#define LED_VAL_100BTX   0x1

Definition at line 1606 of file et131x.h.

#define LED_VAL_10BT   0x2

Definition at line 1607 of file et131x.h.

#define LED_VAL_BLINK   0xD

Definition at line 1618 of file et131x.h.

#define LED_VAL_COLLISION   0x9

Definition at line 1614 of file et131x.h.

#define LED_VAL_DUPLEXFULL   0x8

Definition at line 1613 of file et131x.h.

#define LED_VAL_DUPLEXFULL_COLLISION   0xC /* Duplex on, collision blink */

Definition at line 1617 of file et131x.h.

#define LED_VAL_LINKON   0x4

Definition at line 1609 of file et131x.h.

#define LED_VAL_LINKON_ACTIVE   0xA /* Link on, activity blink */

Definition at line 1615 of file et131x.h.

#define LED_VAL_LINKON_RECV   0xB /* Link on, receive blink */

Definition at line 1616 of file et131x.h.

#define LED_VAL_OFF   0xF

Definition at line 1620 of file et131x.h.

#define LED_VAL_ON   0xE

Definition at line 1619 of file et131x.h.

#define LED_VAL_RX   0x6

Definition at line 1611 of file et131x.h.

#define LED_VAL_TX   0x5

Definition at line 1610 of file et131x.h.

#define LED_VAL_TXRX   0x7 /* TX or RX */

Definition at line 1612 of file et131x.h.

#define MGMT_BUSY   0x00000001 /* busy */

Definition at line 1053 of file et131x.h.

#define MGMT_WAIT   0x00000005 /* busy | not valid */

Definition at line 1054 of file et131x.h.

#define MII_ADDR (   phy,
  reg 
)    ((phy) << 8 | (reg))

Definition at line 1028 of file et131x.h.

#define PHY_CONFIG   0x16 /* TRU_VMI_CONFIGURATION_REG 22 */

Definition at line 1455 of file et131x.h.

#define PHY_DATA_REG   0x11

Definition at line 1448 of file et131x.h.

#define PHY_INDEX_REG   0x10

Definition at line 1447 of file et131x.h.

#define PHY_INTERRUPT_MASK   0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */

Definition at line 1457 of file et131x.h.

#define PHY_INTERRUPT_STATUS   0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */

Definition at line 1458 of file et131x.h.

#define PHY_LED_1   0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */

Definition at line 1460 of file et131x.h.

#define PHY_LED_2   0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */

Definition at line 1461 of file et131x.h.

#define PHY_LOOPBACK_CONTROL   0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */

Definition at line 1452 of file et131x.h.

#define PHY_MPHY_CONTROL_REG   0x12

Definition at line 1449 of file et131x.h.

#define PHY_PHY_CONTROL   0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */

Definition at line 1456 of file et131x.h.

#define PHY_PHY_STATUS   0x1A /* TRU_VMI_PHY_STATUS_REG 26 */

Definition at line 1459 of file et131x.h.

#define PHY_REGISTER_MGMT_CONTROL   0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */

Definition at line 1454 of file et131x.h.

#define TRUEPHY_ADV_DUPLEX_BOTH   (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)

Definition at line 1664 of file et131x.h.

#define TRUEPHY_ADV_DUPLEX_FULL   0x01

Definition at line 1662 of file et131x.h.

#define TRUEPHY_ADV_DUPLEX_HALF   0x02

Definition at line 1663 of file et131x.h.

#define TRUEPHY_ADV_DUPLEX_NONE   0x00

Definition at line 1661 of file et131x.h.

#define TRUEPHY_ANEG_COMPLETE   1

Definition at line 1657 of file et131x.h.

#define TRUEPHY_ANEG_DISABLED   2

Definition at line 1658 of file et131x.h.

#define TRUEPHY_ANEG_NOT_COMPLETE   0

Definition at line 1656 of file et131x.h.

#define TRUEPHY_AUTO_MDI_MDIX   2

Definition at line 1649 of file et131x.h.

#define TRUEPHY_BIT_CLEAR   0

Definition at line 1631 of file et131x.h.

#define TRUEPHY_BIT_READ   2

Definition at line 1633 of file et131x.h.

#define TRUEPHY_BIT_SET   1

Definition at line 1632 of file et131x.h.

#define TRUEPHY_CFG_MASTER   1

Definition at line 1644 of file et131x.h.

#define TRUEPHY_CFG_SLAVE   0

Definition at line 1643 of file et131x.h.

#define TRUEPHY_MASK   2

Definition at line 1639 of file et131x.h.

#define TRUEPHY_MDI   0

Definition at line 1647 of file et131x.h.

#define TRUEPHY_MDIX   1

Definition at line 1648 of file et131x.h.

#define TRUEPHY_POLARITY_INVERTED   1

Definition at line 1653 of file et131x.h.

#define TRUEPHY_POLARITY_NORMAL   0

Definition at line 1652 of file et131x.h.

#define TRUEPHY_READ   0

Definition at line 1637 of file et131x.h.

#define TRUEPHY_WRITE   1

Definition at line 1638 of file et131x.h.