Go to the documentation of this file. 1 #ifndef __extmem_defs_h
2 #define __extmem_defs_h
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
97 unsigned int erc_en : 1;
98 unsigned int dummy1 : 6;
103 #define REG_RD_ADDR_extmem_rw_cse0_cfg 0
104 #define REG_WR_ADDR_extmem_rw_cse0_cfg 0
113 unsigned int ewb : 2;
116 unsigned int erc_en : 1;
117 unsigned int dummy1 : 6;
122 #define REG_RD_ADDR_extmem_rw_cse1_cfg 4
123 #define REG_WR_ADDR_extmem_rw_cse1_cfg 4
132 unsigned int ewb : 2;
135 unsigned int erc_en : 1;
136 unsigned int dummy1 : 6;
141 #define REG_RD_ADDR_extmem_rw_csr0_cfg 8
142 #define REG_WR_ADDR_extmem_rw_csr0_cfg 8
151 unsigned int ewb : 2;
154 unsigned int erc_en : 1;
155 unsigned int dummy1 : 6;
160 #define REG_RD_ADDR_extmem_rw_csr1_cfg 12
161 #define REG_WR_ADDR_extmem_rw_csr1_cfg 12
170 unsigned int ewb : 2;
173 unsigned int erc_en : 1;
174 unsigned int dummy1 : 6;
179 #define REG_RD_ADDR_extmem_rw_csp0_cfg 16
180 #define REG_WR_ADDR_extmem_rw_csp0_cfg 16
189 unsigned int ewb : 2;
192 unsigned int erc_en : 1;
193 unsigned int dummy1 : 6;
198 #define REG_RD_ADDR_extmem_rw_csp1_cfg 20
199 #define REG_WR_ADDR_extmem_rw_csp1_cfg 20
208 unsigned int ewb : 2;
211 unsigned int erc_en : 1;
212 unsigned int dummy1 : 6;
217 #define REG_RD_ADDR_extmem_rw_csp2_cfg 24
218 #define REG_WR_ADDR_extmem_rw_csp2_cfg 24
227 unsigned int ewb : 2;
230 unsigned int erc_en : 1;
231 unsigned int dummy1 : 6;
236 #define REG_RD_ADDR_extmem_rw_csp3_cfg 28
237 #define REG_WR_ADDR_extmem_rw_csp3_cfg 28
246 unsigned int ewb : 2;
249 unsigned int erc_en : 1;
250 unsigned int dummy1 : 6;
255 #define REG_RD_ADDR_extmem_rw_csp4_cfg 32
256 #define REG_WR_ADDR_extmem_rw_csp4_cfg 32
265 unsigned int ewb : 2;
268 unsigned int erc_en : 1;
269 unsigned int dummy1 : 6;
274 #define REG_RD_ADDR_extmem_rw_csp5_cfg 36
275 #define REG_WR_ADDR_extmem_rw_csp5_cfg 36
284 unsigned int ewb : 2;
287 unsigned int erc_en : 1;
288 unsigned int dummy1 : 6;
293 #define REG_RD_ADDR_extmem_rw_csp6_cfg 40
294 #define REG_WR_ADDR_extmem_rw_csp6_cfg 40
303 unsigned int ewb : 2;
306 unsigned int erc_en : 1;
307 unsigned int dummy1 : 6;
312 #define REG_RD_ADDR_extmem_rw_css_cfg 44
313 #define REG_WR_ADDR_extmem_rw_css_cfg 44
319 #define REG_RD_ADDR_extmem_rw_status_handle 48
320 #define REG_WR_ADDR_extmem_rw_status_handle 48
325 unsigned int dummy1 : 15;
328 #define REG_RD_ADDR_extmem_rw_wait_pin 52
329 #define REG_WR_ADDR_extmem_rw_wait_pin 52
333 unsigned int dummy1 : 31;
336 #define REG_RD_ADDR_extmem_rw_gated_csp 56
337 #define REG_WR_ADDR_extmem_rw_gated_csp 56