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9 #ifndef _LTQ_FALCON_H__
10 #define _LTQ_FALCON_H__
12 #ifdef CONFIG_SOC_FALCON
18 #define SOC_ID_FALCON 0x01B8
21 #define SOC_TYPE_FALCON 0x01
27 #define LTQ_ASC0_BASE_ADDR 0x1E100C00
28 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
31 #define LTQ_RST_CAUSE_WDTRST 0x0002
34 #define LTQ_STATUS_BASE_ADDR 0x1E802000
36 #define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
37 #define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
38 #define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
42 #define SYSCTL_SYSETH 1
43 #define SYSCTL_SYSGPE 2
52 #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
53 #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
55 #define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
56 #define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
57 #define ltq_sys1_w32_mask(clear, set, reg) \
58 ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
68 #define LTQ_EBU_PCC_ISTAT 0