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14 #ifndef __DRIVERS_NET_MPC52XX_FEC_H__
15 #define __DRIVERS_NET_MPC52XX_FEC_H__
21 #define FEC_RX_BUFFER_SIZE 1522
22 #define FEC_RX_NUM_BD 256
23 #define FEC_TX_NUM_BD 64
25 #define FEC_RESET_DELAY 50
27 #define FEC_WATCHDOG_TIMEOUT ((400*HZ)/1000)
210 #define FEC_MIB_DISABLE 0x80000000
212 #define FEC_IEVENT_HBERR 0x80000000
213 #define FEC_IEVENT_BABR 0x40000000
214 #define FEC_IEVENT_BABT 0x20000000
215 #define FEC_IEVENT_GRA 0x10000000
216 #define FEC_IEVENT_TFINT 0x08000000
217 #define FEC_IEVENT_MII 0x00800000
218 #define FEC_IEVENT_LATE_COL 0x00200000
219 #define FEC_IEVENT_COL_RETRY_LIM 0x00100000
220 #define FEC_IEVENT_XFIFO_UN 0x00080000
221 #define FEC_IEVENT_XFIFO_ERROR 0x00040000
222 #define FEC_IEVENT_RFIFO_ERROR 0x00020000
224 #define FEC_IMASK_HBERR 0x80000000
225 #define FEC_IMASK_BABR 0x40000000
226 #define FEC_IMASK_BABT 0x20000000
227 #define FEC_IMASK_GRA 0x10000000
228 #define FEC_IMASK_MII 0x00800000
229 #define FEC_IMASK_LATE_COL 0x00200000
230 #define FEC_IMASK_COL_RETRY_LIM 0x00100000
231 #define FEC_IMASK_XFIFO_UN 0x00080000
232 #define FEC_IMASK_XFIFO_ERROR 0x00040000
233 #define FEC_IMASK_RFIFO_ERROR 0x00020000
236 #define FEC_IMASK_ENABLE (FEC_IMASK_HBERR | FEC_IMASK_BABR | \
237 FEC_IMASK_BABT | FEC_IMASK_GRA | FEC_IMASK_LATE_COL | \
238 FEC_IMASK_COL_RETRY_LIM | FEC_IMASK_XFIFO_UN | \
239 FEC_IMASK_XFIFO_ERROR | FEC_IMASK_RFIFO_ERROR)
241 #define FEC_RCNTRL_MAX_FL_SHIFT 16
242 #define FEC_RCNTRL_LOOP 0x01
243 #define FEC_RCNTRL_DRT 0x02
244 #define FEC_RCNTRL_MII_MODE 0x04
245 #define FEC_RCNTRL_PROM 0x08
246 #define FEC_RCNTRL_BC_REJ 0x10
247 #define FEC_RCNTRL_FCE 0x20
249 #define FEC_TCNTRL_GTS 0x00000001
250 #define FEC_TCNTRL_HBC 0x00000002
251 #define FEC_TCNTRL_FDEN 0x00000004
252 #define FEC_TCNTRL_TFC_PAUSE 0x00000008
253 #define FEC_TCNTRL_RFC_PAUSE 0x00000010
255 #define FEC_ECNTRL_RESET 0x00000001
256 #define FEC_ECNTRL_ETHER_EN 0x00000002
258 #define FEC_MII_DATA_ST 0x40000000
259 #define FEC_MII_DATA_OP_RD 0x20000000
260 #define FEC_MII_DATA_OP_WR 0x10000000
261 #define FEC_MII_DATA_PA_MSK 0x0f800000
262 #define FEC_MII_DATA_RA_MSK 0x007c0000
263 #define FEC_MII_DATA_TA 0x00020000
264 #define FEC_MII_DATA_DATAMSK 0x0000ffff
266 #define FEC_MII_READ_FRAME (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA)
267 #define FEC_MII_WRITE_FRAME (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | FEC_MII_DATA_TA)
269 #define FEC_MII_DATA_RA_SHIFT 0x12
270 #define FEC_MII_DATA_PA_SHIFT 0x17
272 #define FEC_PADDR2_TYPE 0x8808
274 #define FEC_OP_PAUSE_OPCODE 0x00010000
276 #define FEC_FIFO_WMRK_256B 0x3
278 #define FEC_FIFO_STATUS_ERR 0x00400000
279 #define FEC_FIFO_STATUS_UF 0x00200000
280 #define FEC_FIFO_STATUS_OF 0x00100000
282 #define FEC_FIFO_CNTRL_FRAME 0x08000000
283 #define FEC_FIFO_CNTRL_LTG_7 0x07000000
285 #define FEC_RESET_CNTRL_RESET_FIFO 0x02000000
286 #define FEC_RESET_CNTRL_ENABLE_IS_RESET 0x01000000
288 #define FEC_XMIT_FSM_APPEND_CRC 0x02000000
289 #define FEC_XMIT_FSM_ENABLE_CRC 0x01000000