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30 #define FINTEK_DRIVER_NAME "fintek-cir"
31 #define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver"
32 #define VENDOR_ID_FINTEK 0x1934
38 #define fit_pr(level, text, ...) \
39 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
41 #define fit_dbg(text, ...) \
44 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
46 #define fit_dbg_verbose(text, ...) \
49 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
51 #define fit_dbg_wake(text, ...) \
54 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
57 #define TX_BUF_LEN 256
115 #define BUF_PULSE_BIT 0x80
116 #define BUF_LEN_MASK 0x1f
117 #define BUF_SAMPLE_MASK 0x7f
119 #define BUF_COMMAND_HEADER 0x9f
120 #define BUF_COMMAND_MASK 0xe0
121 #define BUF_COMMAND_NULL 0x00
122 #define BUF_HW_CMD_HEADER 0xff
123 #define BUF_CMD_G_REVISION 0x0b
124 #define BUF_CMD_S_CARRIER 0x06
125 #define BUF_CMD_S_TIMEOUT 0x0c
126 #define BUF_CMD_SIG_END 0x01
127 #define BUF_CMD_S_TXMASK 0x08
128 #define BUF_CMD_S_RXSENSOR 0x14
129 #define BUF_RSP_PULSE_COUNT 0x15
131 #define CIR_SAMPLE_PERIOD 50
138 #define CR_INDEX_PORT 0x2e
139 #define CR_DATA_PORT 0x2f
142 #define CR_INDEX_PORT2 0x4e
143 #define CR_DATA_PORT2 0x4f
149 #define PORT_SEL_PORT_4E_EN 0x10
152 #define CONFIG_REG_ENABLE 0x87
153 #define CONFIG_REG_DISABLE 0xaa
156 #define CHIP_ID_HIGH_F71809U 0x04
157 #define CHIP_ID_LOW_F71809U 0x08
163 #define GCR_SOFTWARE_RESET 0x02
164 #define GCR_LOGICAL_DEV_NO 0x07
165 #define GCR_CHIP_ID_HI 0x20
166 #define GCR_CHIP_ID_LO 0x21
167 #define GCR_VENDOR_ID_HI 0x23
168 #define GCR_VENDOR_ID_LO 0x24
169 #define GCR_CONFIG_PORT_SEL 0x25
170 #define GCR_KBMOUSE_WAKEUP 0x27
172 #define LOGICAL_DEV_DISABLE 0x00
173 #define LOGICAL_DEV_ENABLE 0x01
176 #define LOGICAL_DEV_CIR_REV1 0x05
177 #define LOGICAL_DEV_CIR_REV2 0x08
180 #define CIR_CR_COMMAND_INDEX 0x04
181 #define CIR_CR_IRCS 0x05
184 #define CIR_CR_COMMAND_DATA 0x06
185 #define CIR_CR_CLASS 0x07
187 #define CIR_CR_DEV_EN 0x30
188 #define CIR_CR_BASE_ADDR_HI 0x60
189 #define CIR_CR_BASE_ADDR_LO 0x61
190 #define CIR_CR_IRQ_SEL 0x70
191 #define CIR_CR_PSOUT_STATUS 0xf1
192 #define CIR_CR_WAKE_KEY3_ADDR 0xf8
193 #define CIR_CR_WAKE_KEY3_CODE 0xf9
194 #define CIR_CR_WAKE_KEY3_DC 0xfa
195 #define CIR_CR_WAKE_CONTROL 0xfb
196 #define CIR_CR_WAKE_KEY12_ADDR 0xfc
197 #define CIR_CR_WAKE_KEY4_ADDR 0xfd
198 #define CIR_CR_WAKE_KEY5_ADDR 0xfe
200 #define CLASS_RX_ONLY 0xff
201 #define CLASS_RX_2TX 0x66
202 #define CLASS_RX_1TX 0x33
205 #define CIR_STATUS 0x00
206 #define CIR_RX_DATA 0x01
207 #define CIR_TX_CONTROL 0x02
208 #define CIR_TX_DATA 0x03
209 #define CIR_CONTROL 0x04
212 #define LOGICAL_DEV_ACPI 0x01
213 #define LDEV_ACPI_WAKE_EN_REG 0xe8
214 #define ACPI_WAKE_EN_CIR_BIT 0x04
216 #define LDEV_ACPI_PME_EN_REG 0xf0
217 #define LDEV_ACPI_PME_CLR_REG 0xf1
218 #define ACPI_PME_CIR_BIT 0x02
220 #define LDEV_ACPI_STATE_REG 0xf4
221 #define ACPI_STATE_CIR_BIT 0x20
231 #define CIR_STATUS_IRQ_EN 0x80
232 #define CIR_STATUS_TX_FINISH 0x08
233 #define CIR_STATUS_TX_UNDERRUN 0x04
234 #define CIR_STATUS_RX_TIMEOUT 0x02
235 #define CIR_STATUS_RX_RECEIVE 0x01
236 #define CIR_STATUS_IRQ_MASK 0x0f
243 #define CIR_TX_CONTROL_TX_START 0x80
244 #define CIR_TX_CONTROL_TX_END 0x40