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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
| #define A_GMAC_BACKOFF_SEED 0x5c |
Definition at line 200 of file fpga_defs.h.
| #define A_GMAC_CSR 0x30 |
Definition at line 103 of file fpga_defs.h.
| #define A_GMAC_IFS 0x34 |
Definition at line 179 of file fpga_defs.h.
| #define A_GMAC_JUMBO_FRAME_LEN 0x38 |
Definition at line 191 of file fpga_defs.h.
| #define A_GMAC_LNK_DLY 0x3c |
Definition at line 192 of file fpga_defs.h.
| #define A_GMAC_MACID_HI 0x2c |
Definition at line 102 of file fpga_defs.h.
| #define A_GMAC_MACID_LO 0x28 |
Definition at line 101 of file fpga_defs.h.
| #define A_GMAC_MCAST_HI 0x48 |
Definition at line 195 of file fpga_defs.h.
| #define A_GMAC_MCAST_LO 0x44 |
Definition at line 194 of file fpga_defs.h.
| #define A_GMAC_MCAST_MASK_HI 0x50 |
Definition at line 197 of file fpga_defs.h.
| #define A_GMAC_MCAST_MASK_LO 0x4c |
Definition at line 196 of file fpga_defs.h.
| #define A_GMAC_PAUSETIME 0x40 |
Definition at line 193 of file fpga_defs.h.
| #define A_GMAC_RMT_CNT 0x54 |
Definition at line 198 of file fpga_defs.h.
| #define A_GMAC_RMT_DATA 0x58 |
Definition at line 199 of file fpga_defs.h.
| #define A_GMAC_TXF_THRES 0x60 |
Definition at line 201 of file fpga_defs.h.
| #define A_MI0_ADDR 0xb08 |
Definition at line 85 of file fpga_defs.h.
| #define A_MI0_CLK 0xb00 |
Definition at line 51 of file fpga_defs.h.
| #define A_MI0_CSR 0xb04 |
Definition at line 63 of file fpga_defs.h.
| #define A_MI0_DATA_EXT 0xb0c |
Definition at line 97 of file fpga_defs.h.
| #define A_MI0_DATA_INT 0xb10 |
Definition at line 98 of file fpga_defs.h.
| #define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U) |
Definition at line 133 of file fpga_defs.h.
| #define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U) |
Definition at line 129 of file fpga_defs.h.
| #define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U) |
Definition at line 165 of file fpga_defs.h.
| #define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U) |
Definition at line 169 of file fpga_defs.h.
| #define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U) |
Definition at line 120 of file fpga_defs.h.
| #define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U) |
Definition at line 157 of file fpga_defs.h.
| #define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U) |
Definition at line 161 of file fpga_defs.h.
| #define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U) |
Definition at line 141 of file fpga_defs.h.
| #define F_MAC_PROMISC V_MAC_PROMISC(1U) |
Definition at line 137 of file fpga_defs.h.
| #define F_MAC_RESET V_MAC_RESET(1U) |
Definition at line 145 of file fpga_defs.h.
| #define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U) |
Definition at line 177 of file fpga_defs.h.
| #define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U) |
Definition at line 116 of file fpga_defs.h.
| #define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U) |
Definition at line 173 of file fpga_defs.h.
| #define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U) |
Definition at line 149 of file fpga_defs.h.
| #define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U) |
Definition at line 112 of file fpga_defs.h.
| #define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U) |
Definition at line 153 of file fpga_defs.h.
| #define F_MI0_BUSY V_MI0_BUSY(1U) |
Definition at line 79 of file fpga_defs.h.
| #define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U) |
Definition at line 67 of file fpga_defs.h.
| #define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U) |
Definition at line 75 of file fpga_defs.h.
| #define F_MI0_MDIO V_MI0_MDIO(1U) |
Definition at line 83 of file fpga_defs.h.
| #define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U) |
Definition at line 71 of file fpga_defs.h.
| #define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34 |
Definition at line 41 of file fpga_defs.h.
| #define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30 |
Definition at line 40 of file fpga_defs.h.
| #define FPGA_GMAC_ADDR_VERSION 0xA38 |
Definition at line 42 of file fpga_defs.h.
| #define FPGA_GMAC_INTERRUPT_PORT0 0x1 |
Definition at line 45 of file fpga_defs.h.
| #define FPGA_GMAC_INTERRUPT_PORT1 0x2 |
Definition at line 46 of file fpga_defs.h.
| #define FPGA_GMAC_INTERRUPT_PORT2 0x4 |
Definition at line 47 of file fpga_defs.h.
| #define FPGA_GMAC_INTERRUPT_PORT3 0x8 |
Definition at line 48 of file fpga_defs.h.
| #define FPGA_MC3_REG_INTRCAUSE 0xA24 |
Definition at line 34 of file fpga_defs.h.
| #define FPGA_MC3_REG_INTRENABLE 0xA20 |
Definition at line 33 of file fpga_defs.h.
| #define FPGA_MC3_REG_VERSION 0xA28 |
Definition at line 35 of file fpga_defs.h.
| #define FPGA_PCIX_ADDR_STAT 0xA0C |
Definition at line 11 of file fpga_defs.h.
| #define FPGA_PCIX_ADDR_VERSION 0xA08 |
Definition at line 10 of file fpga_defs.h.
| #define FPGA_PCIX_INTERRUPT_GMAC 0x10 |
Definition at line 18 of file fpga_defs.h.
| #define FPGA_PCIX_INTERRUPT_MC3 0x8 |
Definition at line 17 of file fpga_defs.h.
| #define FPGA_PCIX_INTERRUPT_PCIX 0x20 |
Definition at line 19 of file fpga_defs.h.
| #define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2 |
Definition at line 15 of file fpga_defs.h.
| #define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1 |
Definition at line 14 of file fpga_defs.h.
| #define FPGA_PCIX_INTERRUPT_TP 0x4 |
Definition at line 16 of file fpga_defs.h.
| #define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14 |
Definition at line 23 of file fpga_defs.h.
| #define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 |
Definition at line 22 of file fpga_defs.h.
| #define FPGA_TP_ADDR_VERSION 0xA18 |
Definition at line 24 of file fpga_defs.h.
| #define FPGA_TP_INTERRUPT_MC4 0x1 |
Definition at line 27 of file fpga_defs.h.
| #define FPGA_TP_INTERRUPT_MC5 0x2 |
Definition at line 28 of file fpga_defs.h.
| #define G_INTERFACE | ( | x | ) | (((x) >> S_INTERFACE) & M_INTERFACE) |
Definition at line 108 of file fpga_defs.h.
| #define G_MAC_IFS1 | ( | x | ) | (((x) >> S_MAC_IFS1) & M_MAC_IFS1) |
Definition at line 189 of file fpga_defs.h.
| #define G_MAC_IFS2 | ( | x | ) | (((x) >> S_MAC_IFS2) & M_MAC_IFS2) |
Definition at line 184 of file fpga_defs.h.
| #define G_MAC_SPEED | ( | x | ) | (((x) >> S_MAC_SPEED) & M_MAC_SPEED) |
Definition at line 125 of file fpga_defs.h.
| #define G_MI0_CLK_CNT | ( | x | ) | (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) |
Definition at line 61 of file fpga_defs.h.
| #define G_MI0_CLK_DIV | ( | x | ) | (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) |
Definition at line 56 of file fpga_defs.h.
| #define G_MI0_PHY_ADDR | ( | x | ) | (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) |
Definition at line 95 of file fpga_defs.h.
| #define G_MI0_PHY_REG_ADDR | ( | x | ) | (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) |
Definition at line 90 of file fpga_defs.h.
| #define G_TXF_READ_THRESHOLD | ( | x | ) | (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) |
Definition at line 206 of file fpga_defs.h.
| #define G_TXF_WRITE_THRESHOLD | ( | x | ) | (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) |
Definition at line 211 of file fpga_defs.h.
| #define M_INTERFACE 0x3 |
Definition at line 106 of file fpga_defs.h.
| #define M_MAC_IFS1 0x7f |
Definition at line 187 of file fpga_defs.h.
| #define M_MAC_IFS2 0x3f |
Definition at line 182 of file fpga_defs.h.
| #define M_MAC_SPEED 0x3 |
Definition at line 123 of file fpga_defs.h.
| #define M_MI0_CLK_CNT 0xff |
Definition at line 59 of file fpga_defs.h.
| #define M_MI0_CLK_DIV 0xff |
Definition at line 54 of file fpga_defs.h.
| #define M_MI0_PHY_ADDR 0x1f |
Definition at line 93 of file fpga_defs.h.
| #define M_MI0_PHY_REG_ADDR 0x1f |
Definition at line 88 of file fpga_defs.h.
| #define M_TXF_READ_THRESHOLD 0xff |
Definition at line 204 of file fpga_defs.h.
| #define M_TXF_WRITE_THRESHOLD 0xff |
Definition at line 209 of file fpga_defs.h.
| #define MAC_REG_ADDR | ( | idx, | |
| reg | |||
| ) | (MAC_REG_BASE + (idx) * 128 + (reg)) |
Definition at line 214 of file fpga_defs.h.
| #define MAC_REG_BASE 0x600 |
Definition at line 213 of file fpga_defs.h.
| #define MAC_REG_CASTLO | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) |
Definition at line 223 of file fpga_defs.h.
| #define MAC_REG_CASTMASKLO | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO) |
Definition at line 225 of file fpga_defs.h.
| #define MAC_REG_CSR | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_CSR) |
Definition at line 218 of file fpga_defs.h.
| #define MAC_REG_GMRANDBACKOFFSEED | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED) |
Definition at line 229 of file fpga_defs.h.
| #define MAC_REG_IDHI | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_MACID_HI) |
Definition at line 217 of file fpga_defs.h.
| #define MAC_REG_IDLO | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_MACID_LO) |
Definition at line 216 of file fpga_defs.h.
| #define MAC_REG_IFS | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_IFS) |
Definition at line 219 of file fpga_defs.h.
| #define MAC_REG_LARGEFRAMELENGTH | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) |
Definition at line 220 of file fpga_defs.h.
| #define MAC_REG_LINKDLY | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) |
Definition at line 221 of file fpga_defs.h.
| #define MAC_REG_MCASTHI | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) |
Definition at line 224 of file fpga_defs.h.
| #define MAC_REG_MCASTMASKHI | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI) |
Definition at line 226 of file fpga_defs.h.
| #define MAC_REG_PAUSETIME | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) |
Definition at line 222 of file fpga_defs.h.
| #define MAC_REG_RMCNT | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_RMT_CNT) |
Definition at line 227 of file fpga_defs.h.
| #define MAC_REG_RMDATA | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_RMT_DATA) |
Definition at line 228 of file fpga_defs.h.
| #define MAC_REG_TXFTHRESHOLDS | ( | idx | ) | MAC_REG_ADDR(idx, A_GMAC_TXF_THRES) |
Definition at line 230 of file fpga_defs.h.
| #define S_INTERFACE 0 |
Definition at line 105 of file fpga_defs.h.
| #define S_MAC_HALF_DUPLEX 8 |
Definition at line 131 of file fpga_defs.h.
| #define S_MAC_HD_FC_ENABLE 7 |
Definition at line 127 of file fpga_defs.h.
| #define S_MAC_IFS1 8 |
Definition at line 186 of file fpga_defs.h.
| #define S_MAC_IFS2 0 |
Definition at line 181 of file fpga_defs.h.
| #define S_MAC_ISL_ENABLE 16 |
Definition at line 163 of file fpga_defs.h.
| #define S_MAC_JUMBO_ENABLE 17 |
Definition at line 167 of file fpga_defs.h.
| #define S_MAC_LB_ENABLE 4 |
Definition at line 118 of file fpga_defs.h.
| #define S_MAC_LWM_ENABLE 14 |
Definition at line 155 of file fpga_defs.h.
| #define S_MAC_MAGIC_PKT_ENABLE 15 |
Definition at line 159 of file fpga_defs.h.
| #define S_MAC_MC_ENABLE 10 |
Definition at line 139 of file fpga_defs.h.
| #define S_MAC_PROMISC 9 |
Definition at line 135 of file fpga_defs.h.
| #define S_MAC_RESET 11 |
Definition at line 143 of file fpga_defs.h.
| #define S_MAC_RX_CRC_ENABLE 19 |
Definition at line 175 of file fpga_defs.h.
| #define S_MAC_RX_ENABLE 3 |
Definition at line 114 of file fpga_defs.h.
| #define S_MAC_RX_PAD_ENABLE 18 |
Definition at line 171 of file fpga_defs.h.
| #define S_MAC_RX_PAUSE_ENABLE 12 |
Definition at line 147 of file fpga_defs.h.
| #define S_MAC_SPEED 5 |
Definition at line 122 of file fpga_defs.h.
| #define S_MAC_TX_ENABLE 2 |
Definition at line 110 of file fpga_defs.h.
| #define S_MAC_TX_PAUSE_ENABLE 13 |
Definition at line 151 of file fpga_defs.h.
| #define S_MI0_BUSY 3 |
Definition at line 77 of file fpga_defs.h.
| #define S_MI0_CLK_CNT 8 |
Definition at line 58 of file fpga_defs.h.
| #define S_MI0_CLK_DIV 0 |
Definition at line 53 of file fpga_defs.h.
| #define S_MI0_CSR_POLL 0 |
Definition at line 65 of file fpga_defs.h.
| #define S_MI0_INTR_ENABLE 2 |
Definition at line 73 of file fpga_defs.h.
| #define S_MI0_MDIO 4 |
Definition at line 81 of file fpga_defs.h.
| #define S_MI0_PHY_ADDR 5 |
Definition at line 92 of file fpga_defs.h.
| #define S_MI0_PHY_REG_ADDR 0 |
Definition at line 87 of file fpga_defs.h.
| #define S_MI0_PREAMBLE 1 |
Definition at line 69 of file fpga_defs.h.
| #define S_TXF_READ_THRESHOLD 0 |
Definition at line 203 of file fpga_defs.h.
| #define S_TXF_WRITE_THRESHOLD 16 |
Definition at line 208 of file fpga_defs.h.
| #define V_INTERFACE | ( | x | ) | ((x) << S_INTERFACE) |
Definition at line 107 of file fpga_defs.h.
| #define V_MAC_HALF_DUPLEX | ( | x | ) | ((x) << S_MAC_HALF_DUPLEX) |
Definition at line 132 of file fpga_defs.h.
| #define V_MAC_HD_FC_ENABLE | ( | x | ) | ((x) << S_MAC_HD_FC_ENABLE) |
Definition at line 128 of file fpga_defs.h.
| #define V_MAC_IFS1 | ( | x | ) | ((x) << S_MAC_IFS1) |
Definition at line 188 of file fpga_defs.h.
| #define V_MAC_IFS2 | ( | x | ) | ((x) << S_MAC_IFS2) |
Definition at line 183 of file fpga_defs.h.
| #define V_MAC_ISL_ENABLE | ( | x | ) | ((x) << S_MAC_ISL_ENABLE) |
Definition at line 164 of file fpga_defs.h.
| #define V_MAC_JUMBO_ENABLE | ( | x | ) | ((x) << S_MAC_JUMBO_ENABLE) |
Definition at line 168 of file fpga_defs.h.
| #define V_MAC_LB_ENABLE | ( | x | ) | ((x) << S_MAC_LB_ENABLE) |
Definition at line 119 of file fpga_defs.h.
| #define V_MAC_LWM_ENABLE | ( | x | ) | ((x) << S_MAC_LWM_ENABLE) |
Definition at line 156 of file fpga_defs.h.
| #define V_MAC_MAGIC_PKT_ENABLE | ( | x | ) | ((x) << S_MAC_MAGIC_PKT_ENABLE) |
Definition at line 160 of file fpga_defs.h.
| #define V_MAC_MC_ENABLE | ( | x | ) | ((x) << S_MAC_MC_ENABLE) |
Definition at line 140 of file fpga_defs.h.
| #define V_MAC_PROMISC | ( | x | ) | ((x) << S_MAC_PROMISC) |
Definition at line 136 of file fpga_defs.h.
| #define V_MAC_RESET | ( | x | ) | ((x) << S_MAC_RESET) |
Definition at line 144 of file fpga_defs.h.
| #define V_MAC_RX_CRC_ENABLE | ( | x | ) | ((x) << S_MAC_RX_CRC_ENABLE) |
Definition at line 176 of file fpga_defs.h.
| #define V_MAC_RX_ENABLE | ( | x | ) | ((x) << S_MAC_RX_ENABLE) |
Definition at line 115 of file fpga_defs.h.
| #define V_MAC_RX_PAD_ENABLE | ( | x | ) | ((x) << S_MAC_RX_PAD_ENABLE) |
Definition at line 172 of file fpga_defs.h.
| #define V_MAC_RX_PAUSE_ENABLE | ( | x | ) | ((x) << S_MAC_RX_PAUSE_ENABLE) |
Definition at line 148 of file fpga_defs.h.
| #define V_MAC_SPEED | ( | x | ) | ((x) << S_MAC_SPEED) |
Definition at line 124 of file fpga_defs.h.
| #define V_MAC_TX_ENABLE | ( | x | ) | ((x) << S_MAC_TX_ENABLE) |
Definition at line 111 of file fpga_defs.h.
| #define V_MAC_TX_PAUSE_ENABLE | ( | x | ) | ((x) << S_MAC_TX_PAUSE_ENABLE) |
Definition at line 152 of file fpga_defs.h.
| #define V_MI0_BUSY | ( | x | ) | ((x) << S_MI0_BUSY) |
Definition at line 78 of file fpga_defs.h.
| #define V_MI0_CLK_CNT | ( | x | ) | ((x) << S_MI0_CLK_CNT) |
Definition at line 60 of file fpga_defs.h.
| #define V_MI0_CLK_DIV | ( | x | ) | ((x) << S_MI0_CLK_DIV) |
Definition at line 55 of file fpga_defs.h.
| #define V_MI0_CSR_POLL | ( | x | ) | ((x) << S_MI0_CSR_POLL) |
Definition at line 66 of file fpga_defs.h.
| #define V_MI0_INTR_ENABLE | ( | x | ) | ((x) << S_MI0_INTR_ENABLE) |
Definition at line 74 of file fpga_defs.h.
| #define V_MI0_MDIO | ( | x | ) | ((x) << S_MI0_MDIO) |
Definition at line 82 of file fpga_defs.h.
| #define V_MI0_PHY_ADDR | ( | x | ) | ((x) << S_MI0_PHY_ADDR) |
Definition at line 94 of file fpga_defs.h.
| #define V_MI0_PHY_REG_ADDR | ( | x | ) | ((x) << S_MI0_PHY_REG_ADDR) |
Definition at line 89 of file fpga_defs.h.
| #define V_MI0_PREAMBLE | ( | x | ) | ((x) << S_MI0_PREAMBLE) |
Definition at line 70 of file fpga_defs.h.
| #define V_TXF_READ_THRESHOLD | ( | x | ) | ((x) << S_TXF_READ_THRESHOLD) |
Definition at line 205 of file fpga_defs.h.
| #define V_TXF_WRITE_THRESHOLD | ( | x | ) | ((x) << S_TXF_WRITE_THRESHOLD) |
Definition at line 210 of file fpga_defs.h.
1.8.2