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fsl_otg.h
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1 /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
2  *
3  * This program is free software; you can redistribute it and/or modify it
4  * under the terms of the GNU General Public License as published by the
5  * Free Software Foundation; either version 2 of the License, or (at your
6  * option) any later version.
7  *
8  * This program is distributed in the hope that it will be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11  * General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License along
14  * with this program; if not, write to the Free Software Foundation, Inc.,
15  * 675 Mass Ave, Cambridge, MA 02139, USA.
16  */
17 
18 #include "otg_fsm.h"
19 #include <linux/usb/otg.h>
20 #include <linux/ioctl.h>
21 
22 /* USB Command Register Bit Masks */
23 #define USB_CMD_RUN_STOP (0x1<<0)
24 #define USB_CMD_CTRL_RESET (0x1<<1)
25 #define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
26 #define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
27 #define USB_CMD_INT_AA_DOORBELL (0x1<<6)
28 #define USB_CMD_ASP (0x3<<8)
29 #define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
30 #define USB_CMD_SUTW (0x1<<13)
31 #define USB_CMD_ATDTW (0x1<<14)
32 #define USB_CMD_ITC (0xFF<<16)
33 
34 /* bit 15,3,2 are frame list size */
35 #define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
36 #define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
37 #define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
38 #define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
39 #define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
40 #define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
41 #define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
42 #define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
43 
44 /* bit 9-8 are async schedule park mode count */
45 #define USB_CMD_ASP_00 (0x0<<8)
46 #define USB_CMD_ASP_01 (0x1<<8)
47 #define USB_CMD_ASP_10 (0x2<<8)
48 #define USB_CMD_ASP_11 (0x3<<8)
49 #define USB_CMD_ASP_BIT_POS (8)
50 
51 /* bit 23-16 are interrupt threshold control */
52 #define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
53 #define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
54 #define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
55 #define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
56 #define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
57 #define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
58 #define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
59 #define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
60 #define USB_CMD_ITC_BIT_POS (16)
61 
62 /* USB Status Register Bit Masks */
63 #define USB_STS_INT (0x1<<0)
64 #define USB_STS_ERR (0x1<<1)
65 #define USB_STS_PORT_CHANGE (0x1<<2)
66 #define USB_STS_FRM_LST_ROLL (0x1<<3)
67 #define USB_STS_SYS_ERR (0x1<<4)
68 #define USB_STS_IAA (0x1<<5)
69 #define USB_STS_RESET_RECEIVED (0x1<<6)
70 #define USB_STS_SOF (0x1<<7)
71 #define USB_STS_DCSUSPEND (0x1<<8)
72 #define USB_STS_HC_HALTED (0x1<<12)
73 #define USB_STS_RCL (0x1<<13)
74 #define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
75 #define USB_STS_ASYNC_SCHEDULE (0x1<<15)
76 
77 /* USB Interrupt Enable Register Bit Masks */
78 #define USB_INTR_INT_EN (0x1<<0)
79 #define USB_INTR_ERR_INT_EN (0x1<<1)
80 #define USB_INTR_PC_DETECT_EN (0x1<<2)
81 #define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
82 #define USB_INTR_SYS_ERR_EN (0x1<<4)
83 #define USB_INTR_ASYN_ADV_EN (0x1<<5)
84 #define USB_INTR_RESET_EN (0x1<<6)
85 #define USB_INTR_SOF_EN (0x1<<7)
86 #define USB_INTR_DEVICE_SUSPEND (0x1<<8)
87 
88 /* Device Address bit masks */
89 #define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
90 #define USB_DEVICE_ADDRESS_BIT_POS (25)
91 /* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
92 #define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
93 #define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
94 #define PORTSC_PORT_ENABLE (0x1<<2)
95 #define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
96 #define PORTSC_OVER_CURRENT_ACT (0x1<<4)
97 #define PORTSC_OVER_CUURENT_CHG (0x1<<5)
98 #define PORTSC_PORT_FORCE_RESUME (0x1<<6)
99 #define PORTSC_PORT_SUSPEND (0x1<<7)
100 #define PORTSC_PORT_RESET (0x1<<8)
101 #define PORTSC_LINE_STATUS_BITS (0x3<<10)
102 #define PORTSC_PORT_POWER (0x1<<12)
103 #define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
104 #define PORTSC_PORT_TEST_CTRL (0xF<<16)
105 #define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
106 #define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
107 #define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
108 #define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
109 #define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
110 #define PORTSC_PORT_SPEED_MASK (0x3<<26)
111 #define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
112 #define PORTSC_PHY_TYPE_SEL (0x3<<30)
113 /* bit 11-10 are line status */
114 #define PORTSC_LINE_STATUS_SE0 (0x0<<10)
115 #define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
116 #define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
117 #define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
118 #define PORTSC_LINE_STATUS_BIT_POS (10)
119 
120 /* bit 15-14 are port indicator control */
121 #define PORTSC_PIC_OFF (0x0<<14)
122 #define PORTSC_PIC_AMBER (0x1<<14)
123 #define PORTSC_PIC_GREEN (0x2<<14)
124 #define PORTSC_PIC_UNDEF (0x3<<14)
125 #define PORTSC_PIC_BIT_POS (14)
126 
127 /* bit 19-16 are port test control */
128 #define PORTSC_PTC_DISABLE (0x0<<16)
129 #define PORTSC_PTC_JSTATE (0x1<<16)
130 #define PORTSC_PTC_KSTATE (0x2<<16)
131 #define PORTSC_PTC_SEQNAK (0x3<<16)
132 #define PORTSC_PTC_PACKET (0x4<<16)
133 #define PORTSC_PTC_FORCE_EN (0x5<<16)
134 #define PORTSC_PTC_BIT_POS (16)
135 
136 /* bit 27-26 are port speed */
137 #define PORTSC_PORT_SPEED_FULL (0x0<<26)
138 #define PORTSC_PORT_SPEED_LOW (0x1<<26)
139 #define PORTSC_PORT_SPEED_HIGH (0x2<<26)
140 #define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
141 #define PORTSC_SPEED_BIT_POS (26)
142 
143 /* bit 28 is parallel transceiver width for UTMI interface */
144 #define PORTSC_PTW (0x1<<28)
145 #define PORTSC_PTW_8BIT (0x0<<28)
146 #define PORTSC_PTW_16BIT (0x1<<28)
147 
148 /* bit 31-30 are port transceiver select */
149 #define PORTSC_PTS_UTMI (0x0<<30)
150 #define PORTSC_PTS_ULPI (0x2<<30)
151 #define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
152 #define PORTSC_PTS_BIT_POS (30)
153 
154 #define PORTSC_W1C_BITS \
155  (PORTSC_CONNECT_STATUS_CHANGE | \
156  PORTSC_PORT_EN_DIS_CHANGE | \
157  PORTSC_OVER_CUURENT_CHG)
158 
159 /* OTG Status Control Register Bit Masks */
160 #define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
161 #define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
162 #define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
163 #define OTGSC_CTRL_DATA_PULSING (0x1<<4)
164 #define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
165 #define OTGSC_HA_DATA_PULSE (0x1<<6)
166 #define OTGSC_HA_BA (0x1<<7)
167 #define OTGSC_STS_USB_ID (0x1<<8)
168 #define OTGSC_STS_A_VBUS_VALID (0x1<<9)
169 #define OTGSC_STS_A_SESSION_VALID (0x1<<10)
170 #define OTGSC_STS_B_SESSION_VALID (0x1<<11)
171 #define OTGSC_STS_B_SESSION_END (0x1<<12)
172 #define OTGSC_STS_1MS_TOGGLE (0x1<<13)
173 #define OTGSC_STS_DATA_PULSING (0x1<<14)
174 #define OTGSC_INTSTS_USB_ID (0x1<<16)
175 #define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
176 #define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
177 #define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
178 #define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
179 #define OTGSC_INTSTS_1MS (0x1<<21)
180 #define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
181 #define OTGSC_INTR_USB_ID_EN (0x1<<24)
182 #define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
183 #define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
184 #define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
185 #define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
186 #define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
187 #define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
188 #define OTGSC_INTSTS_MASK (0x00ff0000)
189 
190 /* USB MODE Register Bit Masks */
191 #define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
192 #define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
193 #define USB_MODE_CTRL_MODE_HOST (0x3<<0)
194 #define USB_MODE_CTRL_MODE_RSV (0x1<<0)
195 #define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
196 #define USB_MODE_STREAM_DISABLE (0x1<<4)
197 #define USB_MODE_ES (0x1<<2) /* Endian Select */
198 
199 /* control Register Bit Masks */
200 #define USB_CTRL_IOENB (0x1<<2)
201 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
202 
203 /* BCSR5 */
204 #define BCSR5_INT_USB (0x02)
205 
206 /* USB module clk cfg */
207 #define SCCR_OFFS (0xA08)
208 #define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
209 #define SCCR_USB_MPHCM_11 (0x00c00000)
210 #define SCCR_USB_MPHCM_01 (0x00400000)
211 #define SCCR_USB_MPHCM_10 (0x00800000)
212 #define SCCR_USB_DRCM_11 (0x00300000)
213 #define SCCR_USB_DRCM_01 (0x00100000)
214 #define SCCR_USB_DRCM_10 (0x00200000)
215 
216 #define SICRL_OFFS (0x114)
217 #define SICRL_USB0 (0x40000000)
218 #define SICRL_USB1 (0x20000000)
219 
220 #define SICRH_OFFS (0x118)
221 #define SICRH_USB_UTMI (0x00020000)
222 
223 /* OTG interrupt enable bit masks */
224 #define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
225  (OTGSC_INTR_USB_ID_EN | \
226  OTGSC_INTR_1MS_TIMER_EN | \
227  OTGSC_INTR_A_VBUS_VALID_EN | \
228  OTGSC_INTR_A_SESSION_VALID_EN | \
229  OTGSC_INTR_B_SESSION_VALID_EN | \
230  OTGSC_INTR_B_SESSION_END_EN | \
231  OTGSC_INTR_DATA_PULSING_EN)
232 
233 /* OTG interrupt status bit masks */
234 #define OTGSC_INTERRUPT_STATUS_BITS_MASK \
235  (OTGSC_INTSTS_USB_ID | \
236  OTGSC_INTR_1MS_TIMER_EN | \
237  OTGSC_INTSTS_A_VBUS_VALID | \
238  OTGSC_INTSTS_A_SESSION_VALID | \
239  OTGSC_INTSTS_B_SESSION_VALID | \
240  OTGSC_INTSTS_B_SESSION_END | \
241  OTGSC_INTSTS_DATA_PULSING)
242 
243 /*
244  * A-DEVICE timing constants
245  */
246 
247 /* Wait for VBUS Rise */
248 #define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
249 
250 /* Wait for B-Connect */
251 #define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
252  * This is only used to get out of
253  * OTG_STATE_A_WAIT_BCON state if there was
254  * no connection for these many milliseconds
255  */
256 
257 /* A-Idle to B-Disconnect */
258 /* It is necessary for this timer to be more than 750 ms because of a bug in OPT
259  * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
260  * in the test description
261  */
262 #define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
263 
264 /* B-Idle to A-Disconnect */
265 #define TA_BIDL_ADIS (12) /* 3 to 200 ms */
266 
267 /* B-device timing constants */
268 
269 
270 /* Data-Line Pulse Time*/
271 #define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
272 #define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
273 #define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
274 
275 /* SRP Initiate Time */
276 #define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
277 
278 /* SRP Fail Time */
279 #define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
280 
281 /* SRP result wait time */
282 #define TB_SRP_WAIT (60)
283 
284 /* VBus time */
285 #define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
286 
287 /* Discharge time */
288 /* This time should be less than 10ms. It varies from system to system. */
289 #define TB_VBUS_DSCHRG (8)
290 
291 /* A-SE0 to B-Reset */
292 #define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
293 
294 /* A bus suspend timer before we can switch to b_wait_aconn */
295 #define TB_A_SUSPEND (7)
296 #define TB_BUS_RESUME (12)
297 
298 /* SE0 Time Before SRP */
299 #define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
300 
301 #define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
302 
303 struct usb_dr_mmap {
304  /* Capability register */
305  u8 res1[256];
306  u16 caplength; /* Capability Register Length */
307  u16 hciversion; /* Host Controller Interface Version */
308  u32 hcsparams; /* Host Controller Structual Parameters */
309  u32 hccparams; /* Host Controller Capability Parameters */
310  u8 res2[20];
311  u32 dciversion; /* Device Controller Interface Version */
312  u32 dccparams; /* Device Controller Capability Parameters */
313  u8 res3[24];
314  /* Operation register */
315  u32 usbcmd; /* USB Command Register */
316  u32 usbsts; /* USB Status Register */
317  u32 usbintr; /* USB Interrupt Enable Register */
318  u32 frindex; /* Frame Index Register */
319  u8 res4[4];
320  u32 deviceaddr; /* Device Address */
321  u32 endpointlistaddr; /* Endpoint List Address Register */
322  u8 res5[4];
323  u32 burstsize; /* Master Interface Data Burst Size Register */
324  u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
325  u8 res6[8];
326  u32 ulpiview; /* ULPI register access */
327  u8 res7[12];
328  u32 configflag; /* Configure Flag Register */
329  u32 portsc; /* Port 1 Status and Control Register */
330  u8 res8[28];
331  u32 otgsc; /* On-The-Go Status and Control */
332  u32 usbmode; /* USB Mode Register */
333  u32 endptsetupstat; /* Endpoint Setup Status Register */
334  u32 endpointprime; /* Endpoint Initialization Register */
335  u32 endptflush; /* Endpoint Flush Register */
336  u32 endptstatus; /* Endpoint Status Register */
337  u32 endptcomplete; /* Endpoint Complete Register */
338  u32 endptctrl[6]; /* Endpoint Control Registers */
339  u8 res9[552];
340  u32 snoop1;
341  u32 snoop2;
342  u32 age_cnt_thresh; /* Age Count Threshold Register */
343  u32 pri_ctrl; /* Priority Control Register */
344  u32 si_ctrl; /* System Interface Control Register */
345  u8 res10[236];
346  u32 control; /* General Purpose Control Register */
347 };
348 
349 struct fsl_otg_timer {
350  unsigned long expires; /* Number of count increase to timeout */
351  unsigned long count; /* Tick counter */
352  void (*function)(unsigned long); /* Timeout function */
353  unsigned long data; /* Data passed to function */
354  struct list_head list;
355 };
356 
357 inline struct fsl_otg_timer *otg_timer_initializer
358 (void (*function)(unsigned long), unsigned long expires, unsigned long data)
359 {
360  struct fsl_otg_timer *timer;
361 
362  timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
363  if (!timer)
364  return NULL;
365  timer->function = function;
366  timer->expires = expires;
367  timer->data = data;
368  return timer;
369 }
370 
371 struct fsl_otg {
372  struct usb_phy phy;
373  struct otg_fsm fsm;
374  struct usb_dr_mmap *dr_mem_map;
375  struct delayed_work otg_event;
376 
377  /* used for usb host */
378  struct work_struct work_wq;
379  u8 host_working;
380 
381  int irq;
382 };
383 
384 struct fsl_otg_config {
385  u8 otg_port;
386 };
387 
388 /* For SRP and HNP handle */
389 #define FSL_OTG_MAJOR 240
390 #define FSL_OTG_NAME "fsl-usb2-otg"
391 /* Command to OTG driver ioctl */
392 #define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
393 /* if otg work as host, it should return 1, otherwise return 0 */
394 #define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
395 #define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
396 #define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
397 #define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
398 #define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
399 #define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
400 #define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
401 #define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
402 #define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
403 
404 void fsl_otg_add_timer(void *timer);
405 void fsl_otg_del_timer(void *timer);
406 void fsl_otg_pulse_vbus(void);
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