|
| #define | USB_CMD_RUN_STOP (0x1<<0) |
| |
| #define | USB_CMD_CTRL_RESET (0x1<<1) |
| |
| #define | USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4) |
| |
| #define | USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5) |
| |
| #define | USB_CMD_INT_AA_DOORBELL (0x1<<6) |
| |
| #define | USB_CMD_ASP (0x3<<8) |
| |
| #define | USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11) |
| |
| #define | USB_CMD_SUTW (0x1<<13) |
| |
| #define | USB_CMD_ATDTW (0x1<<14) |
| |
| #define | USB_CMD_ITC (0xFF<<16) |
| |
| #define | USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2) |
| |
| #define | USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) |
| |
| #define | USB_CMD_ASP_00 (0x0<<8) |
| |
| #define | USB_CMD_ASP_01 (0x1<<8) |
| |
| #define | USB_CMD_ASP_10 (0x2<<8) |
| |
| #define | USB_CMD_ASP_11 (0x3<<8) |
| |
| #define | USB_CMD_ASP_BIT_POS (8) |
| |
| #define | USB_CMD_ITC_NO_THRESHOLD (0x00<<16) |
| |
| #define | USB_CMD_ITC_1_MICRO_FRM (0x01<<16) |
| |
| #define | USB_CMD_ITC_2_MICRO_FRM (0x02<<16) |
| |
| #define | USB_CMD_ITC_4_MICRO_FRM (0x04<<16) |
| |
| #define | USB_CMD_ITC_8_MICRO_FRM (0x08<<16) |
| |
| #define | USB_CMD_ITC_16_MICRO_FRM (0x10<<16) |
| |
| #define | USB_CMD_ITC_32_MICRO_FRM (0x20<<16) |
| |
| #define | USB_CMD_ITC_64_MICRO_FRM (0x40<<16) |
| |
| #define | USB_CMD_ITC_BIT_POS (16) |
| |
| #define | USB_STS_INT (0x1<<0) |
| |
| #define | USB_STS_ERR (0x1<<1) |
| |
| #define | USB_STS_PORT_CHANGE (0x1<<2) |
| |
| #define | USB_STS_FRM_LST_ROLL (0x1<<3) |
| |
| #define | USB_STS_SYS_ERR (0x1<<4) |
| |
| #define | USB_STS_IAA (0x1<<5) |
| |
| #define | USB_STS_RESET_RECEIVED (0x1<<6) |
| |
| #define | USB_STS_SOF (0x1<<7) |
| |
| #define | USB_STS_DCSUSPEND (0x1<<8) |
| |
| #define | USB_STS_HC_HALTED (0x1<<12) |
| |
| #define | USB_STS_RCL (0x1<<13) |
| |
| #define | USB_STS_PERIODIC_SCHEDULE (0x1<<14) |
| |
| #define | USB_STS_ASYNC_SCHEDULE (0x1<<15) |
| |
| #define | USB_INTR_INT_EN (0x1<<0) |
| |
| #define | USB_INTR_ERR_INT_EN (0x1<<1) |
| |
| #define | USB_INTR_PC_DETECT_EN (0x1<<2) |
| |
| #define | USB_INTR_FRM_LST_ROLL_EN (0x1<<3) |
| |
| #define | USB_INTR_SYS_ERR_EN (0x1<<4) |
| |
| #define | USB_INTR_ASYN_ADV_EN (0x1<<5) |
| |
| #define | USB_INTR_RESET_EN (0x1<<6) |
| |
| #define | USB_INTR_SOF_EN (0x1<<7) |
| |
| #define | USB_INTR_DEVICE_SUSPEND (0x1<<8) |
| |
| #define | USB_DEVICE_ADDRESS_MASK (0x7F<<25) |
| |
| #define | USB_DEVICE_ADDRESS_BIT_POS (25) |
| |
| #define | PORTSC_CURRENT_CONNECT_STATUS (0x1<<0) |
| |
| #define | PORTSC_CONNECT_STATUS_CHANGE (0x1<<1) |
| |
| #define | PORTSC_PORT_ENABLE (0x1<<2) |
| |
| #define | PORTSC_PORT_EN_DIS_CHANGE (0x1<<3) |
| |
| #define | PORTSC_OVER_CURRENT_ACT (0x1<<4) |
| |
| #define | PORTSC_OVER_CUURENT_CHG (0x1<<5) |
| |
| #define | PORTSC_PORT_FORCE_RESUME (0x1<<6) |
| |
| #define | PORTSC_PORT_SUSPEND (0x1<<7) |
| |
| #define | PORTSC_PORT_RESET (0x1<<8) |
| |
| #define | PORTSC_LINE_STATUS_BITS (0x3<<10) |
| |
| #define | PORTSC_PORT_POWER (0x1<<12) |
| |
| #define | PORTSC_PORT_INDICTOR_CTRL (0x3<<14) |
| |
| #define | PORTSC_PORT_TEST_CTRL (0xF<<16) |
| |
| #define | PORTSC_WAKE_ON_CONNECT_EN (0x1<<20) |
| |
| #define | PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21) |
| |
| #define | PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22) |
| |
| #define | PORTSC_PHY_LOW_POWER_SPD (0x1<<23) |
| |
| #define | PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24) |
| |
| #define | PORTSC_PORT_SPEED_MASK (0x3<<26) |
| |
| #define | PORTSC_TRANSCEIVER_WIDTH (0x1<<28) |
| |
| #define | PORTSC_PHY_TYPE_SEL (0x3<<30) |
| |
| #define | PORTSC_LINE_STATUS_SE0 (0x0<<10) |
| |
| #define | PORTSC_LINE_STATUS_JSTATE (0x1<<10) |
| |
| #define | PORTSC_LINE_STATUS_KSTATE (0x2<<10) |
| |
| #define | PORTSC_LINE_STATUS_UNDEF (0x3<<10) |
| |
| #define | PORTSC_LINE_STATUS_BIT_POS (10) |
| |
| #define | PORTSC_PIC_OFF (0x0<<14) |
| |
| #define | PORTSC_PIC_AMBER (0x1<<14) |
| |
| #define | PORTSC_PIC_GREEN (0x2<<14) |
| |
| #define | PORTSC_PIC_UNDEF (0x3<<14) |
| |
| #define | PORTSC_PIC_BIT_POS (14) |
| |
| #define | PORTSC_PTC_DISABLE (0x0<<16) |
| |
| #define | PORTSC_PTC_JSTATE (0x1<<16) |
| |
| #define | PORTSC_PTC_KSTATE (0x2<<16) |
| |
| #define | PORTSC_PTC_SEQNAK (0x3<<16) |
| |
| #define | PORTSC_PTC_PACKET (0x4<<16) |
| |
| #define | PORTSC_PTC_FORCE_EN (0x5<<16) |
| |
| #define | PORTSC_PTC_BIT_POS (16) |
| |
| #define | PORTSC_PORT_SPEED_FULL (0x0<<26) |
| |
| #define | PORTSC_PORT_SPEED_LOW (0x1<<26) |
| |
| #define | PORTSC_PORT_SPEED_HIGH (0x2<<26) |
| |
| #define | PORTSC_PORT_SPEED_UNDEF (0x3<<26) |
| |
| #define | PORTSC_SPEED_BIT_POS (26) |
| |
| #define | PORTSC_PTW (0x1<<28) |
| |
| #define | PORTSC_PTW_8BIT (0x0<<28) |
| |
| #define | PORTSC_PTW_16BIT (0x1<<28) |
| |
| #define | PORTSC_PTS_UTMI (0x0<<30) |
| |
| #define | PORTSC_PTS_ULPI (0x2<<30) |
| |
| #define | PORTSC_PTS_FSLS_SERIAL (0x3<<30) |
| |
| #define | PORTSC_PTS_BIT_POS (30) |
| |
| #define | PORTSC_W1C_BITS |
| |
| #define | OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0) |
| |
| #define | OTGSC_CTRL_VBUS_CHARGE (0x1<<1) |
| |
| #define | OTGSC_CTRL_OTG_TERMINATION (0x1<<3) |
| |
| #define | OTGSC_CTRL_DATA_PULSING (0x1<<4) |
| |
| #define | OTGSC_CTRL_ID_PULL_EN (0x1<<5) |
| |
| #define | OTGSC_HA_DATA_PULSE (0x1<<6) |
| |
| #define | OTGSC_HA_BA (0x1<<7) |
| |
| #define | OTGSC_STS_USB_ID (0x1<<8) |
| |
| #define | OTGSC_STS_A_VBUS_VALID (0x1<<9) |
| |
| #define | OTGSC_STS_A_SESSION_VALID (0x1<<10) |
| |
| #define | OTGSC_STS_B_SESSION_VALID (0x1<<11) |
| |
| #define | OTGSC_STS_B_SESSION_END (0x1<<12) |
| |
| #define | OTGSC_STS_1MS_TOGGLE (0x1<<13) |
| |
| #define | OTGSC_STS_DATA_PULSING (0x1<<14) |
| |
| #define | OTGSC_INTSTS_USB_ID (0x1<<16) |
| |
| #define | OTGSC_INTSTS_A_VBUS_VALID (0x1<<17) |
| |
| #define | OTGSC_INTSTS_A_SESSION_VALID (0x1<<18) |
| |
| #define | OTGSC_INTSTS_B_SESSION_VALID (0x1<<19) |
| |
| #define | OTGSC_INTSTS_B_SESSION_END (0x1<<20) |
| |
| #define | OTGSC_INTSTS_1MS (0x1<<21) |
| |
| #define | OTGSC_INTSTS_DATA_PULSING (0x1<<22) |
| |
| #define | OTGSC_INTR_USB_ID_EN (0x1<<24) |
| |
| #define | OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25) |
| |
| #define | OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26) |
| |
| #define | OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27) |
| |
| #define | OTGSC_INTR_B_SESSION_END_EN (0x1<<28) |
| |
| #define | OTGSC_INTR_1MS_TIMER_EN (0x1<<29) |
| |
| #define | OTGSC_INTR_DATA_PULSING_EN (0x1<<30) |
| |
| #define | OTGSC_INTSTS_MASK (0x00ff0000) |
| |
| #define | USB_MODE_CTRL_MODE_IDLE (0x0<<0) |
| |
| #define | USB_MODE_CTRL_MODE_DEVICE (0x2<<0) |
| |
| #define | USB_MODE_CTRL_MODE_HOST (0x3<<0) |
| |
| #define | USB_MODE_CTRL_MODE_RSV (0x1<<0) |
| |
| #define | USB_MODE_SETUP_LOCK_OFF (0x1<<3) |
| |
| #define | USB_MODE_STREAM_DISABLE (0x1<<4) |
| |
| #define | USB_MODE_ES (0x1<<2) /* Endian Select */ |
| |
| #define | USB_CTRL_IOENB (0x1<<2) |
| |
| #define | USB_CTRL_ULPI_INT0EN (0x1<<0) |
| |
| #define | BCSR5_INT_USB (0x02) |
| |
| #define | SCCR_OFFS (0xA08) |
| |
| #define | SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */ |
| |
| #define | SCCR_USB_MPHCM_11 (0x00c00000) |
| |
| #define | SCCR_USB_MPHCM_01 (0x00400000) |
| |
| #define | SCCR_USB_MPHCM_10 (0x00800000) |
| |
| #define | SCCR_USB_DRCM_11 (0x00300000) |
| |
| #define | SCCR_USB_DRCM_01 (0x00100000) |
| |
| #define | SCCR_USB_DRCM_10 (0x00200000) |
| |
| #define | SICRL_OFFS (0x114) |
| |
| #define | SICRL_USB0 (0x40000000) |
| |
| #define | SICRL_USB1 (0x20000000) |
| |
| #define | SICRH_OFFS (0x118) |
| |
| #define | SICRH_USB_UTMI (0x00020000) |
| |
| #define | OTGSC_INTERRUPT_ENABLE_BITS_MASK |
| |
| #define | OTGSC_INTERRUPT_STATUS_BITS_MASK |
| |
| #define | TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */ |
| |
| #define | TA_WAIT_BCON |
| |
| #define | TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */ |
| |
| #define | TA_BIDL_ADIS (12) /* 3 to 200 ms */ |
| |
| #define | TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */ |
| |
| #define | TB_DATA_PLS_MIN (5) /* minimum 5 ms */ |
| |
| #define | TB_DATA_PLS_MAX (10) /* maximum 10 ms */ |
| |
| #define | TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */ |
| |
| #define | TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/ |
| |
| #define | TB_SRP_WAIT (60) |
| |
| #define | TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */ |
| |
| #define | TB_VBUS_DSCHRG (8) |
| |
| #define | TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */ |
| |
| #define | TB_A_SUSPEND (7) |
| |
| #define | TB_BUS_RESUME (12) |
| |
| #define | TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */ |
| |
| #define | SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate) |
| |
| #define | FSL_OTG_MAJOR 240 |
| |
| #define | FSL_OTG_NAME "fsl-usb2-otg" |
| |
| #define | OTG_IOCTL_MAGIC FSL_OTG_MAJOR |
| |
| #define | GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int) |
| |
| #define | SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int) |
| |
| #define | SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int) |
| |
| #define | SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int) |
| |
| #define | SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int) |
| |
| #define | GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int) |
| |
| #define | GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int) |
| |
| #define | GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int) |
| |
| #define | GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int) |
| |
1.8.2