Go to the source code of this file.
| #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ |
Definition at line 27 of file gg2.h.
| #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ |
Definition at line 25 of file gg2.h.
| #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ |
Definition at line 24 of file gg2.h.
| #define GG2_PCI_ADDR_MAP 0x5c /* Address map */ |
Definition at line 43 of file gg2.h.
| #define GG2_PCI_BUSNO 0x40 /* Bus number */ |
Definition at line 39 of file gg2.h.
| #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ |
Definition at line 47 of file gg2.h.
| #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ |
Definition at line 26 of file gg2.h.
| #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ |
Definition at line 41 of file gg2.h.
| #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ |
Definition at line 48 of file gg2.h.
| #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ |
Definition at line 49 of file gg2.h.
| #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ |
Definition at line 50 of file gg2.h.
| #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ |
Definition at line 51 of file gg2.h.
| #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ |
Definition at line 52 of file gg2.h.
| #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ |
Definition at line 53 of file gg2.h.
| #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ |
Definition at line 56 of file gg2.h.
| #define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ |
Definition at line 54 of file gg2.h.
| #define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ |
Definition at line 55 of file gg2.h.
| #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ |
Definition at line 57 of file gg2.h.
| #define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ |
Definition at line 58 of file gg2.h.
| #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ |
Definition at line 23 of file gg2.h.
| #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ |
Definition at line 44 of file gg2.h.
| #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ |
Definition at line 42 of file gg2.h.
| #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ |
Definition at line 45 of file gg2.h.
| #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ |
Definition at line 46 of file gg2.h.
| #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ |
Definition at line 40 of file gg2.h.
| #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ |
Definition at line 29 of file gg2.h.
| #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ |
Definition at line 30 of file gg2.h.
Definition at line 26 of file pci.c.
1.8.2