Go to the documentation of this file.
22 #ifndef __PNX8550_GLB_H
23 #define __PNX8550_GLB_H
25 #define PNX8550_GLB1_BASE 0xBBE63000
26 #define PNX8550_GLB2_BASE 0xBBE4d000
27 #define PNX8550_RESET_BASE 0xBBE60000
30 #define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
36 #define PNX8550_GLB_DAC_PD 0x2
41 #define PNX8550_GLB_ENABLE_INTA_O 0x1
44 #define PNX8550_PCIMEM 0x12000000
45 #define PNX8550_PCIMEM_SIZE 0x08000000
46 #define PNX8550_PCIIO 0x1c000000
47 #define PNX8550_PCIIO_SIZE 0x02000000
49 #define PNX8550_PORT_BASE KSEG1
52 #define PNX8550_GPIO_BASE 0x1Be00000
54 #define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
55 #define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
56 #define PNX8550_GPIO_MC_31_BIT 30
57 #define PNX8550_GPIO_MC_30_BIT 28
58 #define PNX8550_GPIO_MC_29_BIT 26
59 #define PNX8550_GPIO_MC_28_BIT 24
60 #define PNX8550_GPIO_MC_27_BIT 22
61 #define PNX8550_GPIO_MC_26_BIT 20
62 #define PNX8550_GPIO_MC_25_BIT 18
63 #define PNX8550_GPIO_MC_24_BIT 16
64 #define PNX8550_GPIO_MC_23_BIT 14
65 #define PNX8550_GPIO_MC_22_BIT 12
66 #define PNX8550_GPIO_MC_21_BIT 10
67 #define PNX8550_GPIO_MC_20_BIT 8
68 #define PNX8550_GPIO_MC_19_BIT 6
69 #define PNX8550_GPIO_MC_18_BIT 4
70 #define PNX8550_GPIO_MC_17_BIT 2
71 #define PNX8550_GPIO_MC_16_BIT 0
73 #define PNX8550_GPIO_MODE_PRIMOP 0x1
74 #define PNX8550_GPIO_MODE_NO_OPENDR 0x2
75 #define PNX8550_GPIO_MODE_OPENDR 0x3
78 #define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
79 #define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
80 #define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
82 #define PNX8550_RST_REL_MIPS_RST_N 0x8
83 #define PNX8550_RST_DO_SW_RST 0x4
84 #define PNX8550_RST_REL_SYS_RST_OUT 0x2
85 #define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1