Macros
#define	HDMI_CTRL_BASE(x) ((x) + 0x00000000)

#define	HDMI_CORE_BASE(x) ((x) + 0x00010000)

#define	HDMI_I2S_BASE(x) ((x) + 0x00040000)

#define	HDMI_TG_BASE(x) ((x) + 0x00050000)

#define	HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)

#define	HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)

#define	HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)

#define	HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)

#define	HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018)

#define	HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C)

#define	HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)

#define	HDMI_CON_0 HDMI_CORE_BASE(0x0000)

#define	HDMI_CON_1 HDMI_CORE_BASE(0x0004)

#define	HDMI_CON_2 HDMI_CORE_BASE(0x0008)

#define	HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)

#define	HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014)

#define	HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)

#define	HDMI_HPD HDMI_CORE_BASE(0x0030)

#define	HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)

#define	HDMI_ENC_EN HDMI_CORE_BASE(0x0044)

#define	HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)

#define	HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)

#define	HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)

#define	HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)

#define	HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)

#define	HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0)

#define	HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4)

#define	HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8)

#define	HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)

#define	HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)

#define	HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)

#define	HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)

#define	HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)

#define	HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)

#define	HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)

#define	HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)

#define	HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)

#define	HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)

#define	HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)

#define	HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)

#define	HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)

#define	HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)

#define	HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)

#define	HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)

#define	HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)

#define	HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)

#define	HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)

#define	HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)

#define	HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180)

#define	HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300)

#define	HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))

#define	HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0)

#define	HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)

#define	HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8)

#define	HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360)

#define	HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400)

#define	HDMI_TG_CMD HDMI_TG_BASE(0x0000)

#define	HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)

#define	HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)

#define	HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)

#define	HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)

#define	HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)

#define	HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)

#define	HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)

#define	HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)

#define	HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)

#define	HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)

#define	HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)

#define	HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)

#define	HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)

#define	HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)

#define	HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)

#define	HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)

#define	HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)

#define	HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)

#define	HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)

#define	HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)

#define	HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)

#define	HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)

#define	HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)

#define	HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)

#define	HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)

#define	HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)

#define	HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)

#define	HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)

#define	HDMI_INTC_EN_GLOBAL (1 << 6)

#define	HDMI_INTC_EN_HPD_PLUG (1 << 3)

#define	HDMI_INTC_EN_HPD_UNPLUG (1 << 2)

#define	HDMI_INTC_FLAG_HPD_PLUG (1 << 3)

#define	HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)

#define	HDMI_PHY_SW_RSTOUT (1 << 0)

#define	HDMI_CORE_SW_RSTOUT (1 << 0)

#define	HDMI_BLUE_SCR_EN (1 << 5)

#define	HDMI_ASP_EN (1 << 2)

#define	HDMI_ASP_DIS (0 << 2)

#define	HDMI_ASP_MASK (1 << 2)

#define	HDMI_EN (1 << 0)

#define	HDMI_VID_PREAMBLE_DIS (1 << 5)

#define	HDMI_GUARD_BAND_DIS (1 << 1)

#define	HDMI_PHY_STATUS_READY (1 << 0)

#define	HDMI_MODE_HDMI_EN (1 << 1)

#define	HDMI_MODE_DVI_EN (1 << 0)

#define	HDMI_MODE_MASK (3 << 0)

#define	HDMI_TG_EN (1 << 0)

#define	HDMI_FIELD_EN (1 << 1)

#define	HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008)

#define	HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010)

#define	HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014)

#define	HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020)

#define	HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024)

#define	HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028)

#define	HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030)

#define	HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040)

#define	HDMI_HPD_ST HDMI_CTRL_BASE(0x0044)

#define	HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050)

#define	HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070)

#define	HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0074)

#define	HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078)

#define	HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C)

#define	HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080)

#define	HDMI_YMAX HDMI_CORE_BASE(0x0060)

#define	HDMI_YMIN HDMI_CORE_BASE(0x0064)

#define	HDMI_CMAX HDMI_CORE_BASE(0x0068)

#define	HDMI_CMIN HDMI_CORE_BASE(0x006C)

#define	HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0)

#define	HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4)

#define	HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8)

#define	HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC)

#define	HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0)

#define	HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4)

#define	HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8)

#define	HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC)

#define	HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0)

#define	HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110)

#define	HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114)

#define	HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118)

#define	HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C)

#define	HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120)

#define	HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124)

#define	HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128)

#define	HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C)

#define	HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130)

#define	HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134)

#define	HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138)

#define	HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C)

#define	HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140)

#define	HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144)

#define	HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148)

#define	HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C)

#define	HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150)

#define	HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154)

#define	HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158)

#define	HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C)

#define	HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160)

#define	HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164)

#define	HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168)

#define	HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C)

#define	HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170)

#define	HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174)

#define	HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178)

#define	HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C)

#define	HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180)

#define	HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184)

#define	HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188)

#define	HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C)

#define	HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190)

#define	HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194)

#define	HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198)

#define	HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C)

#define	HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0)

#define	HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4)

#define	HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8)

#define	HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC)

#define	HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0)

#define	HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4)

#define	HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8)

#define	HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC)

#define	HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0)

#define	HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4)

#define	HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8)

#define	HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC)

#define	HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0)

#define	HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4)

#define	HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8)

#define	HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC)

#define	HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0)

#define	HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4)

#define	HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8)

#define	HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC)

#define	HDMI_GCP_CON HDMI_CORE_BASE(0x0200)

#define	HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210)

#define	HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214)

#define	HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218)

#define	HDMI_ASP_CON HDMI_CORE_BASE(0x0300)

#define	HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304)

#define	HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310)

#define	HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314)

#define	HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318)

#define	HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C)

#define	HDMI_ACR_CON HDMI_CORE_BASE(0x0400)

#define	HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410)

#define	HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414)

#define	HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418)

#define	HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420)

#define	HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424)

#define	HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428)

#define	HDMI_ACR_N0 HDMI_CORE_BASE(0x0430)

#define	HDMI_ACR_N1 HDMI_CORE_BASE(0x0434)

#define	HDMI_ACR_N2 HDMI_CORE_BASE(0x0438)

#define	HDMI_ACP_CON HDMI_CORE_BASE(0x0500)

#define	HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514)

#define	HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n))

#define	HDMI_ISRC_CON HDMI_CORE_BASE(0x0600)

#define	HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614)

#define	HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n))

#define	HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n))

#define	HDMI_AVI_CON HDMI_CORE_BASE(0x0700)

#define	HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710)

#define	HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714)

#define	HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718)

#define	HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C)

#define	HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n))

#define	HDMI_AUI_CON HDMI_CORE_BASE(0x0800)

#define	HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810)

#define	HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814)

#define	HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818)

#define	HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C)

#define	HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n))

#define	HDMI_MPG_CON HDMI_CORE_BASE(0x0900)

#define	HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C)

#define	HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n))

#define	HDMI_SPD_CON HDMI_CORE_BASE(0x0A00)

#define	HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10)

#define	HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14)

#define	HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18)

#define	HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n))

#define	HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00)

#define	HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10)

#define	HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14)

#define	HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18)

#define	HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n))

#define	HDMI_VSI_CON HDMI_CORE_BASE(0x0C00)

#define	HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10)

#define	HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14)

#define	HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18)

#define	HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n))

#define	HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00)

#define	HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04)

#define	HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48)

#define	HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58)

#define	HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C)

#define	HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60)

#define	HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64)

#define	HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n))

#define	HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n))

#define	HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064)

#define	HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070)

#define	HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080)

#define	HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084)

#define	HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090)

#define	HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n))

#define	HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n))

#define	HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n))

#define	HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100)

#define	HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110)

#define	HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114)

#define	HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140)

#define	HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144)

#define	HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180)

#define	HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190)

#define	HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0)

#define	HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0)

#define	HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0)

#define	HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4)

#define	HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0)

#define	HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500)

#define	HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504)

#define	HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508)

#define	HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C)

#define	HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510)

#define	HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514)

#define	HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518)

#define	HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520)

#define	HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524)

#define	HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528)

#define	HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C)

#define	HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530)

#define	HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534)

#define	HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000)

#define	HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004)

#define	HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008)

#define	HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c)

#define	HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010)

#define	HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014)

#define	HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018)

#define	HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)

#define	HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)

#define	HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)

#define	HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028)

#define	HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c)

#define	HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030)

#define	HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034)

#define	HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038)

#define	HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c)

#define	HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040)

#define	HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044)

#define	HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048)

#define	HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c)

#define	HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054)

#define	HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058)

#define	HDMI_I2S_CLK_DIS (0)

#define	HDMI_I2S_CLK_EN (1)

#define	HDMI_I2S_SCLK_FALLING_EDGE (0 << 1)

#define	HDMI_I2S_SCLK_RISING_EDGE (1 << 1)

#define	HDMI_I2S_L_CH_LOW_POL (0)

#define	HDMI_I2S_L_CH_HIGH_POL (1)

#define	HDMI_I2S_MSB_FIRST_MODE (0 << 6)

#define	HDMI_I2S_LSB_FIRST_MODE (1 << 6)

#define	HDMI_I2S_BIT_CH_32FS (0 << 4)

#define	HDMI_I2S_BIT_CH_48FS (1 << 4)

#define	HDMI_I2S_BIT_CH_RESERVED (2 << 4)

#define	HDMI_I2S_SDATA_16BIT (1 << 2)

#define	HDMI_I2S_SDATA_20BIT (2 << 2)

#define	HDMI_I2S_SDATA_24BIT (3 << 2)

#define	HDMI_I2S_BASIC_FORMAT (0)

#define	HDMI_I2S_L_JUST_FORMAT (2)

#define	HDMI_I2S_R_JUST_FORMAT (3)

#define	HDMI_I2S_CON_2_CLR (~(0xFF))

#define	HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4)

#define	HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2)

#define	HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4)

#define	HDMI_I2S_SEL_LRCK(x) ((x) & 0x7)

#define	HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4)

#define	HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)

#define	HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4)

#define	HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)

#define	HDMI_I2S_SEL_DSD(x) ((x) & 0x7)

#define	HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1)

#define	HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1)

#define	HDMI_I2S_DSD_ENABLE (1)

#define	HDMI_I2S_DSD_DISABLE (0)

#define	HDMI_I2S_NOISE_FILTER_ZERO (0 << 5)

#define	HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5)

#define	HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5)

#define	HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5)

#define	HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5)

#define	HDMI_I2S_IN_DISABLE (1 << 4)

#define	HDMI_I2S_IN_ENABLE (0 << 4)

#define	HDMI_I2S_AUD_SPDIF (0 << 2)

#define	HDMI_I2S_AUD_I2S (1 << 2)

#define	HDMI_I2S_AUD_DSD (2 << 2)

#define	HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1)

#define	HDMI_I2S_CUV_I2S_ENABLE (1 << 1)

#define	HDMI_I2S_MUX_DISABLE (0)

#define	HDMI_I2S_MUX_ENABLE (1)

#define	HDMI_I2S_MUX_CON_CLR (~(0xFF))

#define	HDMI_I2S_CH_STATUS_RELOAD (1)

#define	HDMI_I2S_CH_ST_CON_CLR (~(1))

#define	HDMI_I2S_CH_STATUS_MODE_0 (0 << 6)

#define	HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3)

#define	HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3)

#define	HDMI_I2S_DEFAULT_EMPHASIS (0 << 3)

#define	HDMI_I2S_COPYRIGHT (0 << 2)

#define	HDMI_I2S_NO_COPYRIGHT (1 << 2)

#define	HDMI_I2S_LINEAR_PCM (0 << 1)

#define	HDMI_I2S_NO_LINEAR_PCM (1 << 1)

#define	HDMI_I2S_CONSUMER_FORMAT (0)

#define	HDMI_I2S_PROF_FORMAT (1)

#define	HDMI_I2S_CH_ST_0_CLR (~(0xFF))

#define	HDMI_I2S_CD_PLAYER (0x00)

#define	HDMI_I2S_DAT_PLAYER (0x03)

#define	HDMI_I2S_DCC_PLAYER (0x43)

#define	HDMI_I2S_MINI_DISC_PLAYER (0x49)

#define	HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4)

#define	HDMI_I2S_SOURCE_NUM_MASK (0xF)

#define	HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4)

#define	HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF))

#define	HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4)

#define	HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4)

#define	HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4)

#define	HDMI_I2S_SMP_FREQ_44_1 (0x0)

#define	HDMI_I2S_SMP_FREQ_48 (0x2)

#define	HDMI_I2S_SMP_FREQ_32 (0x3)

#define	HDMI_I2S_SMP_FREQ_96 (0xA)

#define	HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF))

#define	HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4)

#define	HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4)

#define	HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4)

#define	HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4)

#define	HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1)

#define	HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1)

#define	HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1)

#define	HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1)

#define	HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1)

#define	HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1)

#define	HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1)

#define	HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1)

#define	HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1)

#define	HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1)

#define	HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1)

#define	HDMI_I2S_WORD_LEN_MAX_24BITS (1)

#define	HDMI_I2S_WORD_LEN_MAX_20BITS (0)

#define	HDMI_I2S_CH3_R_EN (1 << 7)

#define	HDMI_I2S_CH3_L_EN (1 << 6)

#define	HDMI_I2S_CH3_EN (3 << 6)

#define	HDMI_I2S_CH2_R_EN (1 << 5)

#define	HDMI_I2S_CH2_L_EN (1 << 4)

#define	HDMI_I2S_CH2_EN (3 << 4)

#define	HDMI_I2S_CH1_R_EN (1 << 3)

#define	HDMI_I2S_CH1_L_EN (1 << 2)

#define	HDMI_I2S_CH1_EN (3 << 2)

#define	HDMI_I2S_CH0_R_EN (1 << 1)

#define	HDMI_I2S_CH0_L_EN (1)

#define	HDMI_I2S_CH0_EN (3)

#define	HDMI_I2S_CH_ALL_EN (0xFF)

#define	HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN)

#define	HDMI_I2S_CUV_R_EN (1 << 1)

#define	HDMI_I2S_CUV_L_EN (1)

#define	HDMI_I2S_CUV_RL_EN (0x03)

#define	HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4)

#define	HDMI_I2S_CUV_L_DATA_MASK (0x7)

#define	HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068)

#define	HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c)

#define	HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070)

#define	HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074)

#define	HDMI_TG_3D HDMI_TG_BASE(0x00F0)

Macro Definition Documentation

#define HDMI_ACP_CON HDMI_CORE_BASE(0x0500)

Definition at line 287 of file regs-hdmi.h.

#define HDMI_ACP_DATA ( n ) HDMI_CORE_BASE(0x0520 + 4 * (n))

Definition at line 289 of file regs-hdmi.h.

#define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514)

Definition at line 288 of file regs-hdmi.h.

#define HDMI_ACR_CON HDMI_CORE_BASE(0x0400)

Definition at line 275 of file regs-hdmi.h.

#define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420)

Definition at line 279 of file regs-hdmi.h.

#define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424)

Definition at line 280 of file regs-hdmi.h.

#define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428)

Definition at line 281 of file regs-hdmi.h.

#define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410)

Definition at line 276 of file regs-hdmi.h.

#define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414)

Definition at line 277 of file regs-hdmi.h.

#define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418)

Definition at line 278 of file regs-hdmi.h.

#define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430)

Definition at line 282 of file regs-hdmi.h.

#define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434)

Definition at line 283 of file regs-hdmi.h.

#define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438)

Definition at line 284 of file regs-hdmi.h.

#define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58)

Definition at line 336 of file regs-hdmi.h.

#define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C)

Definition at line 337 of file regs-hdmi.h.

#define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60)

Definition at line 338 of file regs-hdmi.h.

#define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64)

Definition at line 339 of file regs-hdmi.h.

#define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48)

Definition at line 335 of file regs-hdmi.h.

#define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310)

Definition at line 270 of file regs-hdmi.h.

#define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314)

Definition at line 271 of file regs-hdmi.h.

#define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318)

Definition at line 272 of file regs-hdmi.h.

#define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C)

Definition at line 273 of file regs-hdmi.h.

#define HDMI_ASP_CON HDMI_CORE_BASE(0x0300)

Definition at line 268 of file regs-hdmi.h.

#define HDMI_ASP_DIS (0 << 2)

Definition at line 137 of file regs-hdmi.h.

#define HDMI_ASP_EN (1 << 2)

Definition at line 136 of file regs-hdmi.h.

#define HDMI_ASP_MASK (1 << 2)

Definition at line 138 of file regs-hdmi.h.

#define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304)

Definition at line 269 of file regs-hdmi.h.

#define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070)

Definition at line 173 of file regs-hdmi.h.

#define HDMI_AUI_BYTE ( n ) HDMI_CORE_BASE(0x0820 + 4 * (n))

Definition at line 308 of file regs-hdmi.h.

#define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C)

Definition at line 307 of file regs-hdmi.h.

#define HDMI_AUI_CON HDMI_CORE_BASE(0x0800)

Definition at line 303 of file regs-hdmi.h.

#define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810)

Definition at line 304 of file regs-hdmi.h.

#define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814)

Definition at line 305 of file regs-hdmi.h.

#define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818)

Definition at line 306 of file regs-hdmi.h.

#define HDMI_AVI_BYTE ( n ) HDMI_CORE_BASE(0x0720 + 4 * (n))

Definition at line 301 of file regs-hdmi.h.

#define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C)

Definition at line 300 of file regs-hdmi.h.

#define HDMI_AVI_CON HDMI_CORE_BASE(0x0700)

Definition at line 296 of file regs-hdmi.h.

#define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710)

Definition at line 297 of file regs-hdmi.h.

#define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714)

Definition at line 298 of file regs-hdmi.h.

#define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718)

Definition at line 299 of file regs-hdmi.h.

#define HDMI_BLUE_SCR_EN (1 << 5)

Definition at line 135 of file regs-hdmi.h.

#define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520)

Definition at line 375 of file regs-hdmi.h.

#define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524)

Definition at line 376 of file regs-hdmi.h.

#define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528)

Definition at line 377 of file regs-hdmi.h.

#define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C)

Definition at line 378 of file regs-hdmi.h.

#define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530)

Definition at line 379 of file regs-hdmi.h.

#define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534)

Definition at line 380 of file regs-hdmi.h.

#define HDMI_CMAX HDMI_CORE_BASE(0x0068)

Definition at line 182 of file regs-hdmi.h.

#define HDMI_CMIN HDMI_CORE_BASE(0x006C)

Definition at line 183 of file regs-hdmi.h.

#define HDMI_CON_0 HDMI_CORE_BASE(0x0000)

Definition at line 38 of file regs-hdmi.h.

#define HDMI_CON_1 HDMI_CORE_BASE(0x0004)

Definition at line 39 of file regs-hdmi.h.

#define HDMI_CON_2 HDMI_CORE_BASE(0x0008)

Definition at line 40 of file regs-hdmi.h.

#define HDMI_CORE_BASE ( x ) ((x) + 0x00010000)

Definition at line 24 of file regs-hdmi.h.

#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080)

Definition at line 177 of file regs-hdmi.h.

#define HDMI_CORE_SW_RSTOUT (1 << 0)

Definition at line 132 of file regs-hdmi.h.

#define HDMI_CTRL_BASE ( x ) ((x) + 0x00000000)

Definition at line 23 of file regs-hdmi.h.

#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00)

Definition at line 332 of file regs-hdmi.h.

#define HDMI_EN (1 << 0)

Definition at line 139 of file regs-hdmi.h.

#define HDMI_ENC_EN HDMI_CORE_BASE(0x0044)

Definition at line 46 of file regs-hdmi.h.

#define HDMI_FIELD_EN (1 << 1)

Definition at line 155 of file regs-hdmi.h.

#define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00)

Definition at line 320 of file regs-hdmi.h.

#define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10)

Definition at line 321 of file regs-hdmi.h.

#define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14)

Definition at line 322 of file regs-hdmi.h.

#define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18)

Definition at line 323 of file regs-hdmi.h.

#define HDMI_GAMUT_METADATA ( n ) HDMI_CORE_BASE(0x0B20 + 4 * (n))

Definition at line 324 of file regs-hdmi.h.

#define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210)

Definition at line 263 of file regs-hdmi.h.

#define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214)

Definition at line 264 of file regs-hdmi.h.

#define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218)

Definition at line 265 of file regs-hdmi.h.

#define HDMI_GCP_CON HDMI_CORE_BASE(0x0200)

Definition at line 262 of file regs-hdmi.h.

#define HDMI_GUARD_BAND_DIS (1 << 1)

Definition at line 143 of file regs-hdmi.h.

#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)

Definition at line 50 of file regs-hdmi.h.

#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)

Definition at line 51 of file regs-hdmi.h.

#define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8)

Definition at line 192 of file regs-hdmi.h.

#define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC)

Definition at line 193 of file regs-hdmi.h.

#define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128)

Definition at line 204 of file regs-hdmi.h.

#define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C)

Definition at line 205 of file regs-hdmi.h.

#define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120)

Definition at line 202 of file regs-hdmi.h.

#define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124)

Definition at line 203 of file regs-hdmi.h.

#define HDMI_HDCP_AKSV ( n ) HDMI_CORE_BASE(0x70C0 + 4 * (n))

Definition at line 351 of file regs-hdmi.h.

#define HDMI_HDCP_AN ( n ) HDMI_CORE_BASE(0x70E0 + 4 * (n))

Definition at line 352 of file regs-hdmi.h.

#define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190)

Definition at line 360 of file regs-hdmi.h.

#define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100)

Definition at line 354 of file regs-hdmi.h.

#define HDMI_HDCP_BKSV ( n ) HDMI_CORE_BASE(0x70A0 + 4 * (n))

Definition at line 350 of file regs-hdmi.h.

#define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110)

Definition at line 355 of file regs-hdmi.h.

#define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114)

Definition at line 356 of file regs-hdmi.h.

#define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090)

Definition at line 349 of file regs-hdmi.h.

#define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080)

Definition at line 347 of file regs-hdmi.h.

#define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084)

Definition at line 348 of file regs-hdmi.h.

#define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0)

Definition at line 365 of file regs-hdmi.h.

#define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180)

Definition at line 359 of file regs-hdmi.h.

#define HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008)

Definition at line 162 of file regs-hdmi.h.

#define HDMI_HDCP_KSV_LIST ( n ) HDMI_CORE_BASE(0x7050 + 4 * (n))

Definition at line 343 of file regs-hdmi.h.

#define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064)

Definition at line 345 of file regs-hdmi.h.

#define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140)

Definition at line 357 of file regs-hdmi.h.

#define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144)

Definition at line 358 of file regs-hdmi.h.

#define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0)

Definition at line 363 of file regs-hdmi.h.

#define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4)

Definition at line 364 of file regs-hdmi.h.

#define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0)

Definition at line 362 of file regs-hdmi.h.

#define HDMI_HDCP_SHA1 ( n ) HDMI_CORE_BASE(0x7000 + 4 * (n))

Definition at line 342 of file regs-hdmi.h.

#define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070)

Definition at line 346 of file regs-hdmi.h.

#define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0)

Definition at line 361 of file regs-hdmi.h.

#define HDMI_HPD HDMI_CORE_BASE(0x0030)

Definition at line 44 of file regs-hdmi.h.

#define HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040)

Definition at line 170 of file regs-hdmi.h.

#define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044)

Definition at line 171 of file regs-hdmi.h.

#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)

Definition at line 31 of file regs-hdmi.h.

#define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050)

Definition at line 172 of file regs-hdmi.h.

#define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0)

Definition at line 195 of file regs-hdmi.h.

#define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3)

Definition at line 479 of file regs-hdmi.h.

#define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3)

Definition at line 478 of file regs-hdmi.h.

#define HDMI_I2S_AUD_DSD (2 << 2)

Definition at line 465 of file regs-hdmi.h.

#define HDMI_I2S_AUD_I2S (1 << 2)

Definition at line 464 of file regs-hdmi.h.

#define HDMI_I2S_AUD_SPDIF (0 << 2)

Definition at line 463 of file regs-hdmi.h.

#define HDMI_I2S_BASE ( x ) ((x) + 0x00040000)

Definition at line 25 of file regs-hdmi.h.

#define HDMI_I2S_BASIC_FORMAT (0)

Definition at line 427 of file regs-hdmi.h.

#define HDMI_I2S_BIT_CH_32FS (0 << 4)

Definition at line 421 of file regs-hdmi.h.

#define HDMI_I2S_BIT_CH_48FS (1 << 4)

Definition at line 422 of file regs-hdmi.h.

#define HDMI_I2S_BIT_CH_RESERVED (2 << 4)

Definition at line 423 of file regs-hdmi.h.

#define HDMI_I2S_CD_PLAYER (0x00)

Definition at line 490 of file regs-hdmi.h.

#define HDMI_I2S_CH0_EN (3)

Definition at line 542 of file regs-hdmi.h.

#define HDMI_I2S_CH0_L_EN (1)

Definition at line 541 of file regs-hdmi.h.

#define HDMI_I2S_CH0_R_EN (1 << 1)

Definition at line 540 of file regs-hdmi.h.

#define HDMI_I2S_CH1_EN (3 << 2)

Definition at line 539 of file regs-hdmi.h.

#define HDMI_I2S_CH1_L_EN (1 << 2)

Definition at line 538 of file regs-hdmi.h.

#define HDMI_I2S_CH1_R_EN (1 << 3)

Definition at line 537 of file regs-hdmi.h.

#define HDMI_I2S_CH2_EN (3 << 4)

Definition at line 536 of file regs-hdmi.h.

#define HDMI_I2S_CH2_L_EN (1 << 4)

Definition at line 535 of file regs-hdmi.h.

#define HDMI_I2S_CH2_R_EN (1 << 5)

Definition at line 534 of file regs-hdmi.h.

#define HDMI_I2S_CH3_EN (3 << 6)

Definition at line 533 of file regs-hdmi.h.

#define HDMI_I2S_CH3_L_EN (1 << 6)

Definition at line 532 of file regs-hdmi.h.

#define HDMI_I2S_CH3_R_EN (1 << 7)

Definition at line 531 of file regs-hdmi.h.

#define HDMI_I2S_CH_ALL_EN (0xFF)

Definition at line 543 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028)

Definition at line 393 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_0_CLR (~(0xFF))

Definition at line 487 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c)

Definition at line 394 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030)

Definition at line 395 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034)

Definition at line 396 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038)

Definition at line 397 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)

Definition at line 392 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_CON_CLR (~(1))

Definition at line 474 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c)

Definition at line 398 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040)

Definition at line 399 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044)

Definition at line 400 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048)

Definition at line 401 of file regs-hdmi.h.

#define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c)

Definition at line 402 of file regs-hdmi.h.

#define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6)

Definition at line 477 of file regs-hdmi.h.

#define HDMI_I2S_CH_STATUS_RELOAD (1)

Definition at line 473 of file regs-hdmi.h.

#define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4)

Definition at line 496 of file regs-hdmi.h.

#define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4)

Definition at line 502 of file regs-hdmi.h.

#define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4)

Definition at line 503 of file regs-hdmi.h.

#define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4)

Definition at line 504 of file regs-hdmi.h.

#define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000)

Definition at line 383 of file regs-hdmi.h.

#define HDMI_I2S_CLK_DIS (0)

Definition at line 409 of file regs-hdmi.h.

#define HDMI_I2S_CLK_EN (1)

Definition at line 410 of file regs-hdmi.h.

#define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004)

Definition at line 384 of file regs-hdmi.h.

#define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008)

Definition at line 385 of file regs-hdmi.h.

#define HDMI_I2S_CON_2_CLR (~(0xFF))

Definition at line 430 of file regs-hdmi.h.

#define HDMI_I2S_CONSUMER_FORMAT (0)

Definition at line 485 of file regs-hdmi.h.

#define HDMI_I2S_COPYRIGHT (0 << 2)

Definition at line 481 of file regs-hdmi.h.

#define HDMI_I2S_CUV_I2S_ENABLE (1 << 1)

Definition at line 467 of file regs-hdmi.h.

#define HDMI_I2S_CUV_L_DATA_MASK (0x7)

Definition at line 553 of file regs-hdmi.h.

#define HDMI_I2S_CUV_L_EN (1)

Definition at line 548 of file regs-hdmi.h.

#define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4)

Definition at line 552 of file regs-hdmi.h.

#define HDMI_I2S_CUV_R_EN (1 << 1)

Definition at line 547 of file regs-hdmi.h.

#define HDMI_I2S_CUV_RL_EN (0x03)

Definition at line 549 of file regs-hdmi.h.

#define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1)

Definition at line 466 of file regs-hdmi.h.

#define HDMI_I2S_DAT_PLAYER (0x03)

Definition at line 491 of file regs-hdmi.h.

#define HDMI_I2S_DCC_PLAYER (0x43)

Definition at line 492 of file regs-hdmi.h.

#define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3)

Definition at line 480 of file regs-hdmi.h.

#define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1)

Definition at line 451 of file regs-hdmi.h.

#define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1)

Definition at line 450 of file regs-hdmi.h.

#define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)

Definition at line 390 of file regs-hdmi.h.

#define HDMI_I2S_DSD_DISABLE (0)

Definition at line 453 of file regs-hdmi.h.

#define HDMI_I2S_DSD_ENABLE (1)

Definition at line 452 of file regs-hdmi.h.

#define HDMI_I2S_IN_DISABLE (1 << 4)

Definition at line 461 of file regs-hdmi.h.

#define HDMI_I2S_IN_ENABLE (0 << 4)

Definition at line 462 of file regs-hdmi.h.

#define HDMI_I2S_L_CH_HIGH_POL (1)

Definition at line 416 of file regs-hdmi.h.

#define HDMI_I2S_L_CH_LOW_POL (0)

Definition at line 415 of file regs-hdmi.h.

#define HDMI_I2S_L_JUST_FORMAT (2)

Definition at line 428 of file regs-hdmi.h.

#define HDMI_I2S_LINEAR_PCM (0 << 1)

Definition at line 483 of file regs-hdmi.h.

#define HDMI_I2S_LSB_FIRST_MODE (1 << 6)

Definition at line 420 of file regs-hdmi.h.

#define HDMI_I2S_MINI_DISC_PLAYER (0x49)

Definition at line 493 of file regs-hdmi.h.

#define HDMI_I2S_MSB_FIRST_MODE (0 << 6)

Definition at line 419 of file regs-hdmi.h.

#define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054)

Definition at line 403 of file regs-hdmi.h.

#define HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN)

Definition at line 544 of file regs-hdmi.h.

#define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)

Definition at line 391 of file regs-hdmi.h.

#define HDMI_I2S_MUX_CON_CLR (~(0xFF))

Definition at line 470 of file regs-hdmi.h.

#define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058)

Definition at line 404 of file regs-hdmi.h.

#define HDMI_I2S_MUX_DISABLE (0)

Definition at line 468 of file regs-hdmi.h.

#define HDMI_I2S_MUX_ENABLE (1)

Definition at line 469 of file regs-hdmi.h.

#define HDMI_I2S_NO_COPYRIGHT (1 << 2)

Definition at line 482 of file regs-hdmi.h.

#define HDMI_I2S_NO_LINEAR_PCM (1 << 1)

Definition at line 484 of file regs-hdmi.h.

#define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5)

Definition at line 457 of file regs-hdmi.h.

#define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5)

Definition at line 458 of file regs-hdmi.h.

#define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5)

Definition at line 459 of file regs-hdmi.h.

#define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5)

Definition at line 460 of file regs-hdmi.h.

#define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5)

Definition at line 456 of file regs-hdmi.h.

#define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4)

Definition at line 515 of file regs-hdmi.h.

#define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4)

Definition at line 514 of file regs-hdmi.h.

#define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4)

Definition at line 512 of file regs-hdmi.h.

#define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4)

Definition at line 513 of file regs-hdmi.h.

#define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c)

Definition at line 386 of file regs-hdmi.h.

#define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010)

Definition at line 387 of file regs-hdmi.h.

#define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014)

Definition at line 388 of file regs-hdmi.h.

#define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018)

Definition at line 389 of file regs-hdmi.h.

#define HDMI_I2S_PROF_FORMAT (1)

Definition at line 486 of file regs-hdmi.h.

#define HDMI_I2S_R_JUST_FORMAT (3)

Definition at line 429 of file regs-hdmi.h.

#define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1)

Definition at line 413 of file regs-hdmi.h.

#define HDMI_I2S_SCLK_RISING_EDGE (1 << 1)

Definition at line 414 of file regs-hdmi.h.

#define HDMI_I2S_SDATA_16BIT (1 << 2)

Definition at line 424 of file regs-hdmi.h.

#define HDMI_I2S_SDATA_20BIT (2 << 2)

Definition at line 425 of file regs-hdmi.h.

#define HDMI_I2S_SDATA_24BIT (3 << 2)

Definition at line 426 of file regs-hdmi.h.

#define HDMI_I2S_SEL_DSD ( x ) ((x) & 0x7)

Definition at line 447 of file regs-hdmi.h.

#define HDMI_I2S_SEL_LRCK ( x ) ((x) & 0x7)

Definition at line 436 of file regs-hdmi.h.

#define HDMI_I2S_SEL_SCLK ( x ) (((x) & 0x7) << 4)

Definition at line 435 of file regs-hdmi.h.

#define HDMI_I2S_SEL_SDATA1 ( x ) (((x) & 0x7) << 4)

Definition at line 439 of file regs-hdmi.h.

#define HDMI_I2S_SEL_SDATA2 ( x ) ((x) & 0x7)

Definition at line 444 of file regs-hdmi.h.

#define HDMI_I2S_SEL_SDATA2 ( x ) ((x) & 0x7)

Definition at line 444 of file regs-hdmi.h.

#define HDMI_I2S_SEL_SDATA3 ( x ) (((x) & 0x7) << 4)

Definition at line 443 of file regs-hdmi.h.

#define HDMI_I2S_SET_BIT_CH ( x ) (((x) & 0x7) << 4)

Definition at line 431 of file regs-hdmi.h.

#define HDMI_I2S_SET_CHANNEL_NUM ( x ) (((x) & (0xF)) << 4)

Definition at line 498 of file regs-hdmi.h.

#define HDMI_I2S_SET_SDATA_BIT ( x ) (((x) & 0x7) << 2)

Definition at line 432 of file regs-hdmi.h.

#define HDMI_I2S_SET_SMP_FREQ ( x ) ((x) & (0xF))

Definition at line 509 of file regs-hdmi.h.

#define HDMI_I2S_SET_SOURCE_NUM ( x ) ((x) & (0xF))

Definition at line 499 of file regs-hdmi.h.

#define HDMI_I2S_SMP_FREQ_32 (0x3)

Definition at line 507 of file regs-hdmi.h.

#define HDMI_I2S_SMP_FREQ_44_1 (0x0)

Definition at line 505 of file regs-hdmi.h.

#define HDMI_I2S_SMP_FREQ_48 (0x2)

Definition at line 506 of file regs-hdmi.h.

#define HDMI_I2S_SMP_FREQ_96 (0xA)

Definition at line 508 of file regs-hdmi.h.

#define HDMI_I2S_SOURCE_NUM_MASK (0xF)

Definition at line 497 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1)

Definition at line 522 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1)

Definition at line 526 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1)

Definition at line 523 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1)

Definition at line 524 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1)

Definition at line 525 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1)

Definition at line 517 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1)

Definition at line 521 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1)

Definition at line 518 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1)

Definition at line 519 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1)

Definition at line 520 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX_20BITS (0)

Definition at line 528 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_MAX_24BITS (1)

Definition at line 527 of file regs-hdmi.h.

#define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1)

Definition at line 516 of file regs-hdmi.h.

#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)

Definition at line 59 of file regs-hdmi.h.

#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)

Definition at line 29 of file regs-hdmi.h.

#define HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010)

Definition at line 164 of file regs-hdmi.h.

#define HDMI_INTC_EN_GLOBAL (1 << 6)

Definition at line 120 of file regs-hdmi.h.

#define HDMI_INTC_EN_HPD_PLUG (1 << 3)

Definition at line 121 of file regs-hdmi.h.

#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)

Definition at line 122 of file regs-hdmi.h.

#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)

Definition at line 30 of file regs-hdmi.h.

#define HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014)

Definition at line 165 of file regs-hdmi.h.

#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)

Definition at line 125 of file regs-hdmi.h.

#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)

Definition at line 126 of file regs-hdmi.h.

#define HDMI_ISRC1_DATA ( n ) HDMI_CORE_BASE(0x0620 + 4 * (n))

Definition at line 293 of file regs-hdmi.h.

#define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614)

Definition at line 292 of file regs-hdmi.h.

#define HDMI_ISRC2_DATA ( n ) HDMI_CORE_BASE(0x06A0 + 4 * (n))

Definition at line 294 of file regs-hdmi.h.

#define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600)

Definition at line 291 of file regs-hdmi.h.

#define HDMI_MODE_DVI_EN (1 << 0)

Definition at line 150 of file regs-hdmi.h.

#define HDMI_MODE_HDMI_EN (1 << 1)

Definition at line 149 of file regs-hdmi.h.

#define HDMI_MODE_MASK (3 << 0)

Definition at line 151 of file regs-hdmi.h.

#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)

Definition at line 45 of file regs-hdmi.h.

#define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C)

Definition at line 311 of file regs-hdmi.h.

#define HDMI_MPG_CON HDMI_CORE_BASE(0x0900)

Definition at line 310 of file regs-hdmi.h.

#define HDMI_MPG_DATA ( n ) HDMI_CORE_BASE(0x0920 + 4 * (n))

Definition at line 312 of file regs-hdmi.h.

#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C)

Definition at line 176 of file regs-hdmi.h.

#define HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030)

Definition at line 169 of file regs-hdmi.h.

#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0074)

Definition at line 174 of file regs-hdmi.h.

#define HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020)

Definition at line 166 of file regs-hdmi.h.

#define HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024)

Definition at line 167 of file regs-hdmi.h.

#define HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028)

Definition at line 168 of file regs-hdmi.h.

#define HDMI_PHY_STATUS_READY (1 << 0)

Definition at line 146 of file regs-hdmi.h.

#define HDMI_PHY_SW_RSTOUT (1 << 0)

Definition at line 129 of file regs-hdmi.h.

#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078)

Definition at line 175 of file regs-hdmi.h.

#define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500)

Definition at line 367 of file regs-hdmi.h.

#define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00)

Definition at line 314 of file regs-hdmi.h.

#define HDMI_SPD_DATA ( n ) HDMI_CORE_BASE(0x0A20 + 4 * (n))

Definition at line 318 of file regs-hdmi.h.

#define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10)

Definition at line 315 of file regs-hdmi.h.

#define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14)

Definition at line 316 of file regs-hdmi.h.

#define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18)

Definition at line 317 of file regs-hdmi.h.

#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)

Definition at line 43 of file regs-hdmi.h.

#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)

Definition at line 41 of file regs-hdmi.h.

#define HDMI_TG_3D HDMI_TG_BASE(0x00F0)

Definition at line 561 of file regs-hdmi.h.

#define HDMI_TG_BASE ( x ) ((x) + 0x00050000)

Definition at line 26 of file regs-hdmi.h.

#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)

Definition at line 85 of file regs-hdmi.h.

#define HDMI_TG_EN (1 << 0)

Definition at line 154 of file regs-hdmi.h.

#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)

Definition at line 113 of file regs-hdmi.h.

#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)

Definition at line 112 of file regs-hdmi.h.

#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)

Definition at line 103 of file regs-hdmi.h.

#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)

Definition at line 102 of file regs-hdmi.h.

#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)

Definition at line 111 of file regs-hdmi.h.

#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)

Definition at line 110 of file regs-hdmi.h.

#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)

Definition at line 87 of file regs-hdmi.h.

#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)

Definition at line 86 of file regs-hdmi.h.

#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)

Definition at line 89 of file regs-hdmi.h.

#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)

Definition at line 88 of file regs-hdmi.h.

#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)

Definition at line 91 of file regs-hdmi.h.

#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)

Definition at line 90 of file regs-hdmi.h.

#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)

Definition at line 93 of file regs-hdmi.h.

#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)

Definition at line 92 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)

Definition at line 105 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)

Definition at line 104 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c)

Definition at line 558 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068)

Definition at line 557 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074)

Definition at line 560 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070)

Definition at line 559 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)

Definition at line 99 of file regs-hdmi.h.

#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)

Definition at line 98 of file regs-hdmi.h.

#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)

Definition at line 101 of file regs-hdmi.h.

#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)

Definition at line 100 of file regs-hdmi.h.

#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)

Definition at line 97 of file regs-hdmi.h.

#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)

Definition at line 96 of file regs-hdmi.h.

#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)

Definition at line 109 of file regs-hdmi.h.

#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)

Definition at line 108 of file regs-hdmi.h.

#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)

Definition at line 95 of file regs-hdmi.h.

#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)

Definition at line 94 of file regs-hdmi.h.

#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)

Definition at line 107 of file regs-hdmi.h.

#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)

Definition at line 106 of file regs-hdmi.h.

#define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180)

Definition at line 75 of file regs-hdmi.h.

#define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360)

Definition at line 81 of file regs-hdmi.h.

#define HDMI_V13_AVI_BYTE ( n ) HDMI_CORE_BASE(0x0320 + 4 * (n))

Definition at line 77 of file regs-hdmi.h.

#define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300)

Definition at line 76 of file regs-hdmi.h.

#define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)

Definition at line 47 of file regs-hdmi.h.

#define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)

Definition at line 48 of file regs-hdmi.h.

#define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)

Definition at line 49 of file regs-hdmi.h.

#define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)

Definition at line 35 of file regs-hdmi.h.

#define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0)

Definition at line 78 of file regs-hdmi.h.

#define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)

Definition at line 63 of file regs-hdmi.h.

#define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)

Definition at line 64 of file regs-hdmi.h.

#define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)

Definition at line 65 of file regs-hdmi.h.

#define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)

Definition at line 55 of file regs-hdmi.h.

#define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)

Definition at line 56 of file regs-hdmi.h.

#define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)

Definition at line 57 of file regs-hdmi.h.

#define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8)

Definition at line 80 of file regs-hdmi.h.

#define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C)

Definition at line 34 of file regs-hdmi.h.

#define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)

Definition at line 32 of file regs-hdmi.h.

#define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014)

Definition at line 42 of file regs-hdmi.h.

#define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018)

Definition at line 33 of file regs-hdmi.h.

#define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400)

Definition at line 82 of file regs-hdmi.h.

#define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0)

Definition at line 52 of file regs-hdmi.h.

#define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4)

Definition at line 53 of file regs-hdmi.h.

#define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8)

Definition at line 54 of file regs-hdmi.h.

#define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)

Definition at line 60 of file regs-hdmi.h.

#define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)

Definition at line 61 of file regs-hdmi.h.

#define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)

Definition at line 62 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)

Definition at line 66 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)

Definition at line 67 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)

Definition at line 68 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)

Definition at line 69 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)

Definition at line 70 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)

Definition at line 71 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)

Definition at line 72 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)

Definition at line 73 of file regs-hdmi.h.

#define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)

Definition at line 74 of file regs-hdmi.h.

#define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)

Definition at line 79 of file regs-hdmi.h.

#define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8)

Definition at line 187 of file regs-hdmi.h.

#define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC)

Definition at line 188 of file regs-hdmi.h.

#define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0)

Definition at line 185 of file regs-hdmi.h.

#define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4)

Definition at line 186 of file regs-hdmi.h.

#define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110)

Definition at line 197 of file regs-hdmi.h.

#define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114)

Definition at line 198 of file regs-hdmi.h.

#define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118)

Definition at line 199 of file regs-hdmi.h.

#define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C)

Definition at line 200 of file regs-hdmi.h.

#define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160)

Definition at line 222 of file regs-hdmi.h.

#define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164)

Definition at line 223 of file regs-hdmi.h.

#define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168)

Definition at line 224 of file regs-hdmi.h.

#define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C)

Definition at line 225 of file regs-hdmi.h.

#define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170)

Definition at line 226 of file regs-hdmi.h.

#define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174)

Definition at line 227 of file regs-hdmi.h.

#define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178)

Definition at line 228 of file regs-hdmi.h.

#define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C)

Definition at line 229 of file regs-hdmi.h.

#define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0)

Definition at line 190 of file regs-hdmi.h.

#define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4)

Definition at line 191 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148)

Definition at line 214 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C)

Definition at line 215 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140)

Definition at line 212 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144)

Definition at line 213 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180)

Definition at line 231 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184)

Definition at line 232 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188)

Definition at line 233 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C)

Definition at line 234 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190)

Definition at line 235 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194)

Definition at line 236 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198)

Definition at line 237 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C)

Definition at line 238 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158)

Definition at line 219 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C)

Definition at line 220 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150)

Definition at line 217 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154)

Definition at line 218 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0)

Definition at line 240 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4)

Definition at line 241 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8)

Definition at line 242 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC)

Definition at line 243 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0)

Definition at line 244 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4)

Definition at line 245 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8)

Definition at line 246 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC)

Definition at line 247 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138)

Definition at line 209 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C)

Definition at line 210 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130)

Definition at line 207 of file regs-hdmi.h.

#define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134)

Definition at line 208 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0)

Definition at line 249 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4)

Definition at line 250 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8)

Definition at line 251 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC)

Definition at line 252 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0)

Definition at line 253 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4)

Definition at line 254 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8)

Definition at line 255 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC)

Definition at line 256 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0)

Definition at line 257 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4)

Definition at line 258 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8)

Definition at line 259 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC)

Definition at line 260 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514)

Definition at line 372 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518)

Definition at line 373 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C)

Definition at line 370 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510)

Definition at line 371 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504)

Definition at line 368 of file regs-hdmi.h.

#define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508)

Definition at line 369 of file regs-hdmi.h.

#define HDMI_VID_PREAMBLE_DIS (1 << 5)

Definition at line 142 of file regs-hdmi.h.

#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04)

Definition at line 333 of file regs-hdmi.h.

#define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00)

Definition at line 326 of file regs-hdmi.h.

#define HDMI_VSI_DATA ( n ) HDMI_CORE_BASE(0x0C20 + 4 * (n))

Definition at line 330 of file regs-hdmi.h.

#define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10)

Definition at line 327 of file regs-hdmi.h.

#define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14)

Definition at line 328 of file regs-hdmi.h.

#define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18)

Definition at line 329 of file regs-hdmi.h.

#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)

Definition at line 58 of file regs-hdmi.h.

#define HDMI_YMAX HDMI_CORE_BASE(0x0060)

Definition at line 180 of file regs-hdmi.h.

#define HDMI_YMIN HDMI_CORE_BASE(0x0064)

Definition at line 181 of file regs-hdmi.h.

Macros

Macro Definition Documentation