Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
gt64120.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc.
3  * All rights reserved.
4  * Authors: Carsten Langgaard <[email protected]>
5  * Maciej W. Rozycki <[email protected]>
6  * Copyright (C) 2005 Ralf Baechle ([email protected])
7  *
8  * This program is free software; you can distribute it and/or modify it
9  * under the terms of the GNU General Public License (Version 2) as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15  * for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20  */
21 #ifndef _ASM_GT64120_H
22 #define _ASM_GT64120_H
23 
24 #include <asm/addrspace.h>
25 #include <asm/byteorder.h>
26 
27 #define MSK(n) ((1 << (n)) - 1)
28 
29 /*
30  * Register offset addresses
31  */
32 /* CPU Configuration. */
33 #define GT_CPU_OFS 0x000
34 
35 #define GT_MULTI_OFS 0x120
36 
37 /* CPU Address Decode. */
38 #define GT_SCS10LD_OFS 0x008
39 #define GT_SCS10HD_OFS 0x010
40 #define GT_SCS32LD_OFS 0x018
41 #define GT_SCS32HD_OFS 0x020
42 #define GT_CS20LD_OFS 0x028
43 #define GT_CS20HD_OFS 0x030
44 #define GT_CS3BOOTLD_OFS 0x038
45 #define GT_CS3BOOTHD_OFS 0x040
46 #define GT_PCI0IOLD_OFS 0x048
47 #define GT_PCI0IOHD_OFS 0x050
48 #define GT_PCI0M0LD_OFS 0x058
49 #define GT_PCI0M0HD_OFS 0x060
50 #define GT_ISD_OFS 0x068
51 
52 #define GT_PCI0M1LD_OFS 0x080
53 #define GT_PCI0M1HD_OFS 0x088
54 #define GT_PCI1IOLD_OFS 0x090
55 #define GT_PCI1IOHD_OFS 0x098
56 #define GT_PCI1M0LD_OFS 0x0a0
57 #define GT_PCI1M0HD_OFS 0x0a8
58 #define GT_PCI1M1LD_OFS 0x0b0
59 #define GT_PCI1M1HD_OFS 0x0b8
60 #define GT_PCI1M1LD_OFS 0x0b0
61 #define GT_PCI1M1HD_OFS 0x0b8
62 
63 #define GT_SCS10AR_OFS 0x0d0
64 #define GT_SCS32AR_OFS 0x0d8
65 #define GT_CS20R_OFS 0x0e0
66 #define GT_CS3BOOTR_OFS 0x0e8
67 
68 #define GT_PCI0IOREMAP_OFS 0x0f0
69 #define GT_PCI0M0REMAP_OFS 0x0f8
70 #define GT_PCI0M1REMAP_OFS 0x100
71 #define GT_PCI1IOREMAP_OFS 0x108
72 #define GT_PCI1M0REMAP_OFS 0x110
73 #define GT_PCI1M1REMAP_OFS 0x118
74 
75 /* CPU Error Report. */
76 #define GT_CPUERR_ADDRLO_OFS 0x070
77 #define GT_CPUERR_ADDRHI_OFS 0x078
78 
79 #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */
80 #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */
81 #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */
82 
83 /* CPU Sync Barrier. */
84 #define GT_PCI0SYNC_OFS 0x0c0
85 #define GT_PCI1SYNC_OFS 0x0c8
86 
87 /* SDRAM and Device Address Decode. */
88 #define GT_SCS0LD_OFS 0x400
89 #define GT_SCS0HD_OFS 0x404
90 #define GT_SCS1LD_OFS 0x408
91 #define GT_SCS1HD_OFS 0x40c
92 #define GT_SCS2LD_OFS 0x410
93 #define GT_SCS2HD_OFS 0x414
94 #define GT_SCS3LD_OFS 0x418
95 #define GT_SCS3HD_OFS 0x41c
96 #define GT_CS0LD_OFS 0x420
97 #define GT_CS0HD_OFS 0x424
98 #define GT_CS1LD_OFS 0x428
99 #define GT_CS1HD_OFS 0x42c
100 #define GT_CS2LD_OFS 0x430
101 #define GT_CS2HD_OFS 0x434
102 #define GT_CS3LD_OFS 0x438
103 #define GT_CS3HD_OFS 0x43c
104 #define GT_BOOTLD_OFS 0x440
105 #define GT_BOOTHD_OFS 0x444
106 
107 #define GT_ADERR_OFS 0x470
108 
109 /* SDRAM Configuration. */
110 #define GT_SDRAM_CFG_OFS 0x448
111 
112 #define GT_SDRAM_OPMODE_OFS 0x474
113 #define GT_SDRAM_BM_OFS 0x478
114 #define GT_SDRAM_ADDRDECODE_OFS 0x47c
115 
116 /* SDRAM Parameters. */
117 #define GT_SDRAM_B0_OFS 0x44c
118 #define GT_SDRAM_B1_OFS 0x450
119 #define GT_SDRAM_B2_OFS 0x454
120 #define GT_SDRAM_B3_OFS 0x458
121 
122 /* Device Parameters. */
123 #define GT_DEV_B0_OFS 0x45c
124 #define GT_DEV_B1_OFS 0x460
125 #define GT_DEV_B2_OFS 0x464
126 #define GT_DEV_B3_OFS 0x468
127 #define GT_DEV_BOOT_OFS 0x46c
128 
129 /* ECC. */
130 #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
131 #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
132 #define GT_ECC_MEM 0x488 /* GT-64120A only */
133 #define GT_ECC_CALC 0x48c /* GT-64120A only */
134 #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
135 
136 /* DMA Record. */
137 #define GT_DMA0_CNT_OFS 0x800
138 #define GT_DMA1_CNT_OFS 0x804
139 #define GT_DMA2_CNT_OFS 0x808
140 #define GT_DMA3_CNT_OFS 0x80c
141 #define GT_DMA0_SA_OFS 0x810
142 #define GT_DMA1_SA_OFS 0x814
143 #define GT_DMA2_SA_OFS 0x818
144 #define GT_DMA3_SA_OFS 0x81c
145 #define GT_DMA0_DA_OFS 0x820
146 #define GT_DMA1_DA_OFS 0x824
147 #define GT_DMA2_DA_OFS 0x828
148 #define GT_DMA3_DA_OFS 0x82c
149 #define GT_DMA0_NEXT_OFS 0x830
150 #define GT_DMA1_NEXT_OFS 0x834
151 #define GT_DMA2_NEXT_OFS 0x838
152 #define GT_DMA3_NEXT_OFS 0x83c
153 
154 #define GT_DMA0_CUR_OFS 0x870
155 #define GT_DMA1_CUR_OFS 0x874
156 #define GT_DMA2_CUR_OFS 0x878
157 #define GT_DMA3_CUR_OFS 0x87c
158 
159 /* DMA Channel Control. */
160 #define GT_DMA0_CTRL_OFS 0x840
161 #define GT_DMA1_CTRL_OFS 0x844
162 #define GT_DMA2_CTRL_OFS 0x848
163 #define GT_DMA3_CTRL_OFS 0x84c
164 
165 /* DMA Arbiter. */
166 #define GT_DMA_ARB_OFS 0x860
167 
168 /* Timer/Counter. */
169 #define GT_TC0_OFS 0x850
170 #define GT_TC1_OFS 0x854
171 #define GT_TC2_OFS 0x858
172 #define GT_TC3_OFS 0x85c
173 
174 #define GT_TC_CONTROL_OFS 0x864
175 
176 /* PCI Internal. */
177 #define GT_PCI0_CMD_OFS 0xc00
178 #define GT_PCI0_TOR_OFS 0xc04
179 #define GT_PCI0_BS_SCS10_OFS 0xc08
180 #define GT_PCI0_BS_SCS32_OFS 0xc0c
181 #define GT_PCI0_BS_CS20_OFS 0xc10
182 #define GT_PCI0_BS_CS3BT_OFS 0xc14
183 
184 #define GT_PCI1_IACK_OFS 0xc30
185 #define GT_PCI0_IACK_OFS 0xc34
186 
187 #define GT_PCI0_BARE_OFS 0xc3c
188 #define GT_PCI0_PREFMBR_OFS 0xc40
189 
190 #define GT_PCI0_SCS10_BAR_OFS 0xc48
191 #define GT_PCI0_SCS32_BAR_OFS 0xc4c
192 #define GT_PCI0_CS20_BAR_OFS 0xc50
193 #define GT_PCI0_CS3BT_BAR_OFS 0xc54
194 #define GT_PCI0_SSCS10_BAR_OFS 0xc58
195 #define GT_PCI0_SSCS32_BAR_OFS 0xc5c
196 
197 #define GT_PCI0_SCS3BT_BAR_OFS 0xc64
198 
199 #define GT_PCI1_CMD_OFS 0xc80
200 #define GT_PCI1_TOR_OFS 0xc84
201 #define GT_PCI1_BS_SCS10_OFS 0xc88
202 #define GT_PCI1_BS_SCS32_OFS 0xc8c
203 #define GT_PCI1_BS_CS20_OFS 0xc90
204 #define GT_PCI1_BS_CS3BT_OFS 0xc94
205 
206 #define GT_PCI1_BARE_OFS 0xcbc
207 #define GT_PCI1_PREFMBR_OFS 0xcc0
208 
209 #define GT_PCI1_SCS10_BAR_OFS 0xcc8
210 #define GT_PCI1_SCS32_BAR_OFS 0xccc
211 #define GT_PCI1_CS20_BAR_OFS 0xcd0
212 #define GT_PCI1_CS3BT_BAR_OFS 0xcd4
213 #define GT_PCI1_SSCS10_BAR_OFS 0xcd8
214 #define GT_PCI1_SSCS32_BAR_OFS 0xcdc
215 
216 #define GT_PCI1_SCS3BT_BAR_OFS 0xce4
217 
218 #define GT_PCI1_CFGADDR_OFS 0xcf0
219 #define GT_PCI1_CFGDATA_OFS 0xcf4
220 #define GT_PCI0_CFGADDR_OFS 0xcf8
221 #define GT_PCI0_CFGDATA_OFS 0xcfc
222 
223 /* Interrupts. */
224 #define GT_INTRCAUSE_OFS 0xc18
225 #define GT_INTRMASK_OFS 0xc1c
226 
227 #define GT_PCI0_ICMASK_OFS 0xc24
228 #define GT_PCI0_SERR0MASK_OFS 0xc28
229 
230 #define GT_CPU_INTSEL_OFS 0xc70
231 #define GT_PCI0_INTSEL_OFS 0xc74
232 
233 #define GT_HINTRCAUSE_OFS 0xc98
234 #define GT_HINTRMASK_OFS 0xc9c
235 
236 #define GT_PCI0_HICMASK_OFS 0xca4
237 #define GT_PCI1_SERR1MASK_OFS 0xca8
238 
239 
240 /*
241  * I2O Support Registers
242  */
243 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
244 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
245 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
246 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
247 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
248 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
249 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
250 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
251 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
252 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
253 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
254 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
255 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
256 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
257 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
258 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
259 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
260 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
261 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
262 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
263 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
264 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
265 
266 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
267 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
268 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
269 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
270 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
271 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
272 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
273 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
274 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
275 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
276 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
277 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
278 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
279 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
280 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
281 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
282 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
283 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
284 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
285 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
286 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
287 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
288 
289 /*
290  * Register encodings
291  */
292 #define GT_CPU_ENDIAN_SHF 12
293 #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
294 #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
295 #define GT_CPU_WR_SHF 16
296 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
297 #define GT_CPU_WR_BIT GT_CPU_WR_MSK
298 #define GT_CPU_WR_DXDXDXDX 0
299 #define GT_CPU_WR_DDDD 1
300 
301 
302 #define GT_PCI_DCRM_SHF 21
303 #define GT_PCI_LD_SHF 0
304 #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
305 #define GT_PCI_HD_SHF 0
306 #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
307 #define GT_PCI_REMAP_SHF 0
308 #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
309 
310 
311 #define GT_CFGADDR_CFGEN_SHF 31
312 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
313 #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
314 
315 #define GT_CFGADDR_BUSNUM_SHF 16
316 #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
317 
318 #define GT_CFGADDR_DEVNUM_SHF 11
319 #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
320 
321 #define GT_CFGADDR_FUNCNUM_SHF 8
322 #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
323 
324 #define GT_CFGADDR_REGNUM_SHF 2
325 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
326 
327 
328 #define GT_SDRAM_BM_ORDER_SHF 2
329 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
330 #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
331 #define GT_SDRAM_BM_ORDER_SUB 1
332 #define GT_SDRAM_BM_ORDER_LIN 0
333 
334 #define GT_SDRAM_BM_RSVD_ALL1 0xffb
335 
336 
337 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
338 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
339 #define GT_SDRAM_ADDRDECODE_ADDR_0 0
340 #define GT_SDRAM_ADDRDECODE_ADDR_1 1
341 #define GT_SDRAM_ADDRDECODE_ADDR_2 2
342 #define GT_SDRAM_ADDRDECODE_ADDR_3 3
343 #define GT_SDRAM_ADDRDECODE_ADDR_4 4
344 #define GT_SDRAM_ADDRDECODE_ADDR_5 5
345 #define GT_SDRAM_ADDRDECODE_ADDR_6 6
346 #define GT_SDRAM_ADDRDECODE_ADDR_7 7
347 
348 
349 #define GT_SDRAM_B0_CASLAT_SHF 0
350 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
351 #define GT_SDRAM_B0_CASLAT_2 1
352 #define GT_SDRAM_B0_CASLAT_3 2
353 
354 #define GT_SDRAM_B0_FTDIS_SHF 2
355 #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
356 #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
357 
358 #define GT_SDRAM_B0_SRASPRCHG_SHF 3
359 #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
360 #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
361 #define GT_SDRAM_B0_SRASPRCHG_2 0
362 #define GT_SDRAM_B0_SRASPRCHG_3 1
363 
364 #define GT_SDRAM_B0_B0COMPAB_SHF 4
365 #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
366 #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
367 
368 #define GT_SDRAM_B0_64BITINT_SHF 5
369 #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
370 #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
371 #define GT_SDRAM_B0_64BITINT_2 0
372 #define GT_SDRAM_B0_64BITINT_4 1
373 
374 #define GT_SDRAM_B0_BW_SHF 6
375 #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
376 #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
377 #define GT_SDRAM_B0_BW_32 0
378 #define GT_SDRAM_B0_BW_64 1
379 
380 #define GT_SDRAM_B0_BLODD_SHF 7
381 #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
382 #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
383 
384 #define GT_SDRAM_B0_PAR_SHF 8
385 #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
386 #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
387 
388 #define GT_SDRAM_B0_BYPASS_SHF 9
389 #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
390 #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
391 
392 #define GT_SDRAM_B0_SRAS2SCAS_SHF 10
393 #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
394 #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
395 #define GT_SDRAM_B0_SRAS2SCAS_2 0
396 #define GT_SDRAM_B0_SRAS2SCAS_3 1
397 
398 #define GT_SDRAM_B0_SIZE_SHF 11
399 #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
400 #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
401 #define GT_SDRAM_B0_SIZE_16M 0
402 #define GT_SDRAM_B0_SIZE_64M 1
403 
404 #define GT_SDRAM_B0_EXTPAR_SHF 12
405 #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
406 #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
407 
408 #define GT_SDRAM_B0_BLEN_SHF 13
409 #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
410 #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
411 #define GT_SDRAM_B0_BLEN_8 0
412 #define GT_SDRAM_B0_BLEN_4 1
413 
414 
415 #define GT_SDRAM_CFG_REFINT_SHF 0
416 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
417 
418 #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
419 #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
420 #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
421 
422 #define GT_SDRAM_CFG_RMW_SHF 15
423 #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
424 #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
425 
426 #define GT_SDRAM_CFG_NONSTAGREF_SHF 16
427 #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
428 #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
429 
430 #define GT_SDRAM_CFG_DUPCNTL_SHF 19
431 #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
432 #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
433 
434 #define GT_SDRAM_CFG_DUPBA_SHF 20
435 #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
436 #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
437 
438 #define GT_SDRAM_CFG_DUPEOT0_SHF 21
439 #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
440 #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
441 
442 #define GT_SDRAM_CFG_DUPEOT1_SHF 22
443 #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
444 #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
445 
446 #define GT_SDRAM_OPMODE_OP_SHF 0
447 #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
448 #define GT_SDRAM_OPMODE_OP_NORMAL 0
449 #define GT_SDRAM_OPMODE_OP_NOP 1
450 #define GT_SDRAM_OPMODE_OP_PRCHG 2
451 #define GT_SDRAM_OPMODE_OP_MODE 3
452 #define GT_SDRAM_OPMODE_OP_CBR 4
453 
454 #define GT_TC_CONTROL_ENTC0_SHF 0
455 #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
456 #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
457 #define GT_TC_CONTROL_SELTC0_SHF 1
458 #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
459 #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
460 
461 
462 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
463 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
464 #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
465 
466 #define GT_PCI0_BARE_SWSCS32DIS_SHF 1
467 #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
468 #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
469 
470 #define GT_PCI0_BARE_SWSCS10DIS_SHF 2
471 #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
472 #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
473 
474 #define GT_PCI0_BARE_INTIODIS_SHF 3
475 #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
476 #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
477 
478 #define GT_PCI0_BARE_INTMEMDIS_SHF 4
479 #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
480 #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
481 
482 #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
483 #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
484 #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
485 
486 #define GT_PCI0_BARE_CS20DIS_SHF 6
487 #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
488 #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
489 
490 #define GT_PCI0_BARE_SCS32DIS_SHF 7
491 #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
492 #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
493 
494 #define GT_PCI0_BARE_SCS10DIS_SHF 8
495 #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
496 #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
497 
498 
499 #define GT_INTRCAUSE_MASABORT0_SHF 18
500 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
501 #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
502 
503 #define GT_INTRCAUSE_TARABORT0_SHF 19
504 #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
505 #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
506 
507 
508 #define GT_PCI0_CFGADDR_REGNUM_SHF 2
509 #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
510 #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
511 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
512 #define GT_PCI0_CFGADDR_DEVNUM_SHF 11
513 #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
514 #define GT_PCI0_CFGADDR_BUSNUM_SHF 16
515 #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
516 #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
517 #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
518 #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
519 
520 #define GT_PCI0_CMD_MBYTESWAP_SHF 0
521 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
522 #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
523 #define GT_PCI0_CMD_MWORDSWAP_SHF 10
524 #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
525 #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
526 #define GT_PCI0_CMD_SBYTESWAP_SHF 16
527 #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
528 #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
529 #define GT_PCI0_CMD_SWORDSWAP_SHF 11
530 #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
531 #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
532 
533 #define GT_INTR_T0EXP_SHF 8
534 #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
535 #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
536 #define GT_INTR_RETRYCTR0_SHF 20
537 #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
538 #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
539 
540 /*
541  * Misc
542  */
543 #define GT_DEF_PCI0_IO_BASE 0x10000000UL
544 #define GT_DEF_PCI0_IO_SIZE 0x02000000UL
545 #define GT_DEF_PCI0_MEM0_BASE 0x12000000UL
546 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
547 #define GT_DEF_BASE 0x14000000UL
548 
549 #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
550 #define GT_LATTIM_MIN 6 /* Minimum lat */
551 
552 /*
553  * The gt64120_dep.h file must define the following macros
554  *
555  * GT_READ(ofs, data_pointer)
556  * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit
557  *
558  * TIMER - gt64120 timer irq, temporary solution until
559  * full gt64120 cascade interrupt support is in place
560  */
561 
562 #include <mach-gt64120.h>
563 
564 /*
565  * Because of an error/peculiarity in the Galileo chip, we need to swap the
566  * bytes when running bigendian. We also provide non-swapping versions.
567  */
568 #define __GT_READ(ofs) \
569  (*(volatile u32 *)(GT64120_BASE+(ofs)))
570 #define __GT_WRITE(ofs, data) \
571  do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
572 #define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
573 #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
574 
575 extern void gt641xx_set_base_clock(unsigned int clock);
576 extern int gt641xx_timer0_state(void);
577 
578 #endif /* _ASM_GT64120_H */