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hd64461.h File Reference
#include <asm/io_generic.h>

Go to the source code of this file.

Macros

#define HD64461_PCC_WINDOW   0x01000000
 
#define HD64461_IOBASE   0xb0000000
 
#define HD64461_IO_OFFSET(x)   (HD64461_IOBASE + (x))
 
#define HD64461_PCC0_BASE   HD64461_IO_OFFSET(0x8000000)
 
#define HD64461_PCC0_ATTR   (HD64461_PCC0_BASE) /* 0xb80000000 */
 
#define HD64461_PCC0_COMM   (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
 
#define HD64461_PCC0_IO   (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
 
#define HD64461_PCC1_BASE   HD64461_IO_OFFSET(0x4000000)
 
#define HD64461_PCC1_ATTR   (HD64461_PCC1_BASE) /* 0xb4000000 */
 
#define HD64461_PCC1_COMM   (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
 
#define HD64461_STBCR   HD64461_IO_OFFSET(0x00000000)
 
#define HD64461_STBCR_CKIO_STBY   0x2000
 
#define HD64461_STBCR_SAFECKE_IST   0x1000
 
#define HD64461_STBCR_SLCKE_IST   0x0800
 
#define HD64461_STBCR_SAFECKE_OST   0x0400
 
#define HD64461_STBCR_SLCKE_OST   0x0200
 
#define HD64461_STBCR_SMIAST   0x0100
 
#define HD64461_STBCR_SLCDST   0x0080
 
#define HD64461_STBCR_SPC0ST   0x0040
 
#define HD64461_STBCR_SPC1ST   0x0020
 
#define HD64461_STBCR_SAFEST   0x0010
 
#define HD64461_STBCR_STM0ST   0x0008
 
#define HD64461_STBCR_STM1ST   0x0004
 
#define HD64461_STBCR_SIRST   0x0002
 
#define HD64461_STBCR_SURTST   0x0001
 
#define HD64461_SYSCR   HD64461_IO_OFFSET(0x02)
 
#define HD64461_SCPUCR   HD64461_IO_OFFSET(0x04)
 
#define HD64461_LCDCBAR   HD64461_IO_OFFSET(0x1000)
 
#define HD64461_LCDCLOR   HD64461_IO_OFFSET(0x1002)
 
#define HD64461_LCDCCR   HD64461_IO_OFFSET(0x1004)
 
#define HD64461_LCDCCR_STBACK   0x0400 /* Standby Back */
 
#define HD64461_LCDCCR_STREQ   0x0100 /* Standby Request */
 
#define HD64461_LCDCCR_MOFF   0x0080 /* Memory Off */
 
#define HD64461_LCDCCR_REFSEL   0x0040 /* Refresh Select */
 
#define HD64461_LCDCCR_EPON   0x0020 /* End Power On */
 
#define HD64461_LCDCCR_SPON   0x0010 /* Start Power On */
 
#define HD64461_LDR1   HD64461_IO_OFFSET(0x1010)
 
#define HD64461_LDR1_DON   0x01 /* Display On */
 
#define HD64461_LDR1_DINV   0x80 /* Display Invert */
 
#define HD64461_LDR2   HD64461_IO_OFFSET(0x1012)
 
#define HD64461_LDHNCR   HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
 
#define HD64461_LDHNSR   HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
 
#define HD64461_LDVNTR   HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
 
#define HD64461_LDVNDR   HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
 
#define HD64461_LDVSPR   HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
 
#define HD64461_LDR3   HD64461_IO_OFFSET(0x101e)
 
#define HD64461_CPTWAR   HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
 
#define HD64461_CPTWDR   HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
 
#define HD64461_CPTRAR   HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
 
#define HD64461_CPTRDR   HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
 
#define HD64461_GRDOR   HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
 
#define HD64461_GRSCR   HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
 
#define HD64461_GRCFGR   HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
 
#define HD64461_GRCFGR_ACCSTATUS   0x10 /* Accelerator Status */
 
#define HD64461_GRCFGR_ACCRESET   0x08 /* Accelerator Reset */
 
#define HD64461_GRCFGR_ACCSTART_BITBLT   0x06 /* Accelerator Start BITBLT */
 
#define HD64461_GRCFGR_ACCSTART_LINE   0x04 /* Accelerator Start Line Drawing */
 
#define HD64461_GRCFGR_COLORDEPTH16   0x01 /* Sets Colordepth 16 for Accelerator */
 
#define HD64461_GRCFGR_COLORDEPTH8   0x01 /* Sets Colordepth 8 for Accelerator */
 
#define HD64461_LNSARH   HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
 
#define HD64461_LNSARL   HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
 
#define HD64461_LNAXLR   HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
 
#define HD64461_LNDGR   HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
 
#define HD64461_LNAXR   HD64461_IO_OFFSET(0x104e) /* Axial Register */
 
#define HD64461_LNERTR   HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
 
#define HD64461_LNMDR   HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
 
#define HD64461_BBTSSARH   HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
 
#define HD64461_BBTSSARL   HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
 
#define HD64461_BBTDSARH   HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
 
#define HD64461_BBTDSARL   HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
 
#define HD64461_BBTDWR   HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
 
#define HD64461_BBTDHR   HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
 
#define HD64461_BBTPARH   HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
 
#define HD64461_BBTPARL   HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
 
#define HD64461_BBTMARH   HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
 
#define HD64461_BBTMARL   HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
 
#define HD64461_BBTROPR   HD64461_IO_OFFSET(0x1068) /* ROP Register */
 
#define HD64461_BBTMDR   HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
 
#define HD64461_PCC0ISR   HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
 
#define HD64461_PCC0GCR   HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
 
#define HD64461_PCC0CSCR   HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
 
#define HD64461_PCC0CSCIER   HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
 
#define HD64461_PCC0SCR   HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
 
#define HD64461_PCC1ISR   HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
 
#define HD64461_PCC1GCR   HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
 
#define HD64461_PCC1CSCR   HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
 
#define HD64461_PCC1CSCIER   HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
 
#define HD64461_PCC1SCR   HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
 
#define HD64461_PCCISR_READY   0x80 /* card ready */
 
#define HD64461_PCCISR_MWP   0x40 /* card write-protected */
 
#define HD64461_PCCISR_VS2   0x20 /* voltage select pin 2 */
 
#define HD64461_PCCISR_VS1   0x10 /* voltage select pin 1 */
 
#define HD64461_PCCISR_CD2   0x08 /* card detect 2 */
 
#define HD64461_PCCISR_CD1   0x04 /* card detect 1 */
 
#define HD64461_PCCISR_BVD2   0x02 /* battery 1 */
 
#define HD64461_PCCISR_BVD1   0x01 /* battery 1 */
 
#define HD64461_PCCISR_PCD_MASK   0x0c /* card detect */
 
#define HD64461_PCCISR_BVD_MASK   0x03 /* battery voltage */
 
#define HD64461_PCCISR_BVD_BATGOOD   0x03 /* battery good */
 
#define HD64461_PCCISR_BVD_BATWARN   0x01 /* battery low warning */
 
#define HD64461_PCCISR_BVD_BATDEAD1   0x02 /* battery dead */
 
#define HD64461_PCCISR_BVD_BATDEAD2   0x00 /* battery dead */
 
#define HD64461_PCCGCR_DRVE   0x80 /* output drive */
 
#define HD64461_PCCGCR_PCCR   0x40 /* PC card reset */
 
#define HD64461_PCCGCR_PCCT   0x20 /* PC card type, 1=IO&mem, 0=mem */
 
#define HD64461_PCCGCR_VCC0   0x10 /* voltage control pin VCC0SEL0 */
 
#define HD64461_PCCGCR_PMMOD   0x08 /* memory mode */
 
#define HD64461_PCCGCR_PA25   0x04 /* pin A25 */
 
#define HD64461_PCCGCR_PA24   0x02 /* pin A24 */
 
#define HD64461_PCCGCR_REG   0x01 /* pin PCC0REG# */
 
#define HD64461_PCCCSCR_SCDI   0x80 /* sw card detect intr */
 
#define HD64461_PCCCSCR_SRV1   0x40 /* reserved */
 
#define HD64461_PCCCSCR_IREQ   0x20 /* IREQ intr req */
 
#define HD64461_PCCCSCR_SC   0x10 /* STSCHG (status change) pin */
 
#define HD64461_PCCCSCR_CDC   0x08 /* CD (card detect) change */
 
#define HD64461_PCCCSCR_RC   0x04 /* READY change */
 
#define HD64461_PCCCSCR_BW   0x02 /* battery warning change */
 
#define HD64461_PCCCSCR_BD   0x01 /* battery dead change */
 
#define HD64461_PCCCSCIER_CRE   0x80 /* change reset enable */
 
#define HD64461_PCCCSCIER_IREQE_MASK   0x60 /* IREQ enable */
 
#define HD64461_PCCCSCIER_IREQE_DISABLED   0x00 /* IREQ disabled */
 
#define HD64461_PCCCSCIER_IREQE_LEVEL   0x20 /* IREQ level-triggered */
 
#define HD64461_PCCCSCIER_IREQE_FALLING   0x40 /* IREQ falling-edge-trig */
 
#define HD64461_PCCCSCIER_IREQE_RISING   0x60 /* IREQ rising-edge-trig */
 
#define HD64461_PCCCSCIER_SCE   0x10 /* status change enable */
 
#define HD64461_PCCCSCIER_CDE   0x08 /* card detect change enable */
 
#define HD64461_PCCCSCIER_RE   0x04 /* ready change enable */
 
#define HD64461_PCCCSCIER_BWE   0x02 /* battery warn change enable */
 
#define HD64461_PCCCSCIER_BDE   0x01 /* battery dead change enable*/
 
#define HD64461_PCCSCR_VCC1   0x02 /* voltage control pin 1 */
 
#define HD64461_PCCSCR_SWP   0x01 /* write protect */
 
#define HD64461_P0OCR   HD64461_IO_OFFSET(0x202a)
 
#define HD64461_P1OCR   HD64461_IO_OFFSET(0x202c)
 
#define HD64461_PGCR   HD64461_IO_OFFSET(0x202e)
 
#define HD64461_GPACR   HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
 
#define HD64461_GPBCR   HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
 
#define HD64461_GPCCR   HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
 
#define HD64461_GPDCR   HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
 
#define HD64461_GPADR   HD64461_IO_OFFSET(0x4010) /* A */
 
#define HD64461_GPBDR   HD64461_IO_OFFSET(0x4012) /* B */
 
#define HD64461_GPCDR   HD64461_IO_OFFSET(0x4014) /* C */
 
#define HD64461_GPDDR   HD64461_IO_OFFSET(0x4016) /* D */
 
#define HD64461_GPAICR   HD64461_IO_OFFSET(0x4020) /* A */
 
#define HD64461_GPBICR   HD64461_IO_OFFSET(0x4022) /* B */
 
#define HD64461_GPCICR   HD64461_IO_OFFSET(0x4024) /* C */
 
#define HD64461_GPDICR   HD64461_IO_OFFSET(0x4026) /* D */
 
#define HD64461_GPAISR   HD64461_IO_OFFSET(0x4040) /* A */
 
#define HD64461_GPBISR   HD64461_IO_OFFSET(0x4042) /* B */
 
#define HD64461_GPCISR   HD64461_IO_OFFSET(0x4044) /* C */
 
#define HD64461_GPDISR   HD64461_IO_OFFSET(0x4046) /* D */
 
#define HD64461_NIRR   HD64461_IO_OFFSET(0x5000)
 
#define HD64461_NIMR   HD64461_IO_OFFSET(0x5002)
 
#define HD64461_IRQBASE   OFFCHIP_IRQ_BASE
 
#define OFFCHIP_IRQ_BASE   64
 
#define HD64461_IRQ_NUM   16
 
#define HD64461_IRQ_UART   (HD64461_IRQBASE+5)
 
#define HD64461_IRQ_IRDA   (HD64461_IRQBASE+6)
 
#define HD64461_IRQ_TMU1   (HD64461_IRQBASE+9)
 
#define HD64461_IRQ_TMU0   (HD64461_IRQBASE+10)
 
#define HD64461_IRQ_GPIO   (HD64461_IRQBASE+11)
 
#define HD64461_IRQ_AFE   (HD64461_IRQBASE+12)
 
#define HD64461_IRQ_PCC1   (HD64461_IRQBASE+13)
 
#define HD64461_IRQ_PCC0   (HD64461_IRQBASE+14)
 
#define __IO_PREFIX   hd64461
 

Functions

void hd64461_register_irq_demux (int irq, int(*demux)(int irq, void *dev), void *dev)
 
void hd64461_unregister_irq_demux (int irq)
 

Macro Definition Documentation

#define __IO_PREFIX   hd64461

Definition at line 243 of file hd64461.h.

#define HD64461_BBTDHR   HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */

Definition at line 116 of file hd64461.h.

#define HD64461_BBTDSARH   HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */

Definition at line 113 of file hd64461.h.

#define HD64461_BBTDSARL   HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */

Definition at line 114 of file hd64461.h.

#define HD64461_BBTDWR   HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */

Definition at line 115 of file hd64461.h.

#define HD64461_BBTMARH   HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */

Definition at line 119 of file hd64461.h.

#define HD64461_BBTMARL   HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */

Definition at line 120 of file hd64461.h.

#define HD64461_BBTMDR   HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */

Definition at line 122 of file hd64461.h.

#define HD64461_BBTPARH   HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */

Definition at line 117 of file hd64461.h.

#define HD64461_BBTPARL   HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */

Definition at line 118 of file hd64461.h.

#define HD64461_BBTROPR   HD64461_IO_OFFSET(0x1068) /* ROP Register */

Definition at line 121 of file hd64461.h.

#define HD64461_BBTSSARH   HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */

Definition at line 111 of file hd64461.h.

#define HD64461_BBTSSARL   HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */

Definition at line 112 of file hd64461.h.

#define HD64461_CPTRAR   HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */

Definition at line 87 of file hd64461.h.

#define HD64461_CPTRDR   HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */

Definition at line 88 of file hd64461.h.

#define HD64461_CPTWAR   HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */

Definition at line 85 of file hd64461.h.

#define HD64461_CPTWDR   HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */

Definition at line 86 of file hd64461.h.

#define HD64461_GPACR   HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */

Definition at line 203 of file hd64461.h.

#define HD64461_GPADR   HD64461_IO_OFFSET(0x4010) /* A */

Definition at line 209 of file hd64461.h.

#define HD64461_GPAICR   HD64461_IO_OFFSET(0x4020) /* A */

Definition at line 215 of file hd64461.h.

#define HD64461_GPAISR   HD64461_IO_OFFSET(0x4040) /* A */

Definition at line 221 of file hd64461.h.

#define HD64461_GPBCR   HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */

Definition at line 204 of file hd64461.h.

#define HD64461_GPBDR   HD64461_IO_OFFSET(0x4012) /* B */

Definition at line 210 of file hd64461.h.

#define HD64461_GPBICR   HD64461_IO_OFFSET(0x4022) /* B */

Definition at line 216 of file hd64461.h.

#define HD64461_GPBISR   HD64461_IO_OFFSET(0x4042) /* B */

Definition at line 222 of file hd64461.h.

#define HD64461_GPCCR   HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */

Definition at line 205 of file hd64461.h.

#define HD64461_GPCDR   HD64461_IO_OFFSET(0x4014) /* C */

Definition at line 211 of file hd64461.h.

#define HD64461_GPCICR   HD64461_IO_OFFSET(0x4024) /* C */

Definition at line 217 of file hd64461.h.

#define HD64461_GPCISR   HD64461_IO_OFFSET(0x4044) /* C */

Definition at line 223 of file hd64461.h.

#define HD64461_GPDCR   HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */

Definition at line 206 of file hd64461.h.

#define HD64461_GPDDR   HD64461_IO_OFFSET(0x4016) /* D */

Definition at line 212 of file hd64461.h.

#define HD64461_GPDICR   HD64461_IO_OFFSET(0x4026) /* D */

Definition at line 218 of file hd64461.h.

#define HD64461_GPDISR   HD64461_IO_OFFSET(0x4046) /* D */

Definition at line 224 of file hd64461.h.

#define HD64461_GRCFGR   HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */

Definition at line 92 of file hd64461.h.

#define HD64461_GRCFGR_ACCRESET   0x08 /* Accelerator Reset */

Definition at line 95 of file hd64461.h.

#define HD64461_GRCFGR_ACCSTART_BITBLT   0x06 /* Accelerator Start BITBLT */

Definition at line 96 of file hd64461.h.

#define HD64461_GRCFGR_ACCSTART_LINE   0x04 /* Accelerator Start Line Drawing */

Definition at line 97 of file hd64461.h.

#define HD64461_GRCFGR_ACCSTATUS   0x10 /* Accelerator Status */

Definition at line 94 of file hd64461.h.

#define HD64461_GRCFGR_COLORDEPTH16   0x01 /* Sets Colordepth 16 for Accelerator */

Definition at line 98 of file hd64461.h.

#define HD64461_GRCFGR_COLORDEPTH8   0x01 /* Sets Colordepth 8 for Accelerator */

Definition at line 99 of file hd64461.h.

#define HD64461_GRDOR   HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */

Definition at line 90 of file hd64461.h.

#define HD64461_GRSCR   HD64461_IO_OFFSET(0x1042) /* Solid Color Register */

Definition at line 91 of file hd64461.h.

#define HD64461_IO_OFFSET (   x)    (HD64461_IOBASE + (x))

Definition at line 17 of file hd64461.h.

#define HD64461_IOBASE   0xb0000000

Definition at line 16 of file hd64461.h.

#define HD64461_IRQ_AFE   (HD64461_IRQBASE+12)

Definition at line 239 of file hd64461.h.

#define HD64461_IRQ_GPIO   (HD64461_IRQBASE+11)

Definition at line 238 of file hd64461.h.

#define HD64461_IRQ_IRDA   (HD64461_IRQBASE+6)

Definition at line 235 of file hd64461.h.

#define HD64461_IRQ_NUM   16

Definition at line 232 of file hd64461.h.

#define HD64461_IRQ_PCC0   (HD64461_IRQBASE+14)

Definition at line 241 of file hd64461.h.

#define HD64461_IRQ_PCC1   (HD64461_IRQBASE+13)

Definition at line 240 of file hd64461.h.

#define HD64461_IRQ_TMU0   (HD64461_IRQBASE+10)

Definition at line 237 of file hd64461.h.

#define HD64461_IRQ_TMU1   (HD64461_IRQBASE+9)

Definition at line 236 of file hd64461.h.

#define HD64461_IRQ_UART   (HD64461_IRQBASE+5)

Definition at line 234 of file hd64461.h.

#define HD64461_IRQBASE   OFFCHIP_IRQ_BASE

Definition at line 230 of file hd64461.h.

#define HD64461_LCDCBAR   HD64461_IO_OFFSET(0x1000)

Definition at line 52 of file hd64461.h.

#define HD64461_LCDCCR   HD64461_IO_OFFSET(0x1004)

Definition at line 58 of file hd64461.h.

#define HD64461_LCDCCR_EPON   0x0020 /* End Power On */

Definition at line 65 of file hd64461.h.

#define HD64461_LCDCCR_MOFF   0x0080 /* Memory Off */

Definition at line 63 of file hd64461.h.

#define HD64461_LCDCCR_REFSEL   0x0040 /* Refresh Select */

Definition at line 64 of file hd64461.h.

#define HD64461_LCDCCR_SPON   0x0010 /* Start Power On */

Definition at line 66 of file hd64461.h.

#define HD64461_LCDCCR_STBACK   0x0400 /* Standby Back */

Definition at line 61 of file hd64461.h.

#define HD64461_LCDCCR_STREQ   0x0100 /* Standby Request */

Definition at line 62 of file hd64461.h.

#define HD64461_LCDCLOR   HD64461_IO_OFFSET(0x1002)

Definition at line 55 of file hd64461.h.

#define HD64461_LDHNCR   HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */

Definition at line 75 of file hd64461.h.

#define HD64461_LDHNSR   HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */

Definition at line 76 of file hd64461.h.

#define HD64461_LDR1   HD64461_IO_OFFSET(0x1010)

Definition at line 69 of file hd64461.h.

#define HD64461_LDR1_DINV   0x80 /* Display Invert */

Definition at line 71 of file hd64461.h.

#define HD64461_LDR1_DON   0x01 /* Display On */

Definition at line 70 of file hd64461.h.

#define HD64461_LDR2   HD64461_IO_OFFSET(0x1012)

Definition at line 74 of file hd64461.h.

#define HD64461_LDR3   HD64461_IO_OFFSET(0x101e)

Definition at line 82 of file hd64461.h.

#define HD64461_LDVNDR   HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */

Definition at line 78 of file hd64461.h.

#define HD64461_LDVNTR   HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */

Definition at line 77 of file hd64461.h.

#define HD64461_LDVSPR   HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */

Definition at line 79 of file hd64461.h.

#define HD64461_LNAXLR   HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */

Definition at line 104 of file hd64461.h.

#define HD64461_LNAXR   HD64461_IO_OFFSET(0x104e) /* Axial Register */

Definition at line 106 of file hd64461.h.

#define HD64461_LNDGR   HD64461_IO_OFFSET(0x104c) /* Diagonal Register */

Definition at line 105 of file hd64461.h.

#define HD64461_LNERTR   HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */

Definition at line 107 of file hd64461.h.

#define HD64461_LNMDR   HD64461_IO_OFFSET(0x1052) /* Line Mode Register */

Definition at line 108 of file hd64461.h.

#define HD64461_LNSARH   HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */

Definition at line 102 of file hd64461.h.

#define HD64461_LNSARL   HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */

Definition at line 103 of file hd64461.h.

#define HD64461_NIMR   HD64461_IO_OFFSET(0x5002)

Definition at line 228 of file hd64461.h.

#define HD64461_NIRR   HD64461_IO_OFFSET(0x5000)

Definition at line 227 of file hd64461.h.

#define HD64461_P0OCR   HD64461_IO_OFFSET(0x202a)

Definition at line 194 of file hd64461.h.

#define HD64461_P1OCR   HD64461_IO_OFFSET(0x202c)

Definition at line 197 of file hd64461.h.

#define HD64461_PCC0_ATTR   (HD64461_PCC0_BASE) /* 0xb80000000 */

Definition at line 19 of file hd64461.h.

#define HD64461_PCC0_BASE   HD64461_IO_OFFSET(0x8000000)

Definition at line 18 of file hd64461.h.

#define HD64461_PCC0_COMM   (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */

Definition at line 20 of file hd64461.h.

#define HD64461_PCC0_IO   (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */

Definition at line 21 of file hd64461.h.

#define HD64461_PCC0CSCIER   HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */

Definition at line 129 of file hd64461.h.

#define HD64461_PCC0CSCR   HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */

Definition at line 128 of file hd64461.h.

#define HD64461_PCC0GCR   HD64461_IO_OFFSET(0x2002) /* socket 0 general control */

Definition at line 127 of file hd64461.h.

#define HD64461_PCC0ISR   HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */

Definition at line 126 of file hd64461.h.

#define HD64461_PCC0SCR   HD64461_IO_OFFSET(0x2008) /* socket 0 software control */

Definition at line 130 of file hd64461.h.

#define HD64461_PCC1_ATTR   (HD64461_PCC1_BASE) /* 0xb4000000 */

Definition at line 25 of file hd64461.h.

#define HD64461_PCC1_BASE   HD64461_IO_OFFSET(0x4000000)

Definition at line 24 of file hd64461.h.

#define HD64461_PCC1_COMM   (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */

Definition at line 26 of file hd64461.h.

#define HD64461_PCC1CSCIER   HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */

Definition at line 135 of file hd64461.h.

#define HD64461_PCC1CSCR   HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */

Definition at line 134 of file hd64461.h.

#define HD64461_PCC1GCR   HD64461_IO_OFFSET(0x2012) /* socket 1 general control */

Definition at line 133 of file hd64461.h.

#define HD64461_PCC1ISR   HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */

Definition at line 132 of file hd64461.h.

#define HD64461_PCC1SCR   HD64461_IO_OFFSET(0x2018) /* socket 1 software control */

Definition at line 136 of file hd64461.h.

#define HD64461_PCC_WINDOW   0x01000000

Definition at line 13 of file hd64461.h.

#define HD64461_PCCCSCIER_BDE   0x01 /* battery dead change enable*/

Definition at line 187 of file hd64461.h.

#define HD64461_PCCCSCIER_BWE   0x02 /* battery warn change enable */

Definition at line 186 of file hd64461.h.

#define HD64461_PCCCSCIER_CDE   0x08 /* card detect change enable */

Definition at line 184 of file hd64461.h.

#define HD64461_PCCCSCIER_CRE   0x80 /* change reset enable */

Definition at line 176 of file hd64461.h.

#define HD64461_PCCCSCIER_IREQE_DISABLED   0x00 /* IREQ disabled */

Definition at line 178 of file hd64461.h.

#define HD64461_PCCCSCIER_IREQE_FALLING   0x40 /* IREQ falling-edge-trig */

Definition at line 180 of file hd64461.h.

#define HD64461_PCCCSCIER_IREQE_LEVEL   0x20 /* IREQ level-triggered */

Definition at line 179 of file hd64461.h.

#define HD64461_PCCCSCIER_IREQE_MASK   0x60 /* IREQ enable */

Definition at line 177 of file hd64461.h.

#define HD64461_PCCCSCIER_IREQE_RISING   0x60 /* IREQ rising-edge-trig */

Definition at line 181 of file hd64461.h.

#define HD64461_PCCCSCIER_RE   0x04 /* ready change enable */

Definition at line 185 of file hd64461.h.

#define HD64461_PCCCSCIER_SCE   0x10 /* status change enable */

Definition at line 183 of file hd64461.h.

#define HD64461_PCCCSCR_BD   0x01 /* battery dead change */

Definition at line 173 of file hd64461.h.

#define HD64461_PCCCSCR_BW   0x02 /* battery warning change */

Definition at line 172 of file hd64461.h.

#define HD64461_PCCCSCR_CDC   0x08 /* CD (card detect) change */

Definition at line 170 of file hd64461.h.

#define HD64461_PCCCSCR_IREQ   0x20 /* IREQ intr req */

Definition at line 168 of file hd64461.h.

#define HD64461_PCCCSCR_RC   0x04 /* READY change */

Definition at line 171 of file hd64461.h.

#define HD64461_PCCCSCR_SC   0x10 /* STSCHG (status change) pin */

Definition at line 169 of file hd64461.h.

#define HD64461_PCCCSCR_SCDI   0x80 /* sw card detect intr */

Definition at line 166 of file hd64461.h.

#define HD64461_PCCCSCR_SRV1   0x40 /* reserved */

Definition at line 167 of file hd64461.h.

#define HD64461_PCCGCR_DRVE   0x80 /* output drive */

Definition at line 156 of file hd64461.h.

#define HD64461_PCCGCR_PA24   0x02 /* pin A24 */

Definition at line 162 of file hd64461.h.

#define HD64461_PCCGCR_PA25   0x04 /* pin A25 */

Definition at line 161 of file hd64461.h.

#define HD64461_PCCGCR_PCCR   0x40 /* PC card reset */

Definition at line 157 of file hd64461.h.

#define HD64461_PCCGCR_PCCT   0x20 /* PC card type, 1=IO&mem, 0=mem */

Definition at line 158 of file hd64461.h.

#define HD64461_PCCGCR_PMMOD   0x08 /* memory mode */

Definition at line 160 of file hd64461.h.

#define HD64461_PCCGCR_REG   0x01 /* pin PCC0REG# */

Definition at line 163 of file hd64461.h.

#define HD64461_PCCGCR_VCC0   0x10 /* voltage control pin VCC0SEL0 */

Definition at line 159 of file hd64461.h.

#define HD64461_PCCISR_BVD1   0x01 /* battery 1 */

Definition at line 146 of file hd64461.h.

#define HD64461_PCCISR_BVD2   0x02 /* battery 1 */

Definition at line 145 of file hd64461.h.

#define HD64461_PCCISR_BVD_BATDEAD1   0x02 /* battery dead */

Definition at line 152 of file hd64461.h.

#define HD64461_PCCISR_BVD_BATDEAD2   0x00 /* battery dead */

Definition at line 153 of file hd64461.h.

#define HD64461_PCCISR_BVD_BATGOOD   0x03 /* battery good */

Definition at line 150 of file hd64461.h.

#define HD64461_PCCISR_BVD_BATWARN   0x01 /* battery low warning */

Definition at line 151 of file hd64461.h.

#define HD64461_PCCISR_BVD_MASK   0x03 /* battery voltage */

Definition at line 149 of file hd64461.h.

#define HD64461_PCCISR_CD1   0x04 /* card detect 1 */

Definition at line 144 of file hd64461.h.

#define HD64461_PCCISR_CD2   0x08 /* card detect 2 */

Definition at line 143 of file hd64461.h.

#define HD64461_PCCISR_MWP   0x40 /* card write-protected */

Definition at line 140 of file hd64461.h.

#define HD64461_PCCISR_PCD_MASK   0x0c /* card detect */

Definition at line 148 of file hd64461.h.

#define HD64461_PCCISR_READY   0x80 /* card ready */

Definition at line 139 of file hd64461.h.

#define HD64461_PCCISR_VS1   0x10 /* voltage select pin 1 */

Definition at line 142 of file hd64461.h.

#define HD64461_PCCISR_VS2   0x20 /* voltage select pin 2 */

Definition at line 141 of file hd64461.h.

#define HD64461_PCCSCR_SWP   0x01 /* write protect */

Definition at line 191 of file hd64461.h.

#define HD64461_PCCSCR_VCC1   0x02 /* voltage control pin 1 */

Definition at line 190 of file hd64461.h.

#define HD64461_PGCR   HD64461_IO_OFFSET(0x202e)

Definition at line 200 of file hd64461.h.

#define HD64461_SCPUCR   HD64461_IO_OFFSET(0x04)

Definition at line 49 of file hd64461.h.

#define HD64461_STBCR   HD64461_IO_OFFSET(0x00000000)

Definition at line 29 of file hd64461.h.

#define HD64461_STBCR_CKIO_STBY   0x2000

Definition at line 30 of file hd64461.h.

#define HD64461_STBCR_SAFECKE_IST   0x1000

Definition at line 31 of file hd64461.h.

#define HD64461_STBCR_SAFECKE_OST   0x0400

Definition at line 33 of file hd64461.h.

#define HD64461_STBCR_SAFEST   0x0010

Definition at line 39 of file hd64461.h.

#define HD64461_STBCR_SIRST   0x0002

Definition at line 42 of file hd64461.h.

#define HD64461_STBCR_SLCDST   0x0080

Definition at line 36 of file hd64461.h.

#define HD64461_STBCR_SLCKE_IST   0x0800

Definition at line 32 of file hd64461.h.

#define HD64461_STBCR_SLCKE_OST   0x0200

Definition at line 34 of file hd64461.h.

#define HD64461_STBCR_SMIAST   0x0100

Definition at line 35 of file hd64461.h.

#define HD64461_STBCR_SPC0ST   0x0040

Definition at line 37 of file hd64461.h.

#define HD64461_STBCR_SPC1ST   0x0020

Definition at line 38 of file hd64461.h.

#define HD64461_STBCR_STM0ST   0x0008

Definition at line 40 of file hd64461.h.

#define HD64461_STBCR_STM1ST   0x0004

Definition at line 41 of file hd64461.h.

#define HD64461_STBCR_SURTST   0x0001

Definition at line 43 of file hd64461.h.

#define HD64461_SYSCR   HD64461_IO_OFFSET(0x02)

Definition at line 46 of file hd64461.h.

#define OFFCHIP_IRQ_BASE   64

Definition at line 231 of file hd64461.h.

Function Documentation

void hd64461_register_irq_demux ( int  irq,
int(*)(int irq, void *dev demux,
void dev 
)
void hd64461_unregister_irq_demux ( int  irq)