Data Structures
struct	pcsca_bd_t

struct	pkt_desc

Macros
#define	ILAR 0x00

#define	PABR0L 0x20 /* Physical Addr Boundary Register 0 L */

#define	PABR0H 0x21 /* Physical Addr Boundary Register 0 H */

#define	PABR1L 0x22 /* Physical Addr Boundary Register 1 L */

#define	PABR1H 0x23 /* Physical Addr Boundary Register 1 H */

#define	WCRL 0x24 /* Wait Control Register L */

#define	WCRM 0x25 /* Wait Control Register M */

#define	WCRH 0x26 /* Wait Control Register H */

#define	IVR 0x60 /* Interrupt Vector Register */

#define	IMVR 0x64 /* Interrupt Modified Vector Register */

#define	ITCR 0x68 /* Interrupt Control Register */

#define	ISR0 0x6c /* Interrupt Status Register 0 */

#define	ISR1 0x70 /* Interrupt Status Register 1 */

#define	IER0 0x74 /* Interrupt Enable Register 0 */

#define	IER1 0x78 /* Interrupt Enable Register 1 */

#define	M_REG(reg, chan) (reg + 0x80chan) / MSCI */

#define	DRX_REG(reg, chan) (reg + 0x40chan) / DMA Rx */

#define	DTX_REG(reg, chan) (reg + 0x20(2chan + 1)) /* DMA Tx */

#define	TRX_REG(reg, chan) (reg + 0x20chan) / Timer Rx */

#define	TTX_REG(reg, chan) (reg + 0x10(2chan + 1)) /* Timer Tx */

#define	ST_REG(reg, chan) (reg + 0x80chan) / Status Cnt */

#define	IR0_DRX(val, chan) ((val)<<(8(chan))) / Int DMA Rx */

#define	IR0_DTX(val, chan) ((val)<<(4(2chan + 1))) /* Int DMA Tx */

#define	IR0_M(val, chan) ((val)<<(8(chan))) / Int MSCI */

#define	MSCI0_OFFSET 0x00

#define	MSCI1_OFFSET 0x80

#define	MD0 0x138 /* Mode reg 0 */

#define	MD1 0x139 /* Mode reg 1 */

#define	MD2 0x13a /* Mode reg 2 */

#define	MD3 0x13b /* Mode reg 3 */

#define	CTL 0x130 /* Control reg */

#define	RXS 0x13c /* RX clock source */

#define	TXS 0x13d /* TX clock source */

#define	EXS 0x13e /* External clock input selection */

#define	TMCT 0x144 /* Time constant (Tx) */

#define	TMCR 0x145 /* Time constant (Rx) */

#define	CMD 0x128 /* Command reg */

#define	ST0 0x118 /* Status reg 0 */

#define	ST1 0x119 /* Status reg 1 */

#define	ST2 0x11a /* Status reg 2 */

#define	ST3 0x11b /* Status reg 3 */

#define	ST4 0x11c /* Status reg 4 */

#define	FST 0x11d /* frame Status reg */

#define	IE0 0x120 /* Interrupt enable reg 0 */

#define	IE1 0x121 /* Interrupt enable reg 1 */

#define	IE2 0x122 /* Interrupt enable reg 2 */

#define	IE4 0x124 /* Interrupt enable reg 4 */

#define	FIE 0x125 /* Frame Interrupt enable reg */

#define	SA0 0x140 /* Syn Address reg 0 */

#define	SA1 0x141 /* Syn Address reg 1 */

#define	IDL 0x142 /* Idle register */

#define	TRBL 0x100 /* TX/RX buffer reg L */

#define	TRBK 0x101 /* TX/RX buffer reg K */

#define	TRBJ 0x102 /* TX/RX buffer reg J */

#define	TRBH 0x103 /* TX/RX buffer reg H */

#define	TRC0 0x148 /* TX Ready control reg 0 */

#define	TRC1 0x149 /* TX Ready control reg 1 */

#define	RRC 0x14a /* RX Ready control reg */

#define	CST0 0x108 /* Current Status Register 0 */

#define	CST1 0x109 /* Current Status Register 1 */

#define	CST2 0x10a /* Current Status Register 2 */

#define	CST3 0x10b /* Current Status Register 3 */

#define	GPO 0x131 /* General Purpose Output Pin Ctl Reg */

#define	TFS 0x14b /* Tx Start Threshold Ctl Reg */

#define	TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */

#define	TBN 0x110 /* Tx Buffer Number Reg */

#define	RBN 0x111 /* Rx Buffer Number Reg */

#define	TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */

#define	TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */

#define	TCR 0x152 /* Tx DMA Critical Request Reg */

#define	RNR 0x154 /* Rx DMA Request Ctl Reg */

#define	RCR 0x156 /* Rx DMA Critical Request Reg */

#define	TIMER0RX_OFFSET 0x00

#define	TIMER0TX_OFFSET 0x10

#define	TIMER1RX_OFFSET 0x20

#define	TIMER1TX_OFFSET 0x30

#define	TCNTL 0x200 /* Timer Upcounter L */

#define	TCNTH 0x201 /* Timer Upcounter H */

#define	TCONRL 0x204 /* Timer Constant Register L */

#define	TCONRH 0x205 /* Timer Constant Register H */

#define	TCSR 0x206 /* Timer Control/Status Register */

#define	TEPR 0x207 /* Timer Expand Prescale Register */

#define	PCR 0x40 /* DMA priority control reg */

#define	DRR 0x44 /* DMA reset reg */

#define	DMER 0x07 /* DMA Master Enable reg */

#define	BTCR 0x08 /* Burst Tx Ctl Reg */

#define	BOLR 0x0c /* Back-off Length Reg */

#define	DSR_RX(chan) (0x48 + 2chan) / DMA Status Reg (Rx) */

#define	DSR_TX(chan) (0x49 + 2chan) / DMA Status Reg (Tx) */

#define	DIR_RX(chan) (0x4c + 2chan) / DMA Interrupt Enable Reg (Rx) */

#define	DIR_TX(chan) (0x4d + 2chan) / DMA Interrupt Enable Reg (Tx) */

#define	FCT_RX(chan) (0x50 + 2chan) / Frame End Interrupt Counter (Rx) */

#define	FCT_TX(chan) (0x51 + 2chan) / Frame End Interrupt Counter (Tx) */

#define	DMR_RX(chan) (0x54 + 2chan) / DMA Mode Reg (Rx) */

#define	DMR_TX(chan) (0x55 + 2chan) / DMA Mode Reg (Tx) */

#define	DCR_RX(chan) (0x58 + 2chan) / DMA Command Reg (Rx) */

#define	DCR_TX(chan) (0x59 + 2chan) / DMA Command Reg (Tx) */

#define	DMAC0RX_OFFSET 0x00

#define	DMAC0TX_OFFSET 0x20

#define	DMAC1RX_OFFSET 0x40

#define	DMAC1TX_OFFSET 0x60

#define	DARL 0x80 /* Dest Addr Register L (single-block, RX only) */

#define	DARH 0x81 /* Dest Addr Register H (single-block, RX only) */

#define	DARB 0x82 /* Dest Addr Register B (single-block, RX only) */

#define	DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */

#define	SARL 0x80 /* Source Addr Register L (single-block, TX only) */

#define	SARH 0x81 /* Source Addr Register H (single-block, TX only) */

#define	SARB 0x82 /* Source Addr Register B (single-block, TX only) */

#define	DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */

#define	BARL 0x80 /* Buffer Addr Register L (chained-block) */

#define	BARH 0x81 /* Buffer Addr Register H (chained-block) */

#define	BARB 0x82 /* Buffer Addr Register B (chained-block) */

#define	BARBH 0x83 /* Buffer Addr Register BH (chained-block) */

#define	CDAL 0x84 /* Current Descriptor Addr Register L */

#define	CDAH 0x85 /* Current Descriptor Addr Register H */

#define	CDAB 0x86 /* Current Descriptor Addr Register B */

#define	CDABH 0x87 /* Current Descriptor Addr Register BH */

#define	EDAL 0x88 /* Error Descriptor Addr Register L */

#define	EDAH 0x89 /* Error Descriptor Addr Register H */

#define	EDAB 0x8a /* Error Descriptor Addr Register B */

#define	EDABH 0x8b /* Error Descriptor Addr Register BH */

#define	BFLL 0x90 /* RX Buffer Length L (only RX) */

#define	BFLH 0x91 /* RX Buffer Length H (only RX) */

#define	BCRL 0x8c /* Byte Count Register L */

#define	BCRH 0x8d /* Byte Count Register H */

#define	DST_EOT 0x01 /* End of transmit command */

#define	DST_OSB 0x02 /* Ownership bit */

#define	DST_CRC 0x04 /* CRC Error */

#define	DST_OVR 0x08 /* Overrun */

#define	DST_UDR 0x08 /* Underrun */

#define	DST_RBIT 0x10 /* Residual bit */

#define	DST_ABT 0x20 /* Abort */

#define	DST_SHRT 0x40 /* Short Frame */

#define	DST_EOM 0x80 /* End of Message */

#define	ST_TX_EOM 0x80 /* End of frame */

#define	ST_TX_UNDRRUN 0x08

#define	ST_TX_OWNRSHP 0x02

#define	ST_TX_EOT 0x01 /* End of transmition */

#define	ST_RX_EOM 0x80 /* End of frame */

#define	ST_RX_SHORT 0x40 /* Short frame */

#define	ST_RX_ABORT 0x20 /* Abort */

#define	ST_RX_RESBIT 0x10 /* Residual bit */

#define	ST_RX_OVERRUN 0x08 /* Overrun */

#define	ST_RX_CRC 0x04 /* CRC */

#define	ST_RX_OWNRSHP 0x02

#define	ST_ERROR_MASK 0x7C

#define	CMCR 0x158 /* Counter Master Ctl Reg */

#define	TECNTL 0x160 /* Tx EOM Counter L */

#define	TECNTM 0x161 /* Tx EOM Counter M */

#define	TECNTH 0x162 /* Tx EOM Counter H */

#define	TECCR 0x163 /* Tx EOM Counter Ctl Reg */

#define	URCNTL 0x164 /* Underrun Counter L */

#define	URCNTH 0x165 /* Underrun Counter H */

#define	URCCR 0x167 /* Underrun Counter Ctl Reg */

#define	RECNTL 0x168 /* Rx EOM Counter L */

#define	RECNTM 0x169 /* Rx EOM Counter M */

#define	RECNTH 0x16a /* Rx EOM Counter H */

#define	RECCR 0x16b /* Rx EOM Counter Ctl Reg */

#define	ORCNTL 0x16c /* Overrun Counter L */

#define	ORCNTH 0x16d /* Overrun Counter H */

#define	ORCCR 0x16f /* Overrun Counter Ctl Reg */

#define	CECNTL 0x170 /* CRC Counter L */

#define	CECNTH 0x171 /* CRC Counter H */

#define	CECCR 0x173 /* CRC Counter Ctl Reg */

#define	ABCNTL 0x174 /* Abort frame Counter L */

#define	ABCNTH 0x175 /* Abort frame Counter H */

#define	ABCCR 0x177 /* Abort frame Counter Ctl Reg */

#define	SHCNTL 0x178 /* Short frame Counter L */

#define	SHCNTH 0x179 /* Short frame Counter H */

#define	SHCCR 0x17b /* Short frame Counter Ctl Reg */

#define	RSCNTL 0x17c /* Residual bit Counter L */

#define	RSCNTH 0x17d /* Residual bit Counter H */

#define	RSCCR 0x17f /* Residual bit Counter Ctl Reg */

#define	IR0_DMIC 0x00000001

#define	IR0_DMIB 0x00000002

#define	IR0_DMIA 0x00000004

#define	IR0_EFT 0x00000008

#define	IR0_DMAREQ 0x00010000

#define	IR0_TXINT 0x00020000

#define	IR0_RXINTB 0x00040000

#define	IR0_RXINTA 0x00080000

#define	IR0_TXRDY 0x00100000

#define	IR0_RXRDY 0x00200000

#define	MD0_CRC16_0 0x00

#define	MD0_CRC16_1 0x01

#define	MD0_CRC32 0x02

#define	MD0_CRC_CCITT 0x03

#define	MD0_CRCC0 0x04

#define	MD0_CRCC1 0x08

#define	MD0_AUTO_ENA 0x10

#define	MD0_ASYNC 0x00

#define	MD0_BY_MSYNC 0x20

#define	MD0_BY_BISYNC 0x40

#define	MD0_BY_EXT 0x60

#define	MD0_BIT_SYNC 0x80

#define	MD0_TRANSP 0xc0

#define	MD0_HDLC 0x80 /* Bit-sync HDLC mode */

#define	MD0_CRC_NONE 0x00

#define	MD0_CRC_16_0 0x04

#define	MD0_CRC_16 0x05

#define	MD0_CRC_ITU32 0x06

#define	MD0_CRC_ITU 0x07

#define	MD1_NOADDR 0x00

#define	MD1_SADDR1 0x40

#define	MD1_SADDR2 0x80

#define	MD1_DADDR 0xc0

#define	MD2_NRZI_IEEE 0x40

#define	MD2_MANCHESTER 0x80

#define	MD2_FM_MARK 0xA0

#define	MD2_FM_SPACE 0xC0

#define	MD2_LOOPBACK 0x03 /* Local data Loopback */

#define	MD2_F_DUPLEX 0x00

#define	MD2_AUTO_ECHO 0x01

#define	MD2_LOOP_HI_Z 0x02

#define	MD2_LOOP_MIR 0x03

#define	MD2_ADPLL_X8 0x00

#define	MD2_ADPLL_X16 0x08

#define	MD2_ADPLL_X32 0x10

#define	MD2_NRZ 0x00

#define	MD2_NRZI 0x20

#define	MD2_NRZ_IEEE 0x40

#define	MD2_MANCH 0x00

#define	MD2_FM1 0x20

#define	MD2_FM0 0x40

#define	MD2_FM 0x80

#define	CTL_RTS 0x01

#define	CTL_DTR 0x02

#define	CTL_SYN 0x04

#define	CTL_IDLC 0x10

#define	CTL_UDRNC 0x20

#define	CTL_URSKP 0x40

#define	CTL_URCT 0x80

#define	CTL_NORTS 0x01

#define	CTL_NODTR 0x02

#define	CTL_IDLE 0x10

#define	RXS_BR0 0x01

#define	RXS_BR1 0x02

#define	RXS_BR2 0x04

#define	RXS_BR3 0x08

#define	RXS_ECLK 0x00

#define	RXS_ECLK_NS 0x20

#define	RXS_IBRG 0x40

#define	RXS_PLL1 0x50

#define	RXS_PLL2 0x60

#define	RXS_PLL3 0x70

#define	RXS_DRTXC 0x80

#define	TXS_BR0 0x01

#define	TXS_BR1 0x02

#define	TXS_BR2 0x04

#define	TXS_BR3 0x08

#define	TXS_ECLK 0x00

#define	TXS_IBRG 0x40

#define	TXS_RCLK 0x60

#define	TXS_DTRXC 0x80

#define	EXS_RES0 0x01

#define	EXS_RES1 0x02

#define	EXS_RES2 0x04

#define	EXS_TES0 0x10

#define	EXS_TES1 0x20

#define	EXS_TES2 0x40

#define	CLK_BRG_MASK 0x0F

#define	CLK_PIN_OUT 0x80

#define	CLK_LINE 0x00 /* clock line input */

#define	CLK_BRG 0x40 /* internal baud rate generator */

#define	CLK_TX_RXCLK 0x60 /* TX clock from RX clock */

#define	CMD_RX_RST 0x11

#define	CMD_RX_ENA 0x12

#define	CMD_RX_DIS 0x13

#define	CMD_RX_CRC_INIT 0x14

#define	CMD_RX_MSG_REJ 0x15

#define	CMD_RX_MP_SRCH 0x16

#define	CMD_RX_CRC_EXC 0x17

#define	CMD_RX_CRC_FRC 0x18

#define	CMD_TX_RST 0x01

#define	CMD_TX_ENA 0x02

#define	CMD_TX_DISA 0x03

#define	CMD_TX_CRC_INIT 0x04

#define	CMD_TX_CRC_EXC 0x05

#define	CMD_TX_EOM 0x06

#define	CMD_TX_ABORT 0x07

#define	CMD_TX_MP_ON 0x08

#define	CMD_TX_BUF_CLR 0x09

#define	CMD_TX_DISB 0x0b

#define	CMD_CH_RST 0x21

#define	CMD_SRCH_MODE 0x31

#define	CMD_NOP 0x00

#define	CMD_RESET 0x21

#define	CMD_TX_ENABLE 0x02

#define	CMD_RX_ENABLE 0x12

#define	ST0_RXRDY 0x01

#define	ST0_TXRDY 0x02

#define	ST0_RXINTB 0x20

#define	ST0_RXINTA 0x40

#define	ST0_TXINT 0x80

#define	ST1_IDLE 0x01

#define	ST1_ABORT 0x02

#define	ST1_CDCD 0x04

#define	ST1_CCTS 0x08

#define	ST1_SYN_FLAG 0x10

#define	ST1_CLMD 0x20

#define	ST1_TXIDLE 0x40

#define	ST1_UDRN 0x80

#define	ST2_CRCE 0x04

#define	ST2_ONRN 0x08

#define	ST2_RBIT 0x10

#define	ST2_ABORT 0x20

#define	ST2_SHORT 0x40

#define	ST2_EOM 0x80

#define	ST3_RX_ENA 0x01

#define	ST3_TX_ENA 0x02

#define	ST3_DCD 0x04

#define	ST3_CTS 0x08

#define	ST3_SRCH_MODE 0x10

#define	ST3_SLOOP 0x20

#define	ST3_GPI 0x80

#define	ST4_RDNR 0x01

#define	ST4_RDCR 0x02

#define	ST4_TDNR 0x04

#define	ST4_TDCR 0x08

#define	ST4_OCLM 0x20

#define	ST4_CFT 0x40

#define	ST4_CGPI 0x80

#define	FST_CRCEF 0x04

#define	FST_OVRNF 0x08

#define	FST_RBIF 0x10

#define	FST_ABTF 0x20

#define	FST_SHRTF 0x40

#define	FST_EOMF 0x80

#define	IE0_RXRDY 0x01

#define	IE0_TXRDY 0x02

#define	IE0_RXINTB 0x20

#define	IE0_RXINTA 0x40

#define	IE0_TXINT 0x80

#define	IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */

#define	IE0_CDCD 0x00000400 /* CD level change interrupt enable */

#define	IE1_IDLD 0x01

#define	IE1_ABTD 0x02

#define	IE1_CDCD 0x04

#define	IE1_CCTS 0x08

#define	IE1_SYNCD 0x10

#define	IE1_CLMD 0x20

#define	IE1_IDL 0x40

#define	IE1_UDRN 0x80

#define	IE2_CRCE 0x04

#define	IE2_OVRN 0x08

#define	IE2_RBIT 0x10

#define	IE2_ABT 0x20

#define	IE2_SHRT 0x40

#define	IE2_EOM 0x80

#define	IE4_RDNR 0x01

#define	IE4_RDCR 0x02

#define	IE4_TDNR 0x04

#define	IE4_TDCR 0x08

#define	IE4_OCLM 0x20

#define	IE4_CFT 0x40

#define	IE4_CGPI 0x80

#define	FIE_CRCEF 0x04

#define	FIE_OVRNF 0x08

#define	FIE_RBIF 0x10

#define	FIE_ABTF 0x20

#define	FIE_SHRTF 0x40

#define	FIE_EOMF 0x80

#define	DSR_DWE 0x01

#define	DSR_DE 0x02

#define	DSR_REF 0x04

#define	DSR_UDRF 0x04

#define	DSR_COA 0x08

#define	DSR_COF 0x10

#define	DSR_BOF 0x20

#define	DSR_EOM 0x40

#define	DSR_EOT 0x80

#define	DIR_REF 0x04

#define	DIR_UDRF 0x04

#define	DIR_COA 0x08

#define	DIR_COF 0x10

#define	DIR_BOF 0x20

#define	DIR_EOM 0x40

#define	DIR_EOT 0x80

#define	DIR_REFE 0x04

#define	DIR_UDRFE 0x04

#define	DIR_COAE 0x08

#define	DIR_COFE 0x10

#define	DIR_BOFE 0x20

#define	DIR_EOME 0x40

#define	DIR_EOTE 0x80

#define	DMR_CNTE 0x02

#define	DMR_NF 0x04

#define	DMR_SEOME 0x08

#define	DMR_TMOD 0x10

#define	DMER_DME 0x80 /* DMA Master Enable */

#define	DCR_SW_ABT 0x01

#define	DCR_FCT_CLR 0x02

#define	DCR_ABORT 0x01

#define	DCR_CLEAR_EOF 0x02

#define	PCR_COTE 0x80

#define	PCR_PR0 0x01

#define	PCR_PR1 0x02

#define	PCR_PR2 0x04

#define	PCR_CCC 0x08

#define	PCR_BRC 0x10

#define	PCR_OSB 0x40

#define	PCR_BURST 0x80

Macro Definition Documentation

#define ABCCR 0x177 /* Abort frame Counter Ctl Reg */

Definition at line 254 of file hd64572.h.

#define ABCNTH 0x175 /* Abort frame Counter H */

Definition at line 253 of file hd64572.h.

#define ABCNTL 0x174 /* Abort frame Counter L */

Definition at line 252 of file hd64572.h.

#define BARB 0x82 /* Buffer Addr Register B (chained-block) */

Definition at line 158 of file hd64572.h.

#define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */

Definition at line 159 of file hd64572.h.

#define BARH 0x81 /* Buffer Addr Register H (chained-block) */

Definition at line 157 of file hd64572.h.

#define BARL 0x80 /* Buffer Addr Register L (chained-block) */

Definition at line 156 of file hd64572.h.

#define BCRH 0x8d /* Byte Count Register H */

Definition at line 171 of file hd64572.h.

#define BCRL 0x8c /* Byte Count Register L */

Definition at line 170 of file hd64572.h.

#define BFLH 0x91 /* RX Buffer Length H (only RX) */

Definition at line 169 of file hd64572.h.

#define BFLL 0x90 /* RX Buffer Length L (only RX) */

Definition at line 168 of file hd64572.h.

#define BOLR 0x0c /* Back-off Length Reg */

Definition at line 130 of file hd64572.h.

#define BTCR 0x08 /* Burst Tx Ctl Reg */

Definition at line 129 of file hd64572.h.

#define CDAB 0x86 /* Current Descriptor Addr Register B */

Definition at line 162 of file hd64572.h.

#define CDABH 0x87 /* Current Descriptor Addr Register BH */

Definition at line 163 of file hd64572.h.

#define CDAH 0x85 /* Current Descriptor Addr Register H */

Definition at line 161 of file hd64572.h.

#define CDAL 0x84 /* Current Descriptor Addr Register L */

Definition at line 160 of file hd64572.h.

#define CECCR 0x173 /* CRC Counter Ctl Reg */

Definition at line 251 of file hd64572.h.

#define CECNTH 0x171 /* CRC Counter H */

Definition at line 250 of file hd64572.h.

#define CECNTL 0x170 /* CRC Counter L */

Definition at line 249 of file hd64572.h.

#define CLK_BRG 0x40 /* internal baud rate generator */

Definition at line 366 of file hd64572.h.

#define CLK_BRG_MASK 0x0F

Definition at line 363 of file hd64572.h.

#define CLK_LINE 0x00 /* clock line input */

Definition at line 365 of file hd64572.h.

#define CLK_PIN_OUT 0x80

Definition at line 364 of file hd64572.h.

#define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */

Definition at line 367 of file hd64572.h.

#define CMCR 0x158 /* Counter Master Ctl Reg */

Definition at line 234 of file hd64572.h.

#define CMD 0x128 /* Command reg */

Definition at line 75 of file hd64572.h.

#define CMD_CH_RST 0x21

Definition at line 387 of file hd64572.h.

#define CMD_NOP 0x00

Definition at line 389 of file hd64572.h.

#define CMD_RESET 0x21

Definition at line 391 of file hd64572.h.

#define CMD_RX_CRC_EXC 0x17

Definition at line 375 of file hd64572.h.

#define CMD_RX_CRC_FRC 0x18

Definition at line 376 of file hd64572.h.

#define CMD_RX_CRC_INIT 0x14

Definition at line 372 of file hd64572.h.

#define CMD_RX_DIS 0x13

Definition at line 371 of file hd64572.h.

#define CMD_RX_ENA 0x12

Definition at line 370 of file hd64572.h.

#define CMD_RX_ENABLE 0x12

Definition at line 393 of file hd64572.h.

#define CMD_RX_MP_SRCH 0x16

Definition at line 374 of file hd64572.h.

#define CMD_RX_MSG_REJ 0x15

Definition at line 373 of file hd64572.h.

#define CMD_RX_RST 0x11

Definition at line 369 of file hd64572.h.

#define CMD_SRCH_MODE 0x31

Definition at line 388 of file hd64572.h.

#define CMD_TX_ABORT 0x07

Definition at line 383 of file hd64572.h.

#define CMD_TX_BUF_CLR 0x09

Definition at line 385 of file hd64572.h.

#define CMD_TX_CRC_EXC 0x05

Definition at line 381 of file hd64572.h.

#define CMD_TX_CRC_INIT 0x04

Definition at line 380 of file hd64572.h.

#define CMD_TX_DISA 0x03

Definition at line 379 of file hd64572.h.

#define CMD_TX_DISB 0x0b

Definition at line 386 of file hd64572.h.

#define CMD_TX_ENA 0x02

Definition at line 378 of file hd64572.h.

#define CMD_TX_ENABLE 0x02

Definition at line 392 of file hd64572.h.

#define CMD_TX_EOM 0x06

Definition at line 382 of file hd64572.h.

#define CMD_TX_MP_ON 0x08

Definition at line 384 of file hd64572.h.

#define CMD_TX_RST 0x01

Definition at line 377 of file hd64572.h.

#define CST0 0x108 /* Current Status Register 0 */

Definition at line 97 of file hd64572.h.

#define CST1 0x109 /* Current Status Register 1 */

Definition at line 98 of file hd64572.h.

#define CST2 0x10a /* Current Status Register 2 */

Definition at line 99 of file hd64572.h.

#define CST3 0x10b /* Current Status Register 3 */

Definition at line 100 of file hd64572.h.

#define CTL 0x130 /* Control reg */

Definition at line 69 of file hd64572.h.

#define CTL_DTR 0x02

Definition at line 324 of file hd64572.h.

#define CTL_IDLC 0x10

Definition at line 326 of file hd64572.h.

#define CTL_IDLE 0x10

Definition at line 333 of file hd64572.h.

#define CTL_NODTR 0x02

Definition at line 332 of file hd64572.h.

#define CTL_NORTS 0x01

Definition at line 331 of file hd64572.h.

#define CTL_RTS 0x01

Definition at line 323 of file hd64572.h.

#define CTL_SYN 0x04

Definition at line 325 of file hd64572.h.

#define CTL_UDRNC 0x20

Definition at line 327 of file hd64572.h.

#define CTL_URCT 0x80

Definition at line 329 of file hd64572.h.

#define CTL_URSKP 0x40

Definition at line 328 of file hd64572.h.

#define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */

Definition at line 150 of file hd64572.h.

#define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */

Definition at line 155 of file hd64572.h.

#define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */

Definition at line 155 of file hd64572.h.

#define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */

Definition at line 149 of file hd64572.h.

#define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */

Definition at line 148 of file hd64572.h.

#define DCR_ABORT 0x01

Definition at line 515 of file hd64572.h.

#define DCR_CLEAR_EOF 0x02

Definition at line 516 of file hd64572.h.

#define DCR_FCT_CLR 0x02

Definition at line 513 of file hd64572.h.

#define DCR_RX ( chan ) (0x58 + 2*chan) /* DMA Command Reg (Rx) */

Definition at line 139 of file hd64572.h.

#define DCR_SW_ABT 0x01

Definition at line 512 of file hd64572.h.

#define DCR_TX ( chan ) (0x59 + 2*chan) /* DMA Command Reg (Tx) */

Definition at line 140 of file hd64572.h.

#define DIR_BOF 0x20

Definition at line 493 of file hd64572.h.

#define DIR_BOFE 0x20

Definition at line 501 of file hd64572.h.

#define DIR_COA 0x08

Definition at line 491 of file hd64572.h.

#define DIR_COAE 0x08

Definition at line 499 of file hd64572.h.

#define DIR_COF 0x10

Definition at line 492 of file hd64572.h.

#define DIR_COFE 0x10

Definition at line 500 of file hd64572.h.

#define DIR_EOM 0x40

Definition at line 494 of file hd64572.h.

#define DIR_EOME 0x40

Definition at line 502 of file hd64572.h.

#define DIR_EOT 0x80

Definition at line 495 of file hd64572.h.

#define DIR_EOTE 0x80

Definition at line 503 of file hd64572.h.

#define DIR_REF 0x04

Definition at line 489 of file hd64572.h.

#define DIR_REFE 0x04

Definition at line 497 of file hd64572.h.

#define DIR_RX ( chan ) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */

Definition at line 133 of file hd64572.h.

#define DIR_TX ( chan ) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */

Definition at line 134 of file hd64572.h.

#define DIR_UDRF 0x04

Definition at line 490 of file hd64572.h.

#define DIR_UDRFE 0x04

Definition at line 498 of file hd64572.h.

#define DMAC0RX_OFFSET 0x00

Definition at line 143 of file hd64572.h.

#define DMAC0TX_OFFSET 0x20

Definition at line 144 of file hd64572.h.

#define DMAC1RX_OFFSET 0x40

Definition at line 145 of file hd64572.h.

#define DMAC1TX_OFFSET 0x60

Definition at line 146 of file hd64572.h.

#define DMER 0x07 /* DMA Master Enable reg */

Definition at line 128 of file hd64572.h.

#define DMER_DME 0x80 /* DMA Master Enable */

Definition at line 510 of file hd64572.h.

#define DMR_CNTE 0x02

Definition at line 505 of file hd64572.h.

#define DMR_NF 0x04

Definition at line 506 of file hd64572.h.

#define DMR_RX ( chan ) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */

Definition at line 137 of file hd64572.h.

#define DMR_SEOME 0x08

Definition at line 507 of file hd64572.h.

#define DMR_TMOD 0x10

Definition at line 508 of file hd64572.h.

#define DMR_TX ( chan ) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */

Definition at line 138 of file hd64572.h.

#define DRR 0x44 /* DMA reset reg */

Definition at line 127 of file hd64572.h.

#define DRX_REG	(	reg,
		chan
	)	(reg + 0x40chan) / DMA Rx */

Definition at line 52 of file hd64572.h.

#define DSR_BOF 0x20

Definition at line 485 of file hd64572.h.

#define DSR_COA 0x08

Definition at line 483 of file hd64572.h.

#define DSR_COF 0x10

Definition at line 484 of file hd64572.h.

#define DSR_DE 0x02

Definition at line 480 of file hd64572.h.

#define DSR_DWE 0x01

Definition at line 479 of file hd64572.h.

#define DSR_EOM 0x40

Definition at line 486 of file hd64572.h.

#define DSR_EOT 0x80

Definition at line 487 of file hd64572.h.

#define DSR_REF 0x04

Definition at line 481 of file hd64572.h.

#define DSR_RX ( chan ) (0x48 + 2*chan) /* DMA Status Reg (Rx) */

Definition at line 131 of file hd64572.h.

#define DSR_TX ( chan ) (0x49 + 2*chan) /* DMA Status Reg (Tx) */

Definition at line 132 of file hd64572.h.

#define DSR_UDRF 0x04

Definition at line 482 of file hd64572.h.

#define DST_ABT 0x20 /* Abort */

Definition at line 212 of file hd64572.h.

#define DST_CRC 0x04 /* CRC Error */

Definition at line 208 of file hd64572.h.

#define DST_EOM 0x80 /* End of Message */

Definition at line 214 of file hd64572.h.

#define DST_EOT 0x01 /* End of transmit command */

Definition at line 206 of file hd64572.h.

#define DST_OSB 0x02 /* Ownership bit */

Definition at line 207 of file hd64572.h.

#define DST_OVR 0x08 /* Overrun */

Definition at line 209 of file hd64572.h.

#define DST_RBIT 0x10 /* Residual bit */

Definition at line 211 of file hd64572.h.

#define DST_SHRT 0x40 /* Short Frame */

Definition at line 213 of file hd64572.h.

#define DST_UDR 0x08 /* Underrun */

Definition at line 210 of file hd64572.h.

#define DTX_REG	(	reg,
		chan
	)	(reg + 0x20(2chan + 1)) /* DMA Tx */

Definition at line 53 of file hd64572.h.

#define EDAB 0x8a /* Error Descriptor Addr Register B */

Definition at line 166 of file hd64572.h.

#define EDABH 0x8b /* Error Descriptor Addr Register BH */

Definition at line 167 of file hd64572.h.

#define EDAH 0x89 /* Error Descriptor Addr Register H */

Definition at line 165 of file hd64572.h.

#define EDAL 0x88 /* Error Descriptor Addr Register L */

Definition at line 164 of file hd64572.h.

#define EXS 0x13e /* External clock input selection */

Definition at line 72 of file hd64572.h.

#define EXS_RES0 0x01

Definition at line 356 of file hd64572.h.

#define EXS_RES1 0x02

Definition at line 357 of file hd64572.h.

#define EXS_RES2 0x04

Definition at line 358 of file hd64572.h.

#define EXS_TES0 0x10

Definition at line 359 of file hd64572.h.

#define EXS_TES1 0x20

Definition at line 360 of file hd64572.h.

#define EXS_TES2 0x40

Definition at line 361 of file hd64572.h.

#define FCT_RX ( chan ) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */

Definition at line 135 of file hd64572.h.

#define FCT_TX ( chan ) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */

Definition at line 136 of file hd64572.h.

#define FIE 0x125 /* Frame Interrupt enable reg */

Definition at line 86 of file hd64572.h.

#define FIE_ABTF 0x20

Definition at line 475 of file hd64572.h.

#define FIE_CRCEF 0x04

Definition at line 472 of file hd64572.h.

#define FIE_EOMF 0x80

Definition at line 477 of file hd64572.h.

#define FIE_OVRNF 0x08

Definition at line 473 of file hd64572.h.

#define FIE_RBIF 0x10

Definition at line 474 of file hd64572.h.

#define FIE_SHRTF 0x40

Definition at line 476 of file hd64572.h.

#define FST 0x11d /* frame Status reg */

Definition at line 81 of file hd64572.h.

#define FST_ABTF 0x20

Definition at line 436 of file hd64572.h.

#define FST_CRCEF 0x04

Definition at line 433 of file hd64572.h.

#define FST_EOMF 0x80

Definition at line 438 of file hd64572.h.

#define FST_OVRNF 0x08

Definition at line 434 of file hd64572.h.

#define FST_RBIF 0x10

Definition at line 435 of file hd64572.h.

#define FST_SHRTF 0x40

Definition at line 437 of file hd64572.h.

#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */

Definition at line 101 of file hd64572.h.

#define IDL 0x142 /* Idle register */

Definition at line 89 of file hd64572.h.

#define IE0 0x120 /* Interrupt enable reg 0 */

Definition at line 82 of file hd64572.h.

#define IE0_CDCD 0x00000400 /* CD level change interrupt enable */

Definition at line 446 of file hd64572.h.

#define IE0_RXINTA 0x40

Definition at line 443 of file hd64572.h.

#define IE0_RXINTB 0x20

Definition at line 442 of file hd64572.h.

#define IE0_RXRDY 0x01

Definition at line 440 of file hd64572.h.

#define IE0_TXINT 0x80

Definition at line 444 of file hd64572.h.

#define IE0_TXRDY 0x02

Definition at line 441 of file hd64572.h.

#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */

Definition at line 445 of file hd64572.h.

#define IE1 0x121 /* Interrupt enable reg 1 */

Definition at line 83 of file hd64572.h.

#define IE1_ABTD 0x02

Definition at line 449 of file hd64572.h.

#define IE1_CCTS 0x08

Definition at line 451 of file hd64572.h.

#define IE1_CDCD 0x04

Definition at line 450 of file hd64572.h.

#define IE1_CLMD 0x20

Definition at line 453 of file hd64572.h.

#define IE1_IDL 0x40

Definition at line 454 of file hd64572.h.

#define IE1_IDLD 0x01

Definition at line 448 of file hd64572.h.

#define IE1_SYNCD 0x10

Definition at line 452 of file hd64572.h.

#define IE1_UDRN 0x80

Definition at line 455 of file hd64572.h.

#define IE2 0x122 /* Interrupt enable reg 2 */

Definition at line 84 of file hd64572.h.

#define IE2_ABT 0x20

Definition at line 460 of file hd64572.h.

#define IE2_CRCE 0x04

Definition at line 457 of file hd64572.h.

#define IE2_EOM 0x80

Definition at line 462 of file hd64572.h.

#define IE2_OVRN 0x08

Definition at line 458 of file hd64572.h.

#define IE2_RBIT 0x10

Definition at line 459 of file hd64572.h.

#define IE2_SHRT 0x40

Definition at line 461 of file hd64572.h.

#define IE4 0x124 /* Interrupt enable reg 4 */

Definition at line 85 of file hd64572.h.

#define IE4_CFT 0x40

Definition at line 469 of file hd64572.h.

#define IE4_CGPI 0x80

Definition at line 470 of file hd64572.h.

#define IE4_OCLM 0x20

Definition at line 468 of file hd64572.h.

#define IE4_RDCR 0x02

Definition at line 465 of file hd64572.h.

#define IE4_RDNR 0x01

Definition at line 464 of file hd64572.h.

#define IE4_TDCR 0x08

Definition at line 467 of file hd64572.h.

#define IE4_TDNR 0x04

Definition at line 466 of file hd64572.h.

#define IER0 0x74 /* Interrupt Enable Register 0 */

Definition at line 47 of file hd64572.h.

#define IER1 0x78 /* Interrupt Enable Register 1 */

Definition at line 48 of file hd64572.h.

#define ILAR 0x00

Definition at line 30 of file hd64572.h.

#define IMVR 0x64 /* Interrupt Modified Vector Register */

Definition at line 43 of file hd64572.h.

#define IR0_DMAREQ 0x00010000

Definition at line 268 of file hd64572.h.

#define IR0_DMIA 0x00000004

Definition at line 266 of file hd64572.h.

#define IR0_DMIB 0x00000002

Definition at line 265 of file hd64572.h.

#define IR0_DMIC 0x00000001

Definition at line 264 of file hd64572.h.

#define IR0_DRX	(	val,
		chan
	)	((val)<<(8(chan))) / Int DMA Rx */

Definition at line 57 of file hd64572.h.

#define IR0_DTX	(	val,
		chan
	)	((val)<<(4(2chan + 1))) /* Int DMA Tx */

Definition at line 58 of file hd64572.h.

#define IR0_EFT 0x00000008

Definition at line 267 of file hd64572.h.

#define IR0_M	(	val,
		chan
	)	((val)<<(8(chan))) / Int MSCI */

Definition at line 59 of file hd64572.h.

#define IR0_RXINTA 0x00080000

Definition at line 271 of file hd64572.h.

#define IR0_RXINTB 0x00040000

Definition at line 270 of file hd64572.h.

#define IR0_RXRDY 0x00200000

Definition at line 273 of file hd64572.h.

#define IR0_TXINT 0x00020000

Definition at line 269 of file hd64572.h.

#define IR0_TXRDY 0x00100000

Definition at line 272 of file hd64572.h.

#define ISR0 0x6c /* Interrupt Status Register 0 */

Definition at line 45 of file hd64572.h.

#define ISR1 0x70 /* Interrupt Status Register 1 */

Definition at line 46 of file hd64572.h.

#define ITCR 0x68 /* Interrupt Control Register */

Definition at line 44 of file hd64572.h.

#define IVR 0x60 /* Interrupt Vector Register */

Definition at line 42 of file hd64572.h.

#define M_REG	(	reg,
		chan
	)	(reg + 0x80chan) / MSCI */

Definition at line 51 of file hd64572.h.

#define MD0 0x138 /* Mode reg 0 */

Definition at line 65 of file hd64572.h.

#define MD0_ASYNC 0x00

Definition at line 282 of file hd64572.h.

#define MD0_AUTO_ENA 0x10

Definition at line 281 of file hd64572.h.

#define MD0_BIT_SYNC 0x80

Definition at line 286 of file hd64572.h.

#define MD0_BY_BISYNC 0x40

Definition at line 284 of file hd64572.h.

#define MD0_BY_EXT 0x60

Definition at line 285 of file hd64572.h.

#define MD0_BY_MSYNC 0x20

Definition at line 283 of file hd64572.h.

#define MD0_CRC16_0 0x00

Definition at line 275 of file hd64572.h.

#define MD0_CRC16_1 0x01

Definition at line 276 of file hd64572.h.

#define MD0_CRC32 0x02

Definition at line 277 of file hd64572.h.

#define MD0_CRC_16 0x05

Definition at line 293 of file hd64572.h.

#define MD0_CRC_16_0 0x04

Definition at line 292 of file hd64572.h.

#define MD0_CRC_CCITT 0x03

Definition at line 278 of file hd64572.h.

#define MD0_CRC_ITU 0x07

Definition at line 295 of file hd64572.h.

#define MD0_CRC_ITU32 0x06

Definition at line 294 of file hd64572.h.

#define MD0_CRC_NONE 0x00

Definition at line 291 of file hd64572.h.

#define MD0_CRCC0 0x04

Definition at line 279 of file hd64572.h.

#define MD0_CRCC1 0x08

Definition at line 280 of file hd64572.h.

#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */

Definition at line 289 of file hd64572.h.

#define MD0_TRANSP 0xc0

Definition at line 287 of file hd64572.h.

#define MD1 0x139 /* Mode reg 1 */

Definition at line 66 of file hd64572.h.

#define MD1_DADDR 0xc0

Definition at line 300 of file hd64572.h.

#define MD1_NOADDR 0x00

Definition at line 297 of file hd64572.h.

#define MD1_SADDR1 0x40

Definition at line 298 of file hd64572.h.

#define MD1_SADDR2 0x80

Definition at line 299 of file hd64572.h.

#define MD2 0x13a /* Mode reg 2 */

Definition at line 67 of file hd64572.h.

#define MD2_ADPLL_X16 0x08

Definition at line 313 of file hd64572.h.

#define MD2_ADPLL_X32 0x10

Definition at line 314 of file hd64572.h.

#define MD2_ADPLL_X8 0x00

Definition at line 312 of file hd64572.h.

#define MD2_AUTO_ECHO 0x01

Definition at line 309 of file hd64572.h.

#define MD2_F_DUPLEX 0x00

Definition at line 308 of file hd64572.h.

#define MD2_FM 0x80

Definition at line 321 of file hd64572.h.

#define MD2_FM0 0x40

Definition at line 320 of file hd64572.h.

#define MD2_FM1 0x20

Definition at line 319 of file hd64572.h.

#define MD2_FM_MARK 0xA0

Definition at line 304 of file hd64572.h.

#define MD2_FM_SPACE 0xC0

Definition at line 305 of file hd64572.h.

#define MD2_LOOP_HI_Z 0x02

Definition at line 310 of file hd64572.h.

#define MD2_LOOP_MIR 0x03

Definition at line 311 of file hd64572.h.

#define MD2_LOOPBACK 0x03 /* Local data Loopback */

Definition at line 306 of file hd64572.h.

#define MD2_MANCH 0x00

Definition at line 318 of file hd64572.h.

#define MD2_MANCHESTER 0x80

Definition at line 303 of file hd64572.h.

#define MD2_NRZ 0x00

Definition at line 315 of file hd64572.h.

#define MD2_NRZ_IEEE 0x40

Definition at line 317 of file hd64572.h.

#define MD2_NRZI 0x20

Definition at line 316 of file hd64572.h.

#define MD2_NRZI_IEEE 0x40

Definition at line 302 of file hd64572.h.

#define MD3 0x13b /* Mode reg 3 */

Definition at line 68 of file hd64572.h.

#define MSCI0_OFFSET 0x00

Definition at line 62 of file hd64572.h.

#define MSCI1_OFFSET 0x80

Definition at line 63 of file hd64572.h.

#define ORCCR 0x16f /* Overrun Counter Ctl Reg */

Definition at line 248 of file hd64572.h.

#define ORCNTH 0x16d /* Overrun Counter H */

Definition at line 247 of file hd64572.h.

#define ORCNTL 0x16c /* Overrun Counter L */

Definition at line 246 of file hd64572.h.

#define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */

Definition at line 34 of file hd64572.h.

#define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */

Definition at line 33 of file hd64572.h.

#define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */

Definition at line 36 of file hd64572.h.

#define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */

Definition at line 35 of file hd64572.h.

#define PCR 0x40 /* DMA priority control reg */

Definition at line 126 of file hd64572.h.

#define PCR_BRC 0x10

Definition at line 523 of file hd64572.h.

#define PCR_BURST 0x80

Definition at line 525 of file hd64572.h.

#define PCR_CCC 0x08

Definition at line 522 of file hd64572.h.

#define PCR_COTE 0x80

Definition at line 518 of file hd64572.h.

#define PCR_OSB 0x40

Definition at line 524 of file hd64572.h.

#define PCR_PR0 0x01

Definition at line 519 of file hd64572.h.

#define PCR_PR1 0x02

Definition at line 520 of file hd64572.h.

#define PCR_PR2 0x04

Definition at line 521 of file hd64572.h.

#define RBN 0x111 /* Rx Buffer Number Reg */

Definition at line 105 of file hd64572.h.

#define RCR 0x156 /* Rx DMA Critical Request Reg */

Definition at line 110 of file hd64572.h.

#define RECCR 0x16b /* Rx EOM Counter Ctl Reg */

Definition at line 245 of file hd64572.h.

#define RECNTH 0x16a /* Rx EOM Counter H */

Definition at line 244 of file hd64572.h.

#define RECNTL 0x168 /* Rx EOM Counter L */

Definition at line 242 of file hd64572.h.

#define RECNTM 0x169 /* Rx EOM Counter M */

Definition at line 243 of file hd64572.h.

#define RNR 0x154 /* Rx DMA Request Ctl Reg */

Definition at line 109 of file hd64572.h.

#define RRC 0x14a /* RX Ready control reg */

Definition at line 96 of file hd64572.h.

#define RSCCR 0x17f /* Residual bit Counter Ctl Reg */

Definition at line 260 of file hd64572.h.

#define RSCNTH 0x17d /* Residual bit Counter H */

Definition at line 259 of file hd64572.h.

#define RSCNTL 0x17c /* Residual bit Counter L */

Definition at line 258 of file hd64572.h.

#define RXS 0x13c /* RX clock source */

Definition at line 70 of file hd64572.h.

#define RXS_BR0 0x01

Definition at line 335 of file hd64572.h.

#define RXS_BR1 0x02

Definition at line 336 of file hd64572.h.

#define RXS_BR2 0x04

Definition at line 337 of file hd64572.h.

#define RXS_BR3 0x08

Definition at line 338 of file hd64572.h.

#define RXS_DRTXC 0x80

Definition at line 345 of file hd64572.h.

#define RXS_ECLK 0x00

Definition at line 339 of file hd64572.h.

#define RXS_ECLK_NS 0x20

Definition at line 340 of file hd64572.h.

#define RXS_IBRG 0x40

Definition at line 341 of file hd64572.h.

#define RXS_PLL1 0x50

Definition at line 342 of file hd64572.h.

#define RXS_PLL2 0x60

Definition at line 343 of file hd64572.h.

#define RXS_PLL3 0x70

Definition at line 344 of file hd64572.h.

#define SA0 0x140 /* Syn Address reg 0 */

Definition at line 87 of file hd64572.h.

#define SA1 0x141 /* Syn Address reg 1 */

Definition at line 88 of file hd64572.h.

#define SARB 0x82 /* Source Addr Register B (single-block, TX only) */

Definition at line 154 of file hd64572.h.

#define SARH 0x81 /* Source Addr Register H (single-block, TX only) */

Definition at line 153 of file hd64572.h.

#define SARL 0x80 /* Source Addr Register L (single-block, TX only) */

Definition at line 152 of file hd64572.h.

#define SHCCR 0x17b /* Short frame Counter Ctl Reg */

Definition at line 257 of file hd64572.h.

#define SHCNTH 0x179 /* Short frame Counter H */

Definition at line 256 of file hd64572.h.

#define SHCNTL 0x178 /* Short frame Counter L */

Definition at line 255 of file hd64572.h.

#define ST0 0x118 /* Status reg 0 */

Definition at line 76 of file hd64572.h.

#define ST0_RXINTA 0x40

Definition at line 398 of file hd64572.h.

#define ST0_RXINTB 0x20

Definition at line 397 of file hd64572.h.

#define ST0_RXRDY 0x01

Definition at line 395 of file hd64572.h.

#define ST0_TXINT 0x80

Definition at line 399 of file hd64572.h.

#define ST0_TXRDY 0x02

Definition at line 396 of file hd64572.h.

#define ST1 0x119 /* Status reg 1 */

Definition at line 77 of file hd64572.h.

#define ST1_ABORT 0x02

Definition at line 402 of file hd64572.h.

#define ST1_CCTS 0x08

Definition at line 404 of file hd64572.h.

#define ST1_CDCD 0x04

Definition at line 403 of file hd64572.h.

#define ST1_CLMD 0x20

Definition at line 406 of file hd64572.h.

#define ST1_IDLE 0x01

Definition at line 401 of file hd64572.h.

#define ST1_SYN_FLAG 0x10

Definition at line 405 of file hd64572.h.

#define ST1_TXIDLE 0x40

Definition at line 407 of file hd64572.h.

#define ST1_UDRN 0x80

Definition at line 408 of file hd64572.h.

#define ST2 0x11a /* Status reg 2 */

Definition at line 78 of file hd64572.h.

#define ST2_ABORT 0x20

Definition at line 413 of file hd64572.h.

#define ST2_CRCE 0x04

Definition at line 410 of file hd64572.h.

#define ST2_EOM 0x80

Definition at line 415 of file hd64572.h.

#define ST2_ONRN 0x08

Definition at line 411 of file hd64572.h.

#define ST2_RBIT 0x10

Definition at line 412 of file hd64572.h.

#define ST2_SHORT 0x40

Definition at line 414 of file hd64572.h.

#define ST3 0x11b /* Status reg 3 */

Definition at line 79 of file hd64572.h.

#define ST3_CTS 0x08

Definition at line 420 of file hd64572.h.

#define ST3_DCD 0x04

Definition at line 419 of file hd64572.h.

#define ST3_GPI 0x80

Definition at line 423 of file hd64572.h.

#define ST3_RX_ENA 0x01

Definition at line 417 of file hd64572.h.

#define ST3_SLOOP 0x20

Definition at line 422 of file hd64572.h.

#define ST3_SRCH_MODE 0x10

Definition at line 421 of file hd64572.h.

#define ST3_TX_ENA 0x02

Definition at line 418 of file hd64572.h.

#define ST4 0x11c /* Status reg 4 */

Definition at line 80 of file hd64572.h.

#define ST4_CFT 0x40

Definition at line 430 of file hd64572.h.

#define ST4_CGPI 0x80

Definition at line 431 of file hd64572.h.

#define ST4_OCLM 0x20

Definition at line 429 of file hd64572.h.

#define ST4_RDCR 0x02

Definition at line 426 of file hd64572.h.

#define ST4_RDNR 0x01

Definition at line 425 of file hd64572.h.

#define ST4_TDCR 0x08

Definition at line 428 of file hd64572.h.

#define ST4_TDNR 0x04

Definition at line 427 of file hd64572.h.

#define ST_ERROR_MASK 0x7C

Definition at line 231 of file hd64572.h.

#define ST_REG	(	reg,
		chan
	)	(reg + 0x80chan) / Status Cnt */

Definition at line 56 of file hd64572.h.

#define ST_RX_ABORT 0x20 /* Abort */

Definition at line 225 of file hd64572.h.

#define ST_RX_CRC 0x04 /* CRC */

Definition at line 228 of file hd64572.h.

#define ST_RX_EOM 0x80 /* End of frame */

Definition at line 223 of file hd64572.h.

#define ST_RX_OVERRUN 0x08 /* Overrun */

Definition at line 227 of file hd64572.h.

#define ST_RX_OWNRSHP 0x02

Definition at line 229 of file hd64572.h.

#define ST_RX_RESBIT 0x10 /* Residual bit */

Definition at line 226 of file hd64572.h.

#define ST_RX_SHORT 0x40 /* Short frame */

Definition at line 224 of file hd64572.h.

#define ST_TX_EOM 0x80 /* End of frame */

Definition at line 218 of file hd64572.h.

#define ST_TX_EOT 0x01 /* End of transmition */

Definition at line 221 of file hd64572.h.

#define ST_TX_OWNRSHP 0x02

Definition at line 220 of file hd64572.h.

#define ST_TX_UNDRRUN 0x08

Definition at line 219 of file hd64572.h.

#define TBN 0x110 /* Tx Buffer Number Reg */

Definition at line 104 of file hd64572.h.

#define TCNTH 0x201 /* Timer Upcounter H */

Definition at line 119 of file hd64572.h.

#define TCNTL 0x200 /* Timer Upcounter L */

Definition at line 118 of file hd64572.h.

#define TCONRH 0x205 /* Timer Constant Register H */

Definition at line 121 of file hd64572.h.

#define TCONRL 0x204 /* Timer Constant Register L */

Definition at line 120 of file hd64572.h.

#define TCR 0x152 /* Tx DMA Critical Request Reg */

Definition at line 108 of file hd64572.h.

#define TCSR 0x206 /* Timer Control/Status Register */

Definition at line 122 of file hd64572.h.

#define TECCR 0x163 /* Tx EOM Counter Ctl Reg */

Definition at line 238 of file hd64572.h.

#define TECNTH 0x162 /* Tx EOM Counter H */

Definition at line 237 of file hd64572.h.

#define TECNTL 0x160 /* Tx EOM Counter L */

Definition at line 235 of file hd64572.h.

#define TECNTM 0x161 /* Tx EOM Counter M */

Definition at line 236 of file hd64572.h.

#define TEPR 0x207 /* Timer Expand Prescale Register */

Definition at line 123 of file hd64572.h.

#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */

Definition at line 103 of file hd64572.h.

#define TFS 0x14b /* Tx Start Threshold Ctl Reg */

Definition at line 102 of file hd64572.h.

#define TIMER0RX_OFFSET 0x00

Definition at line 113 of file hd64572.h.

#define TIMER0TX_OFFSET 0x10

Definition at line 114 of file hd64572.h.

#define TIMER1RX_OFFSET 0x20

Definition at line 115 of file hd64572.h.

#define TIMER1TX_OFFSET 0x30

Definition at line 116 of file hd64572.h.

#define TMCR 0x145 /* Time constant (Rx) */

Definition at line 74 of file hd64572.h.

#define TMCT 0x144 /* Time constant (Tx) */

Definition at line 73 of file hd64572.h.

#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */

Definition at line 106 of file hd64572.h.

#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */

Definition at line 107 of file hd64572.h.

#define TRBH 0x103 /* TX/RX buffer reg H */

Definition at line 93 of file hd64572.h.

#define TRBJ 0x102 /* TX/RX buffer reg J */

Definition at line 92 of file hd64572.h.

#define TRBK 0x101 /* TX/RX buffer reg K */

Definition at line 91 of file hd64572.h.

#define TRBL 0x100 /* TX/RX buffer reg L */

Definition at line 90 of file hd64572.h.

#define TRC0 0x148 /* TX Ready control reg 0 */

Definition at line 94 of file hd64572.h.

#define TRC1 0x149 /* TX Ready control reg 1 */

Definition at line 95 of file hd64572.h.

#define TRX_REG	(	reg,
		chan
	)	(reg + 0x20chan) / Timer Rx */

Definition at line 54 of file hd64572.h.

#define TTX_REG	(	reg,
		chan
	)	(reg + 0x10(2chan + 1)) /* Timer Tx */

Definition at line 55 of file hd64572.h.

#define TXS 0x13d /* TX clock source */

Definition at line 71 of file hd64572.h.

#define TXS_BR0 0x01

Definition at line 347 of file hd64572.h.

#define TXS_BR1 0x02

Definition at line 348 of file hd64572.h.

#define TXS_BR2 0x04

Definition at line 349 of file hd64572.h.

#define TXS_BR3 0x08

Definition at line 350 of file hd64572.h.

#define TXS_DTRXC 0x80

Definition at line 354 of file hd64572.h.

#define TXS_ECLK 0x00

Definition at line 351 of file hd64572.h.

#define TXS_IBRG 0x40

Definition at line 352 of file hd64572.h.

#define TXS_RCLK 0x60

Definition at line 353 of file hd64572.h.

#define URCCR 0x167 /* Underrun Counter Ctl Reg */

Definition at line 241 of file hd64572.h.

#define URCNTH 0x165 /* Underrun Counter H */

Definition at line 240 of file hd64572.h.

#define URCNTL 0x164 /* Underrun Counter L */

Definition at line 239 of file hd64572.h.

#define WCRH 0x26 /* Wait Control Register H */

Definition at line 39 of file hd64572.h.

#define WCRL 0x24 /* Wait Control Register L */

Definition at line 37 of file hd64572.h.

#define WCRM 0x25 /* Wait Control Register M */

Definition at line 38 of file hd64572.h.

Data Structures

Macros

Macro Definition Documentation