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hfc_multi.h
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1 /*
2  * see notice in hfc_multi.c
3  */
4 
5 #define DEBUG_HFCMULTI_FIFO 0x00010000
6 #define DEBUG_HFCMULTI_CRC 0x00020000
7 #define DEBUG_HFCMULTI_INIT 0x00040000
8 #define DEBUG_HFCMULTI_PLXSD 0x00080000
9 #define DEBUG_HFCMULTI_MODE 0x00100000
10 #define DEBUG_HFCMULTI_MSG 0x00200000
11 #define DEBUG_HFCMULTI_STATE 0x00400000
12 #define DEBUG_HFCMULTI_FILL 0x00800000
13 #define DEBUG_HFCMULTI_SYNC 0x01000000
14 #define DEBUG_HFCMULTI_DTMF 0x02000000
15 #define DEBUG_HFCMULTI_LOCK 0x80000000
16 
17 #define PCI_ENA_REGIO 0x01
18 #define PCI_ENA_MEMIO 0x02
19 
20 #define XHFC_IRQ 4 /* SIU_IRQ2 */
21 #define XHFC_MEMBASE 0xFE000000
22 #define XHFC_MEMSIZE 0x00001000
23 #define XHFC_OFFSET 0x00001000
24 #define PA_XHFC_A0 0x0020 /* PA10 */
25 #define PB_XHFC_IRQ1 0x00000100 /* PB23 */
26 #define PB_XHFC_IRQ2 0x00000200 /* PB22 */
27 #define PB_XHFC_IRQ3 0x00000400 /* PB21 */
28 #define PB_XHFC_IRQ4 0x00000800 /* PB20 */
29 
30 /*
31  * NOTE: some registers are assigned multiple times due to different modes
32  * also registers are assigned differen for HFC-4s/8s and HFC-E1
33  */
34 
35 /*
36  #define MAX_FRAME_SIZE 2048
37 */
38 
39 struct hfc_chan {
40  struct dchannel *dch; /* link if channel is a D-channel */
41  struct bchannel *bch; /* link if channel is a B-channel */
42  int port; /* the interface port this */
43  /* channel is associated with */
44  int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */
45  int los, ais, slip_tx, slip_rx, rdi; /* current alarms */
46  int jitter;
47  u_long cfg; /* port configuration */
48  int sync; /* sync state (used by E1) */
49  u_int protocol; /* current protocol */
50  int slot_tx; /* current pcm slot */
51  int bank_tx; /* current pcm bank */
52  int slot_rx;
53  int bank_rx;
54  int conf; /* conference setting of TX slot */
55  int txpending; /* if there is currently data in */
56  /* the FIFO 0=no, 1=yes, 2=splloop */
57  int Zfill; /* rx-fifo level on last hfcmulti_tx */
58  int rx_off; /* set to turn fifo receive off */
59  int coeff_count; /* curren coeff block */
60  s32 *coeff; /* memory pointer to 8 coeff blocks */
61 };
62 
63 
64 struct hfcm_hw {
65  u_char r_ctrl;
66  u_char r_irq_ctrl;
67  u_char r_cirm;
68  u_char r_ram_sz;
69  u_char r_pcm_md0;
70  u_char r_irqmsk_misc;
71  u_char r_dtmf;
72  u_char r_st_sync;
73  u_char r_sci_msk;
74  u_char r_tx0, r_tx1;
75  u_char a_st_ctrl0[8];
76  u_char r_bert_wd_md;
77  timer_t timer;
78 };
79 
80 
81 /* for each stack these flags are used (cfg) */
82 #define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */
83 #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */
84 #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */
85 #define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */
86 #define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */
87 #define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */
88 #define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */
89 #define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */
90 #define HFC_CFG_DTMF 9 /* enable DTMF-detection */
91 #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */
92 /* use double frame instead. */
93 
94 #define HFC_TYPE_E1 1 /* controller is HFC-E1 */
95 #define HFC_TYPE_4S 4 /* controller is HFC-4S */
96 #define HFC_TYPE_8S 8 /* controller is HFC-8S */
97 #define HFC_TYPE_XHFC 5 /* controller is XHFC */
98 
99 #define HFC_CHIP_EXRAM_128 0 /* external ram 128k */
100 #define HFC_CHIP_EXRAM_512 1 /* external ram 256k */
101 #define HFC_CHIP_REVISION0 2 /* old fifo handling */
102 #define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */
103 #define HFC_CHIP_PCM_MASTER 4 /* PCM is master */
104 #define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */
105 #define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */
106 #define HFC_CHIP_CONF 7 /* conference handling is enabled */
107 #define HFC_CHIP_ULAW 8 /* ULAW mode */
108 #define HFC_CHIP_CLOCK2 9 /* double clock mode */
109 #define HFC_CHIP_E1CLOCK_GET 10 /* always get clock from E1 interface */
110 #define HFC_CHIP_E1CLOCK_PUT 11 /* always put clock from E1 interface */
111 #define HFC_CHIP_WATCHDOG 12 /* whether we should send signals */
112 /* to the watchdog */
113 #define HFC_CHIP_B410P 13 /* whether we have a b410p with echocan in */
114 /* hw */
115 #define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */
116 #define HFC_CHIP_EMBSD 15 /* whether we have a SD Embedded board */
117 
118 #define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */
119 #define HFC_IO_MODE_REGIO 0x01 /* PCI io access */
120 #define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */
121 #define HFC_IO_MODE_EMBSD 0x03 /* direct access */
122 
123 /* table entry in the PCI devices list */
124 struct hm_map {
125  char *vendor_name;
126  char *card_name;
127  int type;
128  int ports;
129  int clock2;
130  int leds;
131  int opticalsupport;
132  int dip_type;
133  int io_mode;
134  int irq;
135 };
136 
137 struct hfc_multi {
138  struct list_head list;
139  struct hm_map *mtyp;
140  int id;
141  int pcm; /* id of pcm bus */
142  int ctype; /* controller type */
143  int ports;
144 
145  u_int irq; /* irq used by card */
146  u_int irqcnt;
147  struct pci_dev *pci_dev;
148  int io_mode; /* selects mode */
149 #ifdef HFC_REGISTER_DEBUG
150  void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
151  u_char val, const char *function, int line);
152  void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
153  u_char val, const char *function, int line);
154  u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg,
155  const char *function, int line);
156  u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg,
157  const char *function, int line);
158  u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg,
159  const char *function, int line);
160  u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg,
161  const char *function, int line);
162  void (*HFC_wait)(struct hfc_multi *hc,
163  const char *function, int line);
164  void (*HFC_wait_nodebug)(struct hfc_multi *hc,
165  const char *function, int line);
166 #else
167  void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
168  u_char val);
169  void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
170  u_char val);
171  u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg);
172  u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg);
173  u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg);
174  u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg);
175  void (*HFC_wait)(struct hfc_multi *hc);
176  void (*HFC_wait_nodebug)(struct hfc_multi *hc);
177 #endif
178  void (*read_fifo)(struct hfc_multi *hc, u_char *data,
179  int len);
180  void (*write_fifo)(struct hfc_multi *hc, u_char *data,
181  int len);
182  u_long pci_origmembase, plx_origmembase;
183  void __iomem *pci_membase; /* PCI memory */
184  void __iomem *plx_membase; /* PLX memory */
185  u_long xhfc_origmembase;
186  u_char *xhfc_membase;
187  u_long *xhfc_memaddr, *xhfc_memdata;
188 #ifdef CONFIG_MISDN_HFCMULTI_8xx
189  struct immap *immap;
190 #endif
191  u_long pb_irqmsk; /* Portbit mask to check the IRQ line */
192  u_long pci_iobase; /* PCI IO */
193  struct hfcm_hw hw; /* remember data of write-only-registers */
194 
195  u_long chip; /* chip configuration */
196  int masterclk; /* port that provides master clock -1=off */
197  unsigned char silence;/* silence byte */
198  unsigned char silence_data[128];/* silence block */
199  int dtmf; /* flag that dtmf is currently in process */
200  int Flen; /* F-buffer size */
201  int Zlen; /* Z-buffer size (must be int for calculation)*/
202  int max_trans; /* maximum transparent fifo fill */
203  int Zmin; /* Z-buffer offset */
204  int DTMFbase; /* base address of DTMF coefficients */
205 
206  u_int slots; /* number of PCM slots */
207  u_int leds; /* type of leds */
208  u_long ledstate; /* save last state of leds */
209  int opticalsupport; /* has the e1 board */
210  /* an optical Interface */
211 
212  u_int bmask[32]; /* bitmask of bchannels for port */
213  u_char dnum[32]; /* array of used dchannel numbers for port */
214  u_char created[32]; /* what port is created */
215  u_int activity_tx; /* if there is data TX / RX */
216  u_int activity_rx; /* bitmask according to port number */
217  /* (will be cleared after */
218  /* showing led-states) */
219  u_int flash[8]; /* counter for flashing 8 leds on activity */
220 
221  u_long wdcount; /* every 500 ms we need to */
222  /* send the watchdog a signal */
223  u_char wdbyte; /* watchdog toggle byte */
224  int e1_state; /* keep track of last state */
225  int e1_getclock; /* if sync is retrieved from interface */
226  int syncronized; /* keep track of existing sync interface */
227  int e1_resync; /* resync jobs */
228 
229  spinlock_t lock; /* the lock */
230 
231  struct mISDNclock *iclock; /* isdn clock support */
232  int iclock_on;
233 
234  /*
235  * the channel index is counted from 0, regardless where the channel
236  * is located on the hfc-channel.
237  * the bch->channel is equvalent to the hfc-channel
238  */
239  struct hfc_chan chan[32];
240  signed char slot_owner[256]; /* owner channel of slot */
241 };
242 
243 /* PLX GPIOs */
244 #define PLX_GPIO4_DIR_BIT 13
245 #define PLX_GPIO4_BIT 14
246 #define PLX_GPIO5_DIR_BIT 16
247 #define PLX_GPIO5_BIT 17
248 #define PLX_GPIO6_DIR_BIT 19
249 #define PLX_GPIO6_BIT 20
250 #define PLX_GPIO7_DIR_BIT 22
251 #define PLX_GPIO7_BIT 23
252 #define PLX_GPIO8_DIR_BIT 25
253 #define PLX_GPIO8_BIT 26
254 
255 #define PLX_GPIO4 (1 << PLX_GPIO4_BIT)
256 #define PLX_GPIO5 (1 << PLX_GPIO5_BIT)
257 #define PLX_GPIO6 (1 << PLX_GPIO6_BIT)
258 #define PLX_GPIO7 (1 << PLX_GPIO7_BIT)
259 #define PLX_GPIO8 (1 << PLX_GPIO8_BIT)
260 
261 #define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT)
262 #define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT)
263 #define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT)
264 #define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT)
265 #define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT)
266 
267 #define PLX_TERM_ON PLX_GPIO7
268 #define PLX_SLAVE_EN_N PLX_GPIO5
269 #define PLX_MASTER_EN PLX_GPIO6
270 #define PLX_SYNC_O_EN PLX_GPIO4
271 #define PLX_DSP_RES_N PLX_GPIO8
272 /* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */
273 #define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \
274  | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N)
275 
276 /* PLX Interrupt Control/STATUS */
277 #define PLX_INTCSR_LINTI1_ENABLE 0x01
278 #define PLX_INTCSR_LINTI1_STATUS 0x04
279 #define PLX_INTCSR_LINTI2_ENABLE 0x08
280 #define PLX_INTCSR_LINTI2_STATUS 0x20
281 #define PLX_INTCSR_PCIINT_ENABLE 0x40
282 
283 /* PLX Registers */
284 #define PLX_INTCSR 0x4c
285 #define PLX_CNTRL 0x50
286 #define PLX_GPIOC 0x54
287 
288 
289 /*
290  * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1
291  */
292 
293 /* write only registers */
294 #define R_CIRM 0x00
295 #define R_CTRL 0x01
296 #define R_BRG_PCM_CFG 0x02
297 #define R_RAM_ADDR0 0x08
298 #define R_RAM_ADDR1 0x09
299 #define R_RAM_ADDR2 0x0A
300 #define R_FIRST_FIFO 0x0B
301 #define R_RAM_SZ 0x0C
302 #define R_FIFO_MD 0x0D
303 #define R_INC_RES_FIFO 0x0E
304 #define R_FSM_IDX 0x0F
305 #define R_FIFO 0x0F
306 #define R_SLOT 0x10
307 #define R_IRQMSK_MISC 0x11
308 #define R_SCI_MSK 0x12
309 #define R_IRQ_CTRL 0x13
310 #define R_PCM_MD0 0x14
311 #define R_PCM_MD1 0x15
312 #define R_PCM_MD2 0x15
313 #define R_SH0H 0x15
314 #define R_SH1H 0x15
315 #define R_SH0L 0x15
316 #define R_SH1L 0x15
317 #define R_SL_SEL0 0x15
318 #define R_SL_SEL1 0x15
319 #define R_SL_SEL2 0x15
320 #define R_SL_SEL3 0x15
321 #define R_SL_SEL4 0x15
322 #define R_SL_SEL5 0x15
323 #define R_SL_SEL6 0x15
324 #define R_SL_SEL7 0x15
325 #define R_ST_SEL 0x16
326 #define R_ST_SYNC 0x17
327 #define R_CONF_EN 0x18
328 #define R_TI_WD 0x1A
329 #define R_BERT_WD_MD 0x1B
330 #define R_DTMF 0x1C
331 #define R_DTMF_N 0x1D
332 #define R_E1_WR_STA 0x20
333 #define R_E1_RD_STA 0x20
334 #define R_LOS0 0x22
335 #define R_LOS1 0x23
336 #define R_RX0 0x24
337 #define R_RX_FR0 0x25
338 #define R_RX_FR1 0x26
339 #define R_TX0 0x28
340 #define R_TX1 0x29
341 #define R_TX_FR0 0x2C
342 
343 #define R_TX_FR1 0x2D
344 #define R_TX_FR2 0x2E
345 #define R_JATT_ATT 0x2F /* undocumented */
346 #define A_ST_RD_STATE 0x30
347 #define A_ST_WR_STATE 0x30
348 #define R_RX_OFF 0x30
349 #define A_ST_CTRL0 0x31
350 #define R_SYNC_OUT 0x31
351 #define A_ST_CTRL1 0x32
352 #define A_ST_CTRL2 0x33
353 #define A_ST_SQ_WR 0x34
354 #define R_TX_OFF 0x34
355 #define R_SYNC_CTRL 0x35
356 #define A_ST_CLK_DLY 0x37
357 #define R_PWM0 0x38
358 #define R_PWM1 0x39
359 #define A_ST_B1_TX 0x3C
360 #define A_ST_B2_TX 0x3D
361 #define A_ST_D_TX 0x3E
362 #define R_GPIO_OUT0 0x40
363 #define R_GPIO_OUT1 0x41
364 #define R_GPIO_EN0 0x42
365 #define R_GPIO_EN1 0x43
366 #define R_GPIO_SEL 0x44
367 #define R_BRG_CTRL 0x45
368 #define R_PWM_MD 0x46
369 #define R_BRG_MD 0x47
370 #define R_BRG_TIM0 0x48
371 #define R_BRG_TIM1 0x49
372 #define R_BRG_TIM2 0x4A
373 #define R_BRG_TIM3 0x4B
374 #define R_BRG_TIM_SEL01 0x4C
375 #define R_BRG_TIM_SEL23 0x4D
376 #define R_BRG_TIM_SEL45 0x4E
377 #define R_BRG_TIM_SEL67 0x4F
378 #define A_SL_CFG 0xD0
379 #define A_CONF 0xD1
380 #define A_CH_MSK 0xF4
381 #define A_CON_HDLC 0xFA
382 #define A_SUBCH_CFG 0xFB
383 #define A_CHANNEL 0xFC
384 #define A_FIFO_SEQ 0xFD
385 #define A_IRQ_MSK 0xFF
386 
387 /* read only registers */
388 #define A_Z12 0x04
389 #define A_Z1L 0x04
390 #define A_Z1 0x04
391 #define A_Z1H 0x05
392 #define A_Z2L 0x06
393 #define A_Z2 0x06
394 #define A_Z2H 0x07
395 #define A_F1 0x0C
396 #define A_F12 0x0C
397 #define A_F2 0x0D
398 #define R_IRQ_OVIEW 0x10
399 #define R_IRQ_MISC 0x11
400 #define R_IRQ_STATECH 0x12
401 #define R_CONF_OFLOW 0x14
402 #define R_RAM_USE 0x15
403 #define R_CHIP_ID 0x16
404 #define R_BERT_STA 0x17
405 #define R_F0_CNTL 0x18
406 #define R_F0_CNTH 0x19
407 #define R_BERT_EC 0x1A
408 #define R_BERT_ECL 0x1A
409 #define R_BERT_ECH 0x1B
410 #define R_STATUS 0x1C
411 #define R_CHIP_RV 0x1F
412 #define R_STATE 0x20
413 #define R_SYNC_STA 0x24
414 #define R_RX_SL0_0 0x25
415 #define R_RX_SL0_1 0x26
416 #define R_RX_SL0_2 0x27
417 #define R_JATT_DIR 0x2b /* undocumented */
418 #define R_SLIP 0x2c
419 #define A_ST_RD_STA 0x30
420 #define R_FAS_EC 0x30
421 #define R_FAS_ECL 0x30
422 #define R_FAS_ECH 0x31
423 #define R_VIO_EC 0x32
424 #define R_VIO_ECL 0x32
425 #define R_VIO_ECH 0x33
426 #define A_ST_SQ_RD 0x34
427 #define R_CRC_EC 0x34
428 #define R_CRC_ECL 0x34
429 #define R_CRC_ECH 0x35
430 #define R_E_EC 0x36
431 #define R_E_ECL 0x36
432 #define R_E_ECH 0x37
433 #define R_SA6_SA13_EC 0x38
434 #define R_SA6_SA13_ECL 0x38
435 #define R_SA6_SA13_ECH 0x39
436 #define R_SA6_SA23_EC 0x3A
437 #define R_SA6_SA23_ECL 0x3A
438 #define R_SA6_SA23_ECH 0x3B
439 #define A_ST_B1_RX 0x3C
440 #define A_ST_B2_RX 0x3D
441 #define A_ST_D_RX 0x3E
442 #define A_ST_E_RX 0x3F
443 #define R_GPIO_IN0 0x40
444 #define R_GPIO_IN1 0x41
445 #define R_GPI_IN0 0x44
446 #define R_GPI_IN1 0x45
447 #define R_GPI_IN2 0x46
448 #define R_GPI_IN3 0x47
449 #define R_INT_DATA 0x88
450 #define R_IRQ_FIFO_BL0 0xC8
451 #define R_IRQ_FIFO_BL1 0xC9
452 #define R_IRQ_FIFO_BL2 0xCA
453 #define R_IRQ_FIFO_BL3 0xCB
454 #define R_IRQ_FIFO_BL4 0xCC
455 #define R_IRQ_FIFO_BL5 0xCD
456 #define R_IRQ_FIFO_BL6 0xCE
457 #define R_IRQ_FIFO_BL7 0xCF
458 
459 /* read and write registers */
460 #define A_FIFO_DATA0 0x80
461 #define A_FIFO_DATA1 0x80
462 #define A_FIFO_DATA2 0x80
463 #define A_FIFO_DATA0_NOINC 0x84
464 #define A_FIFO_DATA1_NOINC 0x84
465 #define A_FIFO_DATA2_NOINC 0x84
466 #define R_RAM_DATA 0xC0
467 
468 
469 /*
470  * BIT SETTING FOR HFC-4S/8S AND HFC-E1
471  */
472 
473 /* chapter 2: universal bus interface */
474 /* R_CIRM */
475 #define V_IRQ_SEL 0x01
476 #define V_SRES 0x08
477 #define V_HFCRES 0x10
478 #define V_PCMRES 0x20
479 #define V_STRES 0x40
480 #define V_ETRES 0x40
481 #define V_RLD_EPR 0x80
482 /* R_CTRL */
483 #define V_FIFO_LPRIO 0x02
484 #define V_SLOW_RD 0x04
485 #define V_EXT_RAM 0x08
486 #define V_CLK_OFF 0x20
487 #define V_ST_CLK 0x40
488 /* R_RAM_ADDR0 */
489 #define V_RAM_ADDR2 0x01
490 #define V_ADDR_RES 0x40
491 #define V_ADDR_INC 0x80
492 /* R_RAM_SZ */
493 #define V_RAM_SZ 0x01
494 #define V_PWM0_16KHZ 0x10
495 #define V_PWM1_16KHZ 0x20
496 #define V_FZ_MD 0x80
497 /* R_CHIP_ID */
498 #define V_PNP_IRQ 0x01
499 #define V_CHIP_ID 0x10
500 
501 /* chapter 3: data flow */
502 /* R_FIRST_FIFO */
503 #define V_FIRST_FIRO_DIR 0x01
504 #define V_FIRST_FIFO_NUM 0x02
505 /* R_FIFO_MD */
506 #define V_FIFO_MD 0x01
507 #define V_CSM_MD 0x04
508 #define V_FSM_MD 0x08
509 #define V_FIFO_SZ 0x10
510 /* R_FIFO */
511 #define V_FIFO_DIR 0x01
512 #define V_FIFO_NUM 0x02
513 #define V_REV 0x80
514 /* R_SLOT */
515 #define V_SL_DIR 0x01
516 #define V_SL_NUM 0x02
517 /* A_SL_CFG */
518 #define V_CH_DIR 0x01
519 #define V_CH_SEL 0x02
520 #define V_ROUTING 0x40
521 /* A_CON_HDLC */
522 #define V_IFF 0x01
523 #define V_HDLC_TRP 0x02
524 #define V_TRP_IRQ 0x04
525 #define V_DATA_FLOW 0x20
526 /* A_SUBCH_CFG */
527 #define V_BIT_CNT 0x01
528 #define V_START_BIT 0x08
529 #define V_LOOP_FIFO 0x40
530 #define V_INV_DATA 0x80
531 /* A_CHANNEL */
532 #define V_CH_DIR0 0x01
533 #define V_CH_NUM0 0x02
534 /* A_FIFO_SEQ */
535 #define V_NEXT_FIFO_DIR 0x01
536 #define V_NEXT_FIFO_NUM 0x02
537 #define V_SEQ_END 0x40
538 
539 /* chapter 4: FIFO handling and HDLC controller */
540 /* R_INC_RES_FIFO */
541 #define V_INC_F 0x01
542 #define V_RES_F 0x02
543 #define V_RES_LOST 0x04
544 
545 /* chapter 5: S/T interface */
546 /* R_SCI_MSK */
547 #define V_SCI_MSK_ST0 0x01
548 #define V_SCI_MSK_ST1 0x02
549 #define V_SCI_MSK_ST2 0x04
550 #define V_SCI_MSK_ST3 0x08
551 #define V_SCI_MSK_ST4 0x10
552 #define V_SCI_MSK_ST5 0x20
553 #define V_SCI_MSK_ST6 0x40
554 #define V_SCI_MSK_ST7 0x80
555 /* R_ST_SEL */
556 #define V_ST_SEL 0x01
557 #define V_MULT_ST 0x08
558 /* R_ST_SYNC */
559 #define V_SYNC_SEL 0x01
560 #define V_AUTO_SYNC 0x08
561 /* A_ST_WR_STA */
562 #define V_ST_SET_STA 0x01
563 #define V_ST_LD_STA 0x10
564 #define V_ST_ACT 0x20
565 #define V_SET_G2_G3 0x80
566 /* A_ST_CTRL0 */
567 #define V_B1_EN 0x01
568 #define V_B2_EN 0x02
569 #define V_ST_MD 0x04
570 #define V_D_PRIO 0x08
571 #define V_SQ_EN 0x10
572 #define V_96KHZ 0x20
573 #define V_TX_LI 0x40
574 #define V_ST_STOP 0x80
575 /* A_ST_CTRL1 */
576 #define V_G2_G3_EN 0x01
577 #define V_D_HI 0x04
578 #define V_E_IGNO 0x08
579 #define V_E_LO 0x10
580 #define V_B12_SWAP 0x80
581 /* A_ST_CTRL2 */
582 #define V_B1_RX_EN 0x01
583 #define V_B2_RX_EN 0x02
584 #define V_ST_TRIS 0x40
585 /* A_ST_CLK_DLY */
586 #define V_ST_CK_DLY 0x01
587 #define V_ST_SMPL 0x10
588 /* A_ST_D_TX */
589 #define V_ST_D_TX 0x40
590 /* R_IRQ_STATECH */
591 #define V_SCI_ST0 0x01
592 #define V_SCI_ST1 0x02
593 #define V_SCI_ST2 0x04
594 #define V_SCI_ST3 0x08
595 #define V_SCI_ST4 0x10
596 #define V_SCI_ST5 0x20
597 #define V_SCI_ST6 0x40
598 #define V_SCI_ST7 0x80
599 /* A_ST_RD_STA */
600 #define V_ST_STA 0x01
601 #define V_FR_SYNC_ST 0x10
602 #define V_TI2_EXP 0x20
603 #define V_INFO0 0x40
604 #define V_G2_G3 0x80
605 /* A_ST_SQ_RD */
606 #define V_ST_SQ 0x01
607 #define V_MF_RX_RDY 0x10
608 #define V_MF_TX_RDY 0x80
609 /* A_ST_D_RX */
610 #define V_ST_D_RX 0x40
611 /* A_ST_E_RX */
612 #define V_ST_E_RX 0x40
613 
614 /* chapter 5: E1 interface */
615 /* R_E1_WR_STA */
616 /* R_E1_RD_STA */
617 #define V_E1_SET_STA 0x01
618 #define V_E1_LD_STA 0x10
619 /* R_RX0 */
620 #define V_RX_CODE 0x01
621 #define V_RX_FBAUD 0x04
622 #define V_RX_CMI 0x08
623 #define V_RX_INV_CMI 0x10
624 #define V_RX_INV_CLK 0x20
625 #define V_RX_INV_DATA 0x40
626 #define V_AIS_ITU 0x80
627 /* R_RX_FR0 */
628 #define V_NO_INSYNC 0x01
629 #define V_AUTO_RESYNC 0x02
630 #define V_AUTO_RECO 0x04
631 #define V_SWORD_COND 0x08
632 #define V_SYNC_LOSS 0x10
633 #define V_XCRC_SYNC 0x20
634 #define V_MF_RESYNC 0x40
635 #define V_RESYNC 0x80
636 /* R_RX_FR1 */
637 #define V_RX_MF 0x01
638 #define V_RX_MF_SYNC 0x02
639 #define V_RX_SL0_RAM 0x04
640 #define V_ERR_SIM 0x20
641 #define V_RES_NMF 0x40
642 /* R_TX0 */
643 #define V_TX_CODE 0x01
644 #define V_TX_FBAUD 0x04
645 #define V_TX_CMI_CODE 0x08
646 #define V_TX_INV_CMI_CODE 0x10
647 #define V_TX_INV_CLK 0x20
648 #define V_TX_INV_DATA 0x40
649 #define V_OUT_EN 0x80
650 /* R_TX1 */
651 #define V_INV_CLK 0x01
652 #define V_EXCHG_DATA_LI 0x02
653 #define V_AIS_OUT 0x04
654 #define V_ATX 0x20
655 #define V_NTRI 0x40
656 #define V_AUTO_ERR_RES 0x80
657 /* R_TX_FR0 */
658 #define V_TRP_FAS 0x01
659 #define V_TRP_NFAS 0x02
660 #define V_TRP_RAL 0x04
661 #define V_TRP_SA 0x08
662 /* R_TX_FR1 */
663 #define V_TX_FAS 0x01
664 #define V_TX_NFAS 0x02
665 #define V_TX_RAL 0x04
666 #define V_TX_SA 0x08
667 /* R_TX_FR2 */
668 #define V_TX_MF 0x01
669 #define V_TRP_SL0 0x02
670 #define V_TX_SL0_RAM 0x04
671 #define V_TX_E 0x10
672 #define V_NEG_E 0x20
673 #define V_XS12_ON 0x40
674 #define V_XS15_ON 0x80
675 /* R_RX_OFF */
676 #define V_RX_SZ 0x01
677 #define V_RX_INIT 0x04
678 /* R_SYNC_OUT */
679 #define V_SYNC_E1_RX 0x01
680 #define V_IPATS0 0x20
681 #define V_IPATS1 0x40
682 #define V_IPATS2 0x80
683 /* R_TX_OFF */
684 #define V_TX_SZ 0x01
685 #define V_TX_INIT 0x04
686 /* R_SYNC_CTRL */
687 #define V_EXT_CLK_SYNC 0x01
688 #define V_SYNC_OFFS 0x02
689 #define V_PCM_SYNC 0x04
690 #define V_NEG_CLK 0x08
691 #define V_HCLK 0x10
692 /*
693  #define V_JATT_AUTO_DEL 0x20
694  #define V_JATT_AUTO 0x40
695 */
696 #define V_JATT_OFF 0x80
697 /* R_STATE */
698 #define V_E1_STA 0x01
699 #define V_ALT_FR_RX 0x40
700 #define V_ALT_FR_TX 0x80
701 /* R_SYNC_STA */
702 #define V_RX_STA 0x01
703 #define V_FR_SYNC_E1 0x04
704 #define V_SIG_LOS 0x08
705 #define V_MFA_STA 0x10
706 #define V_AIS 0x40
707 #define V_NO_MF_SYNC 0x80
708 /* R_RX_SL0_0 */
709 #define V_SI_FAS 0x01
710 #define V_SI_NFAS 0x02
711 #define V_A 0x04
712 #define V_CRC_OK 0x08
713 #define V_TX_E1 0x10
714 #define V_TX_E2 0x20
715 #define V_RX_E1 0x40
716 #define V_RX_E2 0x80
717 /* R_SLIP */
718 #define V_SLIP_RX 0x01
719 #define V_FOSLIP_RX 0x08
720 #define V_SLIP_TX 0x10
721 #define V_FOSLIP_TX 0x80
722 
723 /* chapter 6: PCM interface */
724 /* R_PCM_MD0 */
725 #define V_PCM_MD 0x01
726 #define V_C4_POL 0x02
727 #define V_F0_NEG 0x04
728 #define V_F0_LEN 0x08
729 #define V_PCM_ADDR 0x10
730 /* R_SL_SEL0 */
731 #define V_SL_SEL0 0x01
732 #define V_SH_SEL0 0x80
733 /* R_SL_SEL1 */
734 #define V_SL_SEL1 0x01
735 #define V_SH_SEL1 0x80
736 /* R_SL_SEL2 */
737 #define V_SL_SEL2 0x01
738 #define V_SH_SEL2 0x80
739 /* R_SL_SEL3 */
740 #define V_SL_SEL3 0x01
741 #define V_SH_SEL3 0x80
742 /* R_SL_SEL4 */
743 #define V_SL_SEL4 0x01
744 #define V_SH_SEL4 0x80
745 /* R_SL_SEL5 */
746 #define V_SL_SEL5 0x01
747 #define V_SH_SEL5 0x80
748 /* R_SL_SEL6 */
749 #define V_SL_SEL6 0x01
750 #define V_SH_SEL6 0x80
751 /* R_SL_SEL7 */
752 #define V_SL_SEL7 0x01
753 #define V_SH_SEL7 0x80
754 /* R_PCM_MD1 */
755 #define V_ODEC_CON 0x01
756 #define V_PLL_ADJ 0x04
757 #define V_PCM_DR 0x10
758 #define V_PCM_LOOP 0x40
759 /* R_PCM_MD2 */
760 #define V_SYNC_PLL 0x02
761 #define V_SYNC_SRC 0x04
762 #define V_SYNC_OUT 0x08
763 #define V_ICR_FR_TIME 0x40
764 #define V_EN_PLL 0x80
765 
766 /* chapter 7: pulse width modulation */
767 /* R_PWM_MD */
768 #define V_EXT_IRQ_EN 0x08
769 #define V_PWM0_MD 0x10
770 #define V_PWM1_MD 0x40
771 
772 /* chapter 8: multiparty audio conferences */
773 /* R_CONF_EN */
774 #define V_CONF_EN 0x01
775 #define V_ULAW 0x80
776 /* A_CONF */
777 #define V_CONF_NUM 0x01
778 #define V_NOISE_SUPPR 0x08
779 #define V_ATT_LEV 0x20
780 #define V_CONF_SL 0x80
781 /* R_CONF_OFLOW */
782 #define V_CONF_OFLOW0 0x01
783 #define V_CONF_OFLOW1 0x02
784 #define V_CONF_OFLOW2 0x04
785 #define V_CONF_OFLOW3 0x08
786 #define V_CONF_OFLOW4 0x10
787 #define V_CONF_OFLOW5 0x20
788 #define V_CONF_OFLOW6 0x40
789 #define V_CONF_OFLOW7 0x80
790 
791 /* chapter 9: DTMF contoller */
792 /* R_DTMF0 */
793 #define V_DTMF_EN 0x01
794 #define V_HARM_SEL 0x02
795 #define V_DTMF_RX_CH 0x04
796 #define V_DTMF_STOP 0x08
797 #define V_CHBL_SEL 0x10
798 #define V_RST_DTMF 0x40
799 #define V_ULAW_SEL 0x80
800 
801 /* chapter 10: BERT */
802 /* R_BERT_WD_MD */
803 #define V_PAT_SEQ 0x01
804 #define V_BERT_ERR 0x08
805 #define V_AUTO_WD_RES 0x20
806 #define V_WD_RES 0x80
807 /* R_BERT_STA */
808 #define V_BERT_SYNC_SRC 0x01
809 #define V_BERT_SYNC 0x10
810 #define V_BERT_INV_DATA 0x20
811 
812 /* chapter 11: auxiliary interface */
813 /* R_BRG_PCM_CFG */
814 #define V_BRG_EN 0x01
815 #define V_BRG_MD 0x02
816 #define V_PCM_CLK 0x20
817 #define V_ADDR_WRDLY 0x40
818 /* R_BRG_CTRL */
819 #define V_BRG_CS 0x01
820 #define V_BRG_ADDR 0x08
821 #define V_BRG_CS_SRC 0x80
822 /* R_BRG_MD */
823 #define V_BRG_MD0 0x01
824 #define V_BRG_MD1 0x02
825 #define V_BRG_MD2 0x04
826 #define V_BRG_MD3 0x08
827 #define V_BRG_MD4 0x10
828 #define V_BRG_MD5 0x20
829 #define V_BRG_MD6 0x40
830 #define V_BRG_MD7 0x80
831 /* R_BRG_TIM0 */
832 #define V_BRG_TIM0_IDLE 0x01
833 #define V_BRG_TIM0_CLK 0x10
834 /* R_BRG_TIM1 */
835 #define V_BRG_TIM1_IDLE 0x01
836 #define V_BRG_TIM1_CLK 0x10
837 /* R_BRG_TIM2 */
838 #define V_BRG_TIM2_IDLE 0x01
839 #define V_BRG_TIM2_CLK 0x10
840 /* R_BRG_TIM3 */
841 #define V_BRG_TIM3_IDLE 0x01
842 #define V_BRG_TIM3_CLK 0x10
843 /* R_BRG_TIM_SEL01 */
844 #define V_BRG_WR_SEL0 0x01
845 #define V_BRG_RD_SEL0 0x04
846 #define V_BRG_WR_SEL1 0x10
847 #define V_BRG_RD_SEL1 0x40
848 /* R_BRG_TIM_SEL23 */
849 #define V_BRG_WR_SEL2 0x01
850 #define V_BRG_RD_SEL2 0x04
851 #define V_BRG_WR_SEL3 0x10
852 #define V_BRG_RD_SEL3 0x40
853 /* R_BRG_TIM_SEL45 */
854 #define V_BRG_WR_SEL4 0x01
855 #define V_BRG_RD_SEL4 0x04
856 #define V_BRG_WR_SEL5 0x10
857 #define V_BRG_RD_SEL5 0x40
858 /* R_BRG_TIM_SEL67 */
859 #define V_BRG_WR_SEL6 0x01
860 #define V_BRG_RD_SEL6 0x04
861 #define V_BRG_WR_SEL7 0x10
862 #define V_BRG_RD_SEL7 0x40
863 
864 /* chapter 12: clock, reset, interrupt, timer and watchdog */
865 /* R_IRQMSK_MISC */
866 #define V_STA_IRQMSK 0x01
867 #define V_TI_IRQMSK 0x02
868 #define V_PROC_IRQMSK 0x04
869 #define V_DTMF_IRQMSK 0x08
870 #define V_IRQ1S_MSK 0x10
871 #define V_SA6_IRQMSK 0x20
872 #define V_RX_EOMF_MSK 0x40
873 #define V_TX_EOMF_MSK 0x80
874 /* R_IRQ_CTRL */
875 #define V_FIFO_IRQ 0x01
876 #define V_GLOB_IRQ_EN 0x08
877 #define V_IRQ_POL 0x10
878 /* R_TI_WD */
879 #define V_EV_TS 0x01
880 #define V_WD_TS 0x10
881 /* A_IRQ_MSK */
882 #define V_IRQ 0x01
883 #define V_BERT_EN 0x02
884 #define V_MIX_IRQ 0x04
885 /* R_IRQ_OVIEW */
886 #define V_IRQ_FIFO_BL0 0x01
887 #define V_IRQ_FIFO_BL1 0x02
888 #define V_IRQ_FIFO_BL2 0x04
889 #define V_IRQ_FIFO_BL3 0x08
890 #define V_IRQ_FIFO_BL4 0x10
891 #define V_IRQ_FIFO_BL5 0x20
892 #define V_IRQ_FIFO_BL6 0x40
893 #define V_IRQ_FIFO_BL7 0x80
894 /* R_IRQ_MISC */
895 #define V_STA_IRQ 0x01
896 #define V_TI_IRQ 0x02
897 #define V_IRQ_PROC 0x04
898 #define V_DTMF_IRQ 0x08
899 #define V_IRQ1S 0x10
900 #define V_SA6_IRQ 0x20
901 #define V_RX_EOMF 0x40
902 #define V_TX_EOMF 0x80
903 /* R_STATUS */
904 #define V_BUSY 0x01
905 #define V_PROC 0x02
906 #define V_DTMF_STA 0x04
907 #define V_LOST_STA 0x08
908 #define V_SYNC_IN 0x10
909 #define V_EXT_IRQSTA 0x20
910 #define V_MISC_IRQSTA 0x40
911 #define V_FR_IRQSTA 0x80
912 /* R_IRQ_FIFO_BL0 */
913 #define V_IRQ_FIFO0_TX 0x01
914 #define V_IRQ_FIFO0_RX 0x02
915 #define V_IRQ_FIFO1_TX 0x04
916 #define V_IRQ_FIFO1_RX 0x08
917 #define V_IRQ_FIFO2_TX 0x10
918 #define V_IRQ_FIFO2_RX 0x20
919 #define V_IRQ_FIFO3_TX 0x40
920 #define V_IRQ_FIFO3_RX 0x80
921 /* R_IRQ_FIFO_BL1 */
922 #define V_IRQ_FIFO4_TX 0x01
923 #define V_IRQ_FIFO4_RX 0x02
924 #define V_IRQ_FIFO5_TX 0x04
925 #define V_IRQ_FIFO5_RX 0x08
926 #define V_IRQ_FIFO6_TX 0x10
927 #define V_IRQ_FIFO6_RX 0x20
928 #define V_IRQ_FIFO7_TX 0x40
929 #define V_IRQ_FIFO7_RX 0x80
930 /* R_IRQ_FIFO_BL2 */
931 #define V_IRQ_FIFO8_TX 0x01
932 #define V_IRQ_FIFO8_RX 0x02
933 #define V_IRQ_FIFO9_TX 0x04
934 #define V_IRQ_FIFO9_RX 0x08
935 #define V_IRQ_FIFO10_TX 0x10
936 #define V_IRQ_FIFO10_RX 0x20
937 #define V_IRQ_FIFO11_TX 0x40
938 #define V_IRQ_FIFO11_RX 0x80
939 /* R_IRQ_FIFO_BL3 */
940 #define V_IRQ_FIFO12_TX 0x01
941 #define V_IRQ_FIFO12_RX 0x02
942 #define V_IRQ_FIFO13_TX 0x04
943 #define V_IRQ_FIFO13_RX 0x08
944 #define V_IRQ_FIFO14_TX 0x10
945 #define V_IRQ_FIFO14_RX 0x20
946 #define V_IRQ_FIFO15_TX 0x40
947 #define V_IRQ_FIFO15_RX 0x80
948 /* R_IRQ_FIFO_BL4 */
949 #define V_IRQ_FIFO16_TX 0x01
950 #define V_IRQ_FIFO16_RX 0x02
951 #define V_IRQ_FIFO17_TX 0x04
952 #define V_IRQ_FIFO17_RX 0x08
953 #define V_IRQ_FIFO18_TX 0x10
954 #define V_IRQ_FIFO18_RX 0x20
955 #define V_IRQ_FIFO19_TX 0x40
956 #define V_IRQ_FIFO19_RX 0x80
957 /* R_IRQ_FIFO_BL5 */
958 #define V_IRQ_FIFO20_TX 0x01
959 #define V_IRQ_FIFO20_RX 0x02
960 #define V_IRQ_FIFO21_TX 0x04
961 #define V_IRQ_FIFO21_RX 0x08
962 #define V_IRQ_FIFO22_TX 0x10
963 #define V_IRQ_FIFO22_RX 0x20
964 #define V_IRQ_FIFO23_TX 0x40
965 #define V_IRQ_FIFO23_RX 0x80
966 /* R_IRQ_FIFO_BL6 */
967 #define V_IRQ_FIFO24_TX 0x01
968 #define V_IRQ_FIFO24_RX 0x02
969 #define V_IRQ_FIFO25_TX 0x04
970 #define V_IRQ_FIFO25_RX 0x08
971 #define V_IRQ_FIFO26_TX 0x10
972 #define V_IRQ_FIFO26_RX 0x20
973 #define V_IRQ_FIFO27_TX 0x40
974 #define V_IRQ_FIFO27_RX 0x80
975 /* R_IRQ_FIFO_BL7 */
976 #define V_IRQ_FIFO28_TX 0x01
977 #define V_IRQ_FIFO28_RX 0x02
978 #define V_IRQ_FIFO29_TX 0x04
979 #define V_IRQ_FIFO29_RX 0x08
980 #define V_IRQ_FIFO30_TX 0x10
981 #define V_IRQ_FIFO30_RX 0x20
982 #define V_IRQ_FIFO31_TX 0x40
983 #define V_IRQ_FIFO31_RX 0x80
984 
985 /* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */
986 /* R_GPIO_OUT0 */
987 #define V_GPIO_OUT0 0x01
988 #define V_GPIO_OUT1 0x02
989 #define V_GPIO_OUT2 0x04
990 #define V_GPIO_OUT3 0x08
991 #define V_GPIO_OUT4 0x10
992 #define V_GPIO_OUT5 0x20
993 #define V_GPIO_OUT6 0x40
994 #define V_GPIO_OUT7 0x80
995 /* R_GPIO_OUT1 */
996 #define V_GPIO_OUT8 0x01
997 #define V_GPIO_OUT9 0x02
998 #define V_GPIO_OUT10 0x04
999 #define V_GPIO_OUT11 0x08
1000 #define V_GPIO_OUT12 0x10
1001 #define V_GPIO_OUT13 0x20
1002 #define V_GPIO_OUT14 0x40
1003 #define V_GPIO_OUT15 0x80
1004 /* R_GPIO_EN0 */
1005 #define V_GPIO_EN0 0x01
1006 #define V_GPIO_EN1 0x02
1007 #define V_GPIO_EN2 0x04
1008 #define V_GPIO_EN3 0x08
1009 #define V_GPIO_EN4 0x10
1010 #define V_GPIO_EN5 0x20
1011 #define V_GPIO_EN6 0x40
1012 #define V_GPIO_EN7 0x80
1013 /* R_GPIO_EN1 */
1014 #define V_GPIO_EN8 0x01
1015 #define V_GPIO_EN9 0x02
1016 #define V_GPIO_EN10 0x04
1017 #define V_GPIO_EN11 0x08
1018 #define V_GPIO_EN12 0x10
1019 #define V_GPIO_EN13 0x20
1020 #define V_GPIO_EN14 0x40
1021 #define V_GPIO_EN15 0x80
1022 /* R_GPIO_SEL */
1023 #define V_GPIO_SEL0 0x01
1024 #define V_GPIO_SEL1 0x02
1025 #define V_GPIO_SEL2 0x04
1026 #define V_GPIO_SEL3 0x08
1027 #define V_GPIO_SEL4 0x10
1028 #define V_GPIO_SEL5 0x20
1029 #define V_GPIO_SEL6 0x40
1030 #define V_GPIO_SEL7 0x80
1031 /* R_GPIO_IN0 */
1032 #define V_GPIO_IN0 0x01
1033 #define V_GPIO_IN1 0x02
1034 #define V_GPIO_IN2 0x04
1035 #define V_GPIO_IN3 0x08
1036 #define V_GPIO_IN4 0x10
1037 #define V_GPIO_IN5 0x20
1038 #define V_GPIO_IN6 0x40
1039 #define V_GPIO_IN7 0x80
1040 /* R_GPIO_IN1 */
1041 #define V_GPIO_IN8 0x01
1042 #define V_GPIO_IN9 0x02
1043 #define V_GPIO_IN10 0x04
1044 #define V_GPIO_IN11 0x08
1045 #define V_GPIO_IN12 0x10
1046 #define V_GPIO_IN13 0x20
1047 #define V_GPIO_IN14 0x40
1048 #define V_GPIO_IN15 0x80
1049 /* R_GPI_IN0 */
1050 #define V_GPI_IN0 0x01
1051 #define V_GPI_IN1 0x02
1052 #define V_GPI_IN2 0x04
1053 #define V_GPI_IN3 0x08
1054 #define V_GPI_IN4 0x10
1055 #define V_GPI_IN5 0x20
1056 #define V_GPI_IN6 0x40
1057 #define V_GPI_IN7 0x80
1058 /* R_GPI_IN1 */
1059 #define V_GPI_IN8 0x01
1060 #define V_GPI_IN9 0x02
1061 #define V_GPI_IN10 0x04
1062 #define V_GPI_IN11 0x08
1063 #define V_GPI_IN12 0x10
1064 #define V_GPI_IN13 0x20
1065 #define V_GPI_IN14 0x40
1066 #define V_GPI_IN15 0x80
1067 /* R_GPI_IN2 */
1068 #define V_GPI_IN16 0x01
1069 #define V_GPI_IN17 0x02
1070 #define V_GPI_IN18 0x04
1071 #define V_GPI_IN19 0x08
1072 #define V_GPI_IN20 0x10
1073 #define V_GPI_IN21 0x20
1074 #define V_GPI_IN22 0x40
1075 #define V_GPI_IN23 0x80
1076 /* R_GPI_IN3 */
1077 #define V_GPI_IN24 0x01
1078 #define V_GPI_IN25 0x02
1079 #define V_GPI_IN26 0x04
1080 #define V_GPI_IN27 0x08
1081 #define V_GPI_IN28 0x10
1082 #define V_GPI_IN29 0x20
1083 #define V_GPI_IN30 0x40
1084 #define V_GPI_IN31 0x80
1085 
1086 /* map of all registers, used for debugging */
1087 
1088 #ifdef HFC_REGISTER_DEBUG
1089 struct hfc_register_names {
1090  char *name;
1091  u_char reg;
1092 } hfc_register_names[] = {
1093  /* write registers */
1094  {"R_CIRM", 0x00},
1095  {"R_CTRL", 0x01},
1096  {"R_BRG_PCM_CFG ", 0x02},
1097  {"R_RAM_ADDR0", 0x08},
1098  {"R_RAM_ADDR1", 0x09},
1099  {"R_RAM_ADDR2", 0x0A},
1100  {"R_FIRST_FIFO", 0x0B},
1101  {"R_RAM_SZ", 0x0C},
1102  {"R_FIFO_MD", 0x0D},
1103  {"R_INC_RES_FIFO", 0x0E},
1104  {"R_FIFO / R_FSM_IDX", 0x0F},
1105  {"R_SLOT", 0x10},
1106  {"R_IRQMSK_MISC", 0x11},
1107  {"R_SCI_MSK", 0x12},
1108  {"R_IRQ_CTRL", 0x13},
1109  {"R_PCM_MD0", 0x14},
1110  {"R_0x15", 0x15},
1111  {"R_ST_SEL", 0x16},
1112  {"R_ST_SYNC", 0x17},
1113  {"R_CONF_EN", 0x18},
1114  {"R_TI_WD", 0x1A},
1115  {"R_BERT_WD_MD", 0x1B},
1116  {"R_DTMF", 0x1C},
1117  {"R_DTMF_N", 0x1D},
1118  {"R_E1_XX_STA", 0x20},
1119  {"R_LOS0", 0x22},
1120  {"R_LOS1", 0x23},
1121  {"R_RX0", 0x24},
1122  {"R_RX_FR0", 0x25},
1123  {"R_RX_FR1", 0x26},
1124  {"R_TX0", 0x28},
1125  {"R_TX1", 0x29},
1126  {"R_TX_FR0", 0x2C},
1127  {"R_TX_FR1", 0x2D},
1128  {"R_TX_FR2", 0x2E},
1129  {"R_JATT_ATT", 0x2F},
1130  {"A_ST_xx_STA/R_RX_OFF", 0x30},
1131  {"A_ST_CTRL0/R_SYNC_OUT", 0x31},
1132  {"A_ST_CTRL1", 0x32},
1133  {"A_ST_CTRL2", 0x33},
1134  {"A_ST_SQ_WR", 0x34},
1135  {"R_TX_OFF", 0x34},
1136  {"R_SYNC_CTRL", 0x35},
1137  {"A_ST_CLK_DLY", 0x37},
1138  {"R_PWM0", 0x38},
1139  {"R_PWM1", 0x39},
1140  {"A_ST_B1_TX", 0x3C},
1141  {"A_ST_B2_TX", 0x3D},
1142  {"A_ST_D_TX", 0x3E},
1143  {"R_GPIO_OUT0", 0x40},
1144  {"R_GPIO_OUT1", 0x41},
1145  {"R_GPIO_EN0", 0x42},
1146  {"R_GPIO_EN1", 0x43},
1147  {"R_GPIO_SEL", 0x44},
1148  {"R_BRG_CTRL", 0x45},
1149  {"R_PWM_MD", 0x46},
1150  {"R_BRG_MD", 0x47},
1151  {"R_BRG_TIM0", 0x48},
1152  {"R_BRG_TIM1", 0x49},
1153  {"R_BRG_TIM2", 0x4A},
1154  {"R_BRG_TIM3", 0x4B},
1155  {"R_BRG_TIM_SEL01", 0x4C},
1156  {"R_BRG_TIM_SEL23", 0x4D},
1157  {"R_BRG_TIM_SEL45", 0x4E},
1158  {"R_BRG_TIM_SEL67", 0x4F},
1159  {"A_FIFO_DATA0-2", 0x80},
1160  {"A_FIFO_DATA0-2_NOINC", 0x84},
1161  {"R_RAM_DATA", 0xC0},
1162  {"A_SL_CFG", 0xD0},
1163  {"A_CONF", 0xD1},
1164  {"A_CH_MSK", 0xF4},
1165  {"A_CON_HDLC", 0xFA},
1166  {"A_SUBCH_CFG", 0xFB},
1167  {"A_CHANNEL", 0xFC},
1168  {"A_FIFO_SEQ", 0xFD},
1169  {"A_IRQ_MSK", 0xFF},
1170  {NULL, 0},
1171 
1172  /* read registers */
1173  {"A_Z1", 0x04},
1174  {"A_Z1H", 0x05},
1175  {"A_Z2", 0x06},
1176  {"A_Z2H", 0x07},
1177  {"A_F1", 0x0C},
1178  {"A_F2", 0x0D},
1179  {"R_IRQ_OVIEW", 0x10},
1180  {"R_IRQ_MISC", 0x11},
1181  {"R_IRQ_STATECH", 0x12},
1182  {"R_CONF_OFLOW", 0x14},
1183  {"R_RAM_USE", 0x15},
1184  {"R_CHIP_ID", 0x16},
1185  {"R_BERT_STA", 0x17},
1186  {"R_F0_CNTL", 0x18},
1187  {"R_F0_CNTH", 0x19},
1188  {"R_BERT_ECL", 0x1A},
1189  {"R_BERT_ECH", 0x1B},
1190  {"R_STATUS", 0x1C},
1191  {"R_CHIP_RV", 0x1F},
1192  {"R_STATE", 0x20},
1193  {"R_SYNC_STA", 0x24},
1194  {"R_RX_SL0_0", 0x25},
1195  {"R_RX_SL0_1", 0x26},
1196  {"R_RX_SL0_2", 0x27},
1197  {"R_JATT_DIR", 0x2b},
1198  {"R_SLIP", 0x2c},
1199  {"A_ST_RD_STA", 0x30},
1200  {"R_FAS_ECL", 0x30},
1201  {"R_FAS_ECH", 0x31},
1202  {"R_VIO_ECL", 0x32},
1203  {"R_VIO_ECH", 0x33},
1204  {"R_CRC_ECL / A_ST_SQ_RD", 0x34},
1205  {"R_CRC_ECH", 0x35},
1206  {"R_E_ECL", 0x36},
1207  {"R_E_ECH", 0x37},
1208  {"R_SA6_SA13_ECL", 0x38},
1209  {"R_SA6_SA13_ECH", 0x39},
1210  {"R_SA6_SA23_ECL", 0x3A},
1211  {"R_SA6_SA23_ECH", 0x3B},
1212  {"A_ST_B1_RX", 0x3C},
1213  {"A_ST_B2_RX", 0x3D},
1214  {"A_ST_D_RX", 0x3E},
1215  {"A_ST_E_RX", 0x3F},
1216  {"R_GPIO_IN0", 0x40},
1217  {"R_GPIO_IN1", 0x41},
1218  {"R_GPI_IN0", 0x44},
1219  {"R_GPI_IN1", 0x45},
1220  {"R_GPI_IN2", 0x46},
1221  {"R_GPI_IN3", 0x47},
1222  {"A_FIFO_DATA0-2", 0x80},
1223  {"A_FIFO_DATA0-2_NOINC", 0x84},
1224  {"R_INT_DATA", 0x88},
1225  {"R_RAM_DATA", 0xC0},
1226  {"R_IRQ_FIFO_BL0", 0xC8},
1227  {"R_IRQ_FIFO_BL1", 0xC9},
1228  {"R_IRQ_FIFO_BL2", 0xCA},
1229  {"R_IRQ_FIFO_BL3", 0xCB},
1230  {"R_IRQ_FIFO_BL4", 0xCC},
1231  {"R_IRQ_FIFO_BL5", 0xCD},
1232  {"R_IRQ_FIFO_BL6", 0xCE},
1233  {"R_IRQ_FIFO_BL7", 0xCF},
1234 };
1235 #endif /* HFC_REGISTER_DEBUG */
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