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| #define FIFO_EMPTY 0xffffffff |
| #define HPSA_BOARD_NOT_READY_ITERATIONS |
Value:
Definition at line 199 of file hpsa.h.
| #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) |
| #define HPSA_BOARD_READY_ITERATIONS |
Value:
Definition at line 196 of file hpsa.h.
| #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) |
| #define HPSA_BOARD_READY_WAIT_SECS (120) |
| #define HPSA_DEVICE_RESET_MSG 1 |
| #define HPSA_ERROR_BIT 0x02 |
| #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ |
| #define HPSA_MAX_POLL_TIME_SECS (20) |
| #define HPSA_MAX_WAIT_INTERVAL_SECS (30) |
| #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) |
| #define HPSA_MSG_SEND_RETRY_LIMIT 10 |
| #define HPSA_POST_RESET_NOOP_RETRIES (12) |
| #define HPSA_POST_RESET_PAUSE_MSECS (3000) |
| #define HPSA_RESET_TYPE_BUS 0x01 |
| #define HPSA_RESET_TYPE_CONTROLLER 0x00 |
| #define HPSA_RESET_TYPE_LUN 0x04 |
| #define HPSA_RESET_TYPE_TARGET 0x03 |
| #define HPSA_TUR_RETRY_LIMIT (20) |
| #define HPSATMF_BITS_SUPPORTED (1 << 0) |
| #define HPSATMF_LOG_CLEAR_ACA (1 << 21) |
| #define HPSATMF_LOG_CLEAR_TSET (1 << 22) |
| #define HPSATMF_LOG_LUN_RESET (1 << 17) |
| #define HPSATMF_LOG_NEX_RESET (1 << 18) |
| #define HPSATMF_LOG_QRY_ASYNC (1 << 25) |
| #define HPSATMF_LOG_QRY_TASK (1 << 23) |
| #define HPSATMF_LOG_QRY_TSET (1 << 24) |
| #define HPSATMF_LOG_TASK_ABORT (1 << 19) |
| #define HPSATMF_LOG_TSET_ABORT (1 << 20) |
| #define HPSATMF_MASK_SUPPORTED (1 << 16) |
| #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) |
| #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) |
| #define HPSATMF_PHYS_LUN_RESET (1 << 1) |
| #define HPSATMF_PHYS_NEX_RESET (1 << 2) |
| #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) |
| #define HPSATMF_PHYS_QRY_TASK (1 << 7) |
| #define HPSATMF_PHYS_QRY_TSET (1 << 8) |
| #define HPSATMF_PHYS_TASK_ABORT (1 << 3) |
| #define HPSATMF_PHYS_TSET_ABORT (1 << 4) |
| #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" |
| #define SA5_CTCFG_OFFSET 0xB4 |
| #define SA5_CTMEM_OFFSET 0xB8 |
| #define SA5_DOORBELL 0x20 |
| #define SA5_INTR_OFF 0x08 |
| #define SA5_INTR_PENDING 0x08 |
| #define SA5_INTR_STATUS 0x30 |
| #define SA5_OUTDB_CLEAR 0xA0 |
| #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
| #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
| #define SA5_OUTDB_STATUS 0x9C |
| #define SA5_OUTDB_STATUS_PERF_BIT 0x01 |
| #define SA5_PERF_INTR_OFF 0x05 |
| #define SA5_PERF_INTR_PENDING 0x04 |
| #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
| #define SA5_REPLY_PORT_OFFSET 0x44 |
| #define SA5_REQUEST_PORT_OFFSET 0x40 |
| #define SA5_SCRATCHPAD_OFFSET 0xB0 |
| #define SA5B_INTR_OFF 0x04 |
| #define SA5B_INTR_PENDING 0x04 |
| #define SIMPLE_MODE_INT 2 |
1.8.2