#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/module.h>
#include <asm/clock.h>
#include <asm/i2c-sh7760.h>

Data Structures
struct	cami2c

Macros
#define	I2CSCR 0x0 /* slave ctrl */

#define	I2CMCR 0x4 /* master ctrl */

#define	I2CSSR 0x8 /* slave status */

#define	I2CMSR 0xC /* master status */

#define	I2CSIER 0x10 /* slave irq enable */

#define	I2CMIER 0x14 /* master irq enable */

#define	I2CCCR 0x18 /* clock dividers */

#define	I2CSAR 0x1c /* slave address */

#define	I2CMAR 0x20 /* master address */

#define	I2CRXTX 0x24 /* data port */

#define	I2CFCR 0x28 /* fifo control */

#define	I2CFSR 0x2C /* fifo status */

#define	I2CFIER 0x30 /* fifo irq enable */

#define	I2CRFDR 0x34 /* rx fifo count */

#define	I2CTFDR 0x38 /* tx fifo count */

#define	REGSIZE 0x3C

#define	MCR_MDBS 0x80 /* non-fifo mode switch */

#define	MCR_FSCL 0x40 /* override SCL pin */

#define	MCR_FSDA 0x20 /* override SDA pin */

#define	MCR_OBPC 0x10 /* override pins */

#define	MCR_MIE 0x08 /* master if enable */

#define	MCR_TSBE 0x04

#define	MCR_FSB 0x02 /* force stop bit */

#define	MCR_ESG 0x01 /* en startbit gen. */

#define	MSR_MNR 0x40 /* nack received */

#define	MSR_MAL 0x20 /* arbitration lost */

#define	MSR_MST 0x10 /* sent a stop */

#define	MSR_MDE 0x08

#define	MSR_MDT 0x04

#define	MSR_MDR 0x02

#define	MSR_MAT 0x01 /* slave addr xfer done */

#define	MIE_MNRE 0x40 /* nack irq en */

#define	MIE_MALE 0x20 /* arblos irq en */

#define	MIE_MSTE 0x10 /* stop irq en */

#define	MIE_MDEE 0x08

#define	MIE_MDTE 0x04

#define	MIE_MDRE 0x02

#define	MIE_MATE 0x01 /* address sent irq en */

#define	FCR_RFRST 0x02 /* reset rx fifo */

#define	FCR_TFRST 0x01 /* reset tx fifo */

#define	FSR_TEND 0x04 /* last byte sent */

#define	FSR_RDF 0x02 /* rx fifo trigger */

#define	FSR_TDFE 0x01 /* tx fifo empty */

#define	FIER_TEIE 0x04 /* tx fifo empty irq en */

#define	FIER_RXIE 0x02 /* rx fifo trig irq en */

#define	FIER_TXIE 0x01 /* tx fifo trig irq en */

#define	FIFO_SIZE 16

#define	IDF_SEND 1

#define	IDF_RECV 2

#define	IDF_STOP 4

#define	IDS_DONE 1

#define	IDS_ARBLOST 2

#define	IDS_NACK 4

Functions
	module_platform_driver (sh7760_i2c_drv)

	MODULE_LICENSE ("GPL")

	MODULE_DESCRIPTION ("SH7760 I2C bus driver")

	MODULE_AUTHOR ("Manuel Lauss <[email protected]>")

Macro Definition Documentation

#define FCR_RFRST 0x02 /* reset rx fifo */

Definition at line 69 of file i2c-sh7760.c.

#define FCR_TFRST 0x01 /* reset tx fifo */

Definition at line 70 of file i2c-sh7760.c.

#define FIER_RXIE 0x02 /* rx fifo trig irq en */

Definition at line 77 of file i2c-sh7760.c.

#define FIER_TEIE 0x04 /* tx fifo empty irq en */

Definition at line 76 of file i2c-sh7760.c.

#define FIER_TXIE 0x01 /* tx fifo trig irq en */

Definition at line 78 of file i2c-sh7760.c.

#define FIFO_SIZE 16

Definition at line 80 of file i2c-sh7760.c.

#define FSR_RDF 0x02 /* rx fifo trigger */

Definition at line 73 of file i2c-sh7760.c.

#define FSR_TDFE 0x01 /* tx fifo empty */

Definition at line 74 of file i2c-sh7760.c.

#define FSR_TEND 0x04 /* last byte sent */

Definition at line 72 of file i2c-sh7760.c.

#define I2CCCR 0x18 /* clock dividers */

Definition at line 32 of file i2c-sh7760.c.

#define I2CFCR 0x28 /* fifo control */

Definition at line 36 of file i2c-sh7760.c.

#define I2CFIER 0x30 /* fifo irq enable */

Definition at line 38 of file i2c-sh7760.c.

#define I2CFSR 0x2C /* fifo status */

Definition at line 37 of file i2c-sh7760.c.

#define I2CMAR 0x20 /* master address */

Definition at line 34 of file i2c-sh7760.c.

#define I2CMCR 0x4 /* master ctrl */

Definition at line 27 of file i2c-sh7760.c.

#define I2CMIER 0x14 /* master irq enable */

Definition at line 31 of file i2c-sh7760.c.

#define I2CMSR 0xC /* master status */

Definition at line 29 of file i2c-sh7760.c.

#define I2CRFDR 0x34 /* rx fifo count */

Definition at line 39 of file i2c-sh7760.c.

#define I2CRXTX 0x24 /* data port */

Definition at line 35 of file i2c-sh7760.c.

#define I2CSAR 0x1c /* slave address */

Definition at line 33 of file i2c-sh7760.c.

#define I2CSCR 0x0 /* slave ctrl */

Definition at line 26 of file i2c-sh7760.c.

#define I2CSIER 0x10 /* slave irq enable */

Definition at line 30 of file i2c-sh7760.c.

#define I2CSSR 0x8 /* slave status */

Definition at line 28 of file i2c-sh7760.c.

#define I2CTFDR 0x38 /* tx fifo count */

Definition at line 40 of file i2c-sh7760.c.

#define IDF_RECV 2

Definition at line 89 of file i2c-sh7760.c.

#define IDF_SEND 1

Definition at line 88 of file i2c-sh7760.c.

#define IDF_STOP 4

Definition at line 90 of file i2c-sh7760.c.

#define IDS_ARBLOST 2

Definition at line 94 of file i2c-sh7760.c.

#define IDS_DONE 1

Definition at line 93 of file i2c-sh7760.c.

#define IDS_NACK 4

Definition at line 95 of file i2c-sh7760.c.

#define MCR_ESG 0x01 /* en startbit gen. */

Definition at line 51 of file i2c-sh7760.c.

#define MCR_FSB 0x02 /* force stop bit */

Definition at line 50 of file i2c-sh7760.c.

#define MCR_FSCL 0x40 /* override SCL pin */

Definition at line 45 of file i2c-sh7760.c.

#define MCR_FSDA 0x20 /* override SDA pin */

Definition at line 46 of file i2c-sh7760.c.

#define MCR_MDBS 0x80 /* non-fifo mode switch */

Definition at line 44 of file i2c-sh7760.c.

#define MCR_MIE 0x08 /* master if enable */

Definition at line 48 of file i2c-sh7760.c.

#define MCR_OBPC 0x10 /* override pins */

Definition at line 47 of file i2c-sh7760.c.

#define MCR_TSBE 0x04

Definition at line 49 of file i2c-sh7760.c.

#define MIE_MALE 0x20 /* arblos irq en */

Definition at line 62 of file i2c-sh7760.c.

#define MIE_MATE 0x01 /* address sent irq en */

Definition at line 67 of file i2c-sh7760.c.

#define MIE_MDEE 0x08

Definition at line 64 of file i2c-sh7760.c.

#define MIE_MDRE 0x02

Definition at line 66 of file i2c-sh7760.c.

#define MIE_MDTE 0x04

Definition at line 65 of file i2c-sh7760.c.

#define MIE_MNRE 0x40 /* nack irq en */

Definition at line 61 of file i2c-sh7760.c.

#define MIE_MSTE 0x10 /* stop irq en */

Definition at line 63 of file i2c-sh7760.c.

#define MSR_MAL 0x20 /* arbitration lost */

Definition at line 54 of file i2c-sh7760.c.

#define MSR_MAT 0x01 /* slave addr xfer done */

Definition at line 59 of file i2c-sh7760.c.

#define MSR_MDE 0x08

Definition at line 56 of file i2c-sh7760.c.

#define MSR_MDR 0x02

Definition at line 58 of file i2c-sh7760.c.

#define MSR_MDT 0x04

Definition at line 57 of file i2c-sh7760.c.

#define MSR_MNR 0x40 /* nack received */

Definition at line 53 of file i2c-sh7760.c.

#define MSR_MST 0x10 /* sent a stop */

Definition at line 55 of file i2c-sh7760.c.

#define REGSIZE 0x3C

Definition at line 42 of file i2c-sh7760.c.

Function Documentation

MODULE_AUTHOR ( "Manuel Lauss <[email protected]>" )

MODULE_DESCRIPTION ( "SH7760 I2C bus driver" )

MODULE_LICENSE ( "GPL" )

module_platform_driver ( sh7760_i2c_drv )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation