#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
Go to the source code of this file.
|
| enum | stu300_event {
STU300_EVENT_NONE = 0,
STU300_EVENT_1,
STU300_EVENT_2,
STU300_EVENT_3,
STU300_EVENT_4,
STU300_EVENT_5,
STU300_EVENT_6,
STU300_EVENT_7,
STU300_EVENT_8,
STU300_EVENT_9
} |
| |
| enum | stu300_error {
STU300_ERROR_NONE = 0,
STU300_ERROR_ACKNOWLEDGE_FAILURE,
STU300_ERROR_BUS_ERROR,
STU300_ERROR_ARBITRATION_LOST,
STU300_ERROR_UNKNOWN
} |
| |
| #define BUSY_RELEASE_ATTEMPTS 10 |
| #define I2C_CCR (0x0000000C) |
| #define I2C_CCR_CC_MASK (0x7F) |
| #define I2C_CCR_FMSM (0x80) |
| #define I2C_CCR_MASK (0xFF) |
| #define I2C_CCR_RESET_UMASK (0x00) |
| #define I2C_CCR_RESET_VALUE (0x00) |
| #define I2C_CR (0x00000000) |
| #define I2C_CR_ACK_ENABLE (0x04) |
| #define I2C_CR_DDC1_ENABLE (0x80) |
| #define I2C_CR_DDC2B_ENABLE (0x10) |
| #define I2C_CR_INTERRUPT_ENABLE (0x01) |
| #define I2C_CR_PERIPHERAL_ENABLE (0x20) |
| #define I2C_CR_RESET_UMASK (0x00) |
| #define I2C_CR_RESET_VALUE (0x00) |
| #define I2C_CR_START_ENABLE (0x08) |
| #define I2C_CR_STOP_ENABLE (0x02) |
| #define I2C_CR_TRANS_ENABLE (0x40) |
| #define I2C_DR (0x00000018) |
| #define I2C_DR_D_MASK (0xFF) |
| #define I2C_DR_RESET_UMASK (0xFF) |
| #define I2C_DR_RESET_VALUE (0x00) |
| #define I2C_ECCR (0x0000001C) |
| #define I2C_ECCR_CC_MASK (0x1F) |
| #define I2C_ECCR_MASK (0x1F) |
| #define I2C_ECCR_RESET_UMASK (0xE0) |
| #define I2C_ECCR_RESET_VALUE (0x00) |
| #define I2C_OAR1 (0x00000010) |
| #define I2C_OAR1_ADD_MASK (0xFF) |
| #define I2C_OAR1_RESET_UMASK (0x00) |
| #define I2C_OAR1_RESET_VALUE (0x00) |
| #define I2C_OAR2 (0x00000014) |
| #define I2C_OAR2_ADD_MASK (0x06) |
| #define I2C_OAR2_FR_10_1667MHZ (0x20) |
| #define I2C_OAR2_FR_1667_2667MHZ (0x40) |
| #define I2C_OAR2_FR_25_10MHZ (0x00) |
| #define I2C_OAR2_FR_2667_40MHZ (0x60) |
| #define I2C_OAR2_FR_40_5333MHZ (0x80) |
| #define I2C_OAR2_FR_5333_66MHZ (0xA0) |
| #define I2C_OAR2_FR_66_80MHZ (0xC0) |
| #define I2C_OAR2_FR_80_100MHZ (0xE0) |
| #define I2C_OAR2_FR_MASK (0xE0) |
| #define I2C_OAR2_MASK (0xE6) |
| #define I2C_OAR2_RESET_UMASK (0x19) |
| #define I2C_OAR2_RESET_VALUE (0x40) |
| #define I2C_SR1 (0x00000004) |
| #define I2C_SR1_ADD10_IND (0x40) |
| #define I2C_SR1_ADSL_IND (0x04) |
| #define I2C_SR1_BTF_IND (0x08) |
| #define I2C_SR1_BUSY_IND (0x10) |
| #define I2C_SR1_EVF_IND (0x80) |
| #define I2C_SR1_MSL_IND (0x02) |
| #define I2C_SR1_RESET_UMASK (0x00) |
| #define I2C_SR1_RESET_VALUE (0x00) |
| #define I2C_SR1_SB_IND (0x01) |
| #define I2C_SR1_TRA_IND (0x20) |
| #define I2C_SR2 (0x00000008) |
| #define I2C_SR2_AF_IND (0x10) |
| #define I2C_SR2_ARLO_IND (0x04) |
| #define I2C_SR2_BERR_IND (0x02) |
| #define I2C_SR2_DDC2BF_IND (0x01) |
| #define I2C_SR2_ENDAD_IND (0x20) |
| #define I2C_SR2_MASK (0xBF) |
| #define I2C_SR2_RESET_UMASK (0x40) |
| #define I2C_SR2_RESET_VALUE (0x00) |
| #define I2C_SR2_SCLFAL_IND (0x80) |
| #define I2C_SR2_STOPF_IND (0x08) |
| #define NUM_ADDR_RESEND_ATTEMPTS 12 |
| #define STU300_I2C_PM NULL |
- Enumerator:
| STU300_ERROR_NONE |
|
| STU300_ERROR_ACKNOWLEDGE_FAILURE |
|
| STU300_ERROR_BUS_ERROR |
|
| STU300_ERROR_ARBITRATION_LOST |
|
| STU300_ERROR_UNKNOWN |
|
Definition at line 117 of file i2c-stu300.c.
- Enumerator:
| STU300_EVENT_NONE |
|
| STU300_EVENT_1 |
|
| STU300_EVENT_2 |
|
| STU300_EVENT_3 |
|
| STU300_EVENT_4 |
|
| STU300_EVENT_5 |
|
| STU300_EVENT_6 |
|
| STU300_EVENT_7 |
|
| STU300_EVENT_8 |
|
| STU300_EVENT_9 |
|
Definition at line 104 of file i2c-stu300.c.
| MODULE_ALIAS |
( |
"platform:" |
NAME | ) |
|
| module_exit |
( |
stu300_exit |
| ) |
|
| module_param |
( |
scl_frequency |
, |
|
|
uint |
, |
|
|
0644 |
|
|
) |
| |
| subsys_initcall |
( |
stu300_init |
| ) |
|
1.8.2