i2c-xiic.c File Reference

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-xiic.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of_i2c.h>

Go to the source code of this file.

Data Structures
struct	xiic_i2c

Macros
#define	DRIVER_NAME   "xiic-i2c"
#define	XIIC_MSB_OFFSET   0
#define	XIIC_REG_OFFSET   (0x100+XIIC_MSB_OFFSET)
#define	XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET) /* Control Register */
#define	XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET) /* Status Register */
#define	XIIC_DTR_REG_OFFSET   (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
#define	XIIC_DRR_REG_OFFSET   (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
#define	XIIC_ADR_REG_OFFSET   (0x10+XIIC_REG_OFFSET) /* Address Register */
#define	XIIC_TFO_REG_OFFSET   (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
#define	XIIC_RFO_REG_OFFSET   (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
#define	XIIC_TBA_REG_OFFSET   (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
#define	XIIC_RFD_REG_OFFSET   (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
#define	XIIC_GPO_REG_OFFSET   (0x24+XIIC_REG_OFFSET) /* Output Register */
#define	XIIC_CR_ENABLE_DEVICE_MASK   0x01 /* Device enable = 1 */
#define	XIIC_CR_TX_FIFO_RESET_MASK   0x02 /* Transmit FIFO reset=1 */
#define	XIIC_CR_MSMS_MASK   0x04 /* Master starts Txing=1 */
#define	XIIC_CR_DIR_IS_TX_MASK   0x08 /* Dir of tx. Txing=1 */
#define	XIIC_CR_NO_ACK_MASK   0x10 /* Tx Ack. NO ack = 1 */
#define	XIIC_CR_REPEATED_START_MASK   0x20 /* Repeated start = 1 */
#define	XIIC_CR_GENERAL_CALL_MASK   0x40 /* Gen Call enabled = 1 */
#define	XIIC_SR_GEN_CALL_MASK   0x01 /* 1=a mstr issued a GC */
#define	XIIC_SR_ADDR_AS_SLAVE_MASK   0x02 /* 1=when addr as slave */
#define	XIIC_SR_BUS_BUSY_MASK   0x04 /* 1 = bus is busy */
#define	XIIC_SR_MSTR_RDING_SLAVE_MASK   0x08 /* 1=Dir: mstr <-- slave */
#define	XIIC_SR_TX_FIFO_FULL_MASK   0x10 /* 1 = Tx FIFO full */
#define	XIIC_SR_RX_FIFO_FULL_MASK   0x20 /* 1 = Rx FIFO full */
#define	XIIC_SR_RX_FIFO_EMPTY_MASK   0x40 /* 1 = Rx FIFO empty */
#define	XIIC_SR_TX_FIFO_EMPTY_MASK   0x80 /* 1 = Tx FIFO empty */
#define	XIIC_INTR_ARB_LOST_MASK   0x01 /* 1 = arbitration lost */
#define	XIIC_INTR_TX_ERROR_MASK   0x02 /* 1=Tx error/msg complete */
#define	XIIC_INTR_TX_EMPTY_MASK   0x04 /* 1 = Tx FIFO/reg empty */
#define	XIIC_INTR_RX_FULL_MASK   0x08 /* 1=Rx FIFO/reg=OCY level */
#define	XIIC_INTR_BNB_MASK   0x10 /* 1 = Bus not busy */
#define	XIIC_INTR_AAS_MASK   0x20 /* 1 = when addr as slave */
#define	XIIC_INTR_NAAS_MASK   0x40 /* 1 = not addr as slave */
#define	XIIC_INTR_TX_HALF_MASK   0x80 /* 1 = TX FIFO half empty */
#define	IIC_RX_FIFO_DEPTH   16 /* Rx fifo capacity */
#define	IIC_TX_FIFO_DEPTH   16 /* Tx fifo capacity */
#define	XIIC_TX_INTERRUPTS   (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
#define	XIIC_TX_RX_INTERRUPTS   (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
#define	XIIC_READ_OPERATION   1
#define	XIIC_WRITE_OPERATION   0
#define	XIIC_TX_DYN_START_MASK   0x0100 /* 1 = Set dynamic start */
#define	XIIC_TX_DYN_STOP_MASK   0x0200 /* 1 = Set dynamic stop */
#define	XIIC_DGIER_OFFSET   0x1C /* Device Global Interrupt Enable Register */
#define	XIIC_IISR_OFFSET   0x20 /* Interrupt Status Register */
#define	XIIC_IIER_OFFSET   0x28 /* Interrupt Enable Register */
#define	XIIC_RESETR_OFFSET   0x40 /* Reset Register */
#define	XIIC_RESET_MASK   0xAUL
#define	XIIC_GINTR_ENABLE_MASK   0x80000000UL
#define	xiic_tx_space(i2c)   ((i2c)->tx_msg->len - (i2c)->tx_pos)
#define	xiic_rx_space(i2c)   ((i2c)->rx_msg->len - (i2c)->rx_pos)

Enumerations
enum	xilinx_i2c_state { STATE_DONE, STATE_ERROR, STATE_START }

Functions
	module_platform_driver (xiic_i2c_driver)
	MODULE_AUTHOR ("[email protected]")
	MODULE_DESCRIPTION ("Xilinx I2C bus driver")
	MODULE_LICENSE ("GPL v2")
	MODULE_ALIAS ("platform:"DRIVER_NAME)

Macro Definition Documentation

#define DRIVER_NAME   "xiic-i2c"

Definition at line 45 of file i2c-xiic.c.

#define IIC_RX_FIFO_DEPTH   16 /* Rx fifo capacity */

Definition at line 128 of file i2c-xiic.c.

#define IIC_TX_FIFO_DEPTH   16 /* Tx fifo capacity */

Definition at line 129 of file i2c-xiic.c.

#define XIIC_ADR_REG_OFFSET   (0x10+XIIC_REG_OFFSET) /* Address Register */

Definition at line 91 of file i2c-xiic.c.

#define XIIC_CR_DIR_IS_TX_MASK   0x08 /* Dir of tx. Txing=1 */

Definition at line 102 of file i2c-xiic.c.

#define XIIC_CR_ENABLE_DEVICE_MASK   0x01 /* Device enable = 1 */

Definition at line 99 of file i2c-xiic.c.

#define XIIC_CR_GENERAL_CALL_MASK   0x40 /* Gen Call enabled = 1 */

Definition at line 105 of file i2c-xiic.c.

#define XIIC_CR_MSMS_MASK   0x04 /* Master starts Txing=1 */

Definition at line 101 of file i2c-xiic.c.

#define XIIC_CR_NO_ACK_MASK   0x10 /* Tx Ack. NO ack = 1 */

Definition at line 103 of file i2c-xiic.c.

#define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET) /* Control Register */

Definition at line 87 of file i2c-xiic.c.

#define XIIC_CR_REPEATED_START_MASK   0x20 /* Repeated start = 1 */

Definition at line 104 of file i2c-xiic.c.

#define XIIC_CR_TX_FIFO_RESET_MASK   0x02 /* Transmit FIFO reset=1 */

Definition at line 100 of file i2c-xiic.c.

#define XIIC_DGIER_OFFSET   0x1C /* Device Global Interrupt Enable Register */

Definition at line 157 of file i2c-xiic.c.

#define XIIC_DRR_REG_OFFSET   (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */

Definition at line 90 of file i2c-xiic.c.

#define XIIC_DTR_REG_OFFSET   (0x08+XIIC_REG_OFFSET) /* Data Tx Register */

Definition at line 89 of file i2c-xiic.c.

#define XIIC_GINTR_ENABLE_MASK   0x80000000UL

Definition at line 169 of file i2c-xiic.c.

#define XIIC_GPO_REG_OFFSET   (0x24+XIIC_REG_OFFSET) /* Output Register */

Definition at line 96 of file i2c-xiic.c.

#define XIIC_IIER_OFFSET   0x28 /* Interrupt Enable Register */

Definition at line 159 of file i2c-xiic.c.

#define XIIC_IISR_OFFSET   0x20 /* Interrupt Status Register */

Definition at line 158 of file i2c-xiic.c.

#define XIIC_INTR_AAS_MASK   0x20 /* 1 = when addr as slave */

Definition at line 123 of file i2c-xiic.c.

#define XIIC_INTR_ARB_LOST_MASK   0x01 /* 1 = arbitration lost */

Definition at line 118 of file i2c-xiic.c.

#define XIIC_INTR_BNB_MASK   0x10 /* 1 = Bus not busy */

Definition at line 122 of file i2c-xiic.c.

#define XIIC_INTR_NAAS_MASK   0x40 /* 1 = not addr as slave */

Definition at line 124 of file i2c-xiic.c.

#define XIIC_INTR_RX_FULL_MASK   0x08 /* 1=Rx FIFO/reg=OCY level */

Definition at line 121 of file i2c-xiic.c.

#define XIIC_INTR_TX_EMPTY_MASK   0x04 /* 1 = Tx FIFO/reg empty */

Definition at line 120 of file i2c-xiic.c.

#define XIIC_INTR_TX_ERROR_MASK   0x02 /* 1=Tx error/msg complete */

Definition at line 119 of file i2c-xiic.c.

#define XIIC_INTR_TX_HALF_MASK   0x80 /* 1 = TX FIFO half empty */

Definition at line 125 of file i2c-xiic.c.

#define XIIC_MSB_OFFSET   0

Definition at line 80 of file i2c-xiic.c.

#define XIIC_READ_OPERATION   1

Definition at line 142 of file i2c-xiic.c.

#define XIIC_REG_OFFSET   (0x100+XIIC_MSB_OFFSET)

Definition at line 81 of file i2c-xiic.c.

#define XIIC_RESET_MASK   0xAUL

Definition at line 162 of file i2c-xiic.c.

#define XIIC_RESETR_OFFSET   0x40 /* Reset Register */

Definition at line 160 of file i2c-xiic.c.

#define XIIC_RFD_REG_OFFSET   (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */

Definition at line 95 of file i2c-xiic.c.

#define XIIC_RFO_REG_OFFSET   (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */

Definition at line 93 of file i2c-xiic.c.

#define xiic_rx_space

(

i2c

)

((i2c)->rx_msg->len - (i2c)->rx_pos)

Definition at line 172 of file i2c-xiic.c.

#define XIIC_SR_ADDR_AS_SLAVE_MASK   0x02 /* 1=when addr as slave */

Definition at line 109 of file i2c-xiic.c.

#define XIIC_SR_BUS_BUSY_MASK   0x04 /* 1 = bus is busy */

Definition at line 110 of file i2c-xiic.c.

#define XIIC_SR_GEN_CALL_MASK   0x01 /* 1=a mstr issued a GC */

Definition at line 108 of file i2c-xiic.c.

#define XIIC_SR_MSTR_RDING_SLAVE_MASK   0x08 /* 1=Dir: mstr <-- slave */

Definition at line 111 of file i2c-xiic.c.

#define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET) /* Status Register */

Definition at line 88 of file i2c-xiic.c.

#define XIIC_SR_RX_FIFO_EMPTY_MASK   0x40 /* 1 = Rx FIFO empty */

Definition at line 114 of file i2c-xiic.c.

#define XIIC_SR_RX_FIFO_FULL_MASK   0x20 /* 1 = Rx FIFO full */

Definition at line 113 of file i2c-xiic.c.

#define XIIC_SR_TX_FIFO_EMPTY_MASK   0x80 /* 1 = Tx FIFO empty */

Definition at line 115 of file i2c-xiic.c.

#define XIIC_SR_TX_FIFO_FULL_MASK   0x10 /* 1 = Tx FIFO full */

Definition at line 112 of file i2c-xiic.c.

#define XIIC_TBA_REG_OFFSET   (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */

Definition at line 94 of file i2c-xiic.c.

#define XIIC_TFO_REG_OFFSET   (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */

Definition at line 92 of file i2c-xiic.c.

#define XIIC_TX_DYN_START_MASK   0x0100 /* 1 = Set dynamic start */

Definition at line 148 of file i2c-xiic.c.

#define XIIC_TX_DYN_STOP_MASK   0x0200 /* 1 = Set dynamic stop */

Definition at line 149 of file i2c-xiic.c.

#define XIIC_TX_INTERRUPTS   (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)

Definition at line 134 of file i2c-xiic.c.

#define XIIC_TX_RX_INTERRUPTS   (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)

Definition at line 137 of file i2c-xiic.c.

#define xiic_tx_space

(

i2c

)

((i2c)->tx_msg->len - (i2c)->tx_pos)

Definition at line 171 of file i2c-xiic.c.

#define XIIC_WRITE_OPERATION   0

Definition at line 143 of file i2c-xiic.c.

Enumeration Type Documentation

enum xilinx_i2c_state

Enumerator:

STATE_DONE
STATE_ERROR
STATE_START

Definition at line 47 of file i2c-xiic.c.

Function Documentation

MODULE_ALIAS

(

"platform:"

DRIVER_NAME

)

MODULE_AUTHOR

(

"[email protected]"

)

MODULE_DESCRIPTION

(

"Xilinx I2C bus driver"

)

MODULE_LICENSE

(

"GPL v2"

)

module_platform_driver

(

xiic_i2c_driver

)