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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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| #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL |
| #define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL |
| #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL |
| #define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL |
| #define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL |
| #define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL |
| #define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL |
| #define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL |
| #define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL |
| #define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL |
| #define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL |
| #define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL |
| #define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL |
| #define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL |
| #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL |
| #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL |
| #define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL |
| #define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL |
| #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL |
| #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL |
| #define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL |
| #define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL |
| #define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL |
| #define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL |
| #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL |
| #define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL |
| #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL |
| #define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL |
| #define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL |
| #define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL |
| #define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL |
| #define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL |
| #define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL |
| #define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL |
| #define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL |
| #define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL |
| #define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL |
| #define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL |
| #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL |
| #define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL |
| #define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL |
| #define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL |
| #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL |
| #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL |
| #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL |
| #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL |
| #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL |
| #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL |
| #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL |
| #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL |
| #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL |
| #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL |
| #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL |
| #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL |
| #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL |
| #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL |
| #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL |
| #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL |
| #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL |
| #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL |
| #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL |
| #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL |
| #define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL |
| #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 |
| #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL |
| #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
| #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL |
| #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL |
| #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL |
| #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL |
| #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 |
| #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
| #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
| #define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
| #define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL |
| #define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
| #define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL |
| #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL |
| #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL |
| #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL |
| #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
| #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL |
| #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL |
| #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
| #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL |
| #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL |
| #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
| #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL |
1.8.2