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18 #ifndef _LBS_IF_SPI_H_
19 #define _LBS_IF_SPI_H_
21 #define IPFIELD_ALIGN_OFFSET 2
22 #define IF_SPI_CMD_BUF_SIZE 2400
26 #define IF_SPI_FW_NAME_MAX 30
28 #define MAX_MAIN_FW_LOAD_CRC_ERR 10
31 #define HELPER_FW_LOAD_CHUNK_SZ 64
34 #define FIRMWARE_DNLD_OK 0x0000
37 #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888
41 #define IF_SPI_READ_OPERATION_MASK 0x0
42 #define IF_SPI_WRITE_OPERATION_MASK 0x8000
45 #define IF_SPI_DEVICEID_CTRL_REG 0x00
46 #define IF_SPI_IO_READBASE_REG 0x04
47 #define IF_SPI_IO_WRITEBASE_REG 0x08
48 #define IF_SPI_IO_RDWRPORT_REG 0x0C
50 #define IF_SPI_CMD_READBASE_REG 0x10
51 #define IF_SPI_CMD_WRITEBASE_REG 0x14
52 #define IF_SPI_CMD_RDWRPORT_REG 0x18
54 #define IF_SPI_DATA_READBASE_REG 0x1C
55 #define IF_SPI_DATA_WRITEBASE_REG 0x20
56 #define IF_SPI_DATA_RDWRPORT_REG 0x24
58 #define IF_SPI_SCRATCH_1_REG 0x28
59 #define IF_SPI_SCRATCH_2_REG 0x2C
60 #define IF_SPI_SCRATCH_3_REG 0x30
61 #define IF_SPI_SCRATCH_4_REG 0x34
63 #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38
64 #define IF_SPI_TX_FRAME_STATUS_REG 0x3C
66 #define IF_SPI_HOST_INT_CTRL_REG 0x40
68 #define IF_SPI_CARD_INT_CAUSE_REG 0x44
69 #define IF_SPI_CARD_INT_STATUS_REG 0x48
70 #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C
71 #define IF_SPI_CARD_INT_STATUS_MASK_REG 0x50
73 #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54
75 #define IF_SPI_HOST_INT_CAUSE_REG 0x58
76 #define IF_SPI_HOST_INT_STATUS_REG 0x5C
77 #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60
78 #define IF_SPI_HOST_INT_STATUS_MASK_REG 0x64
79 #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68
81 #define IF_SPI_DELAY_READ_REG 0x6C
82 #define IF_SPI_SPU_BUS_MODE_REG 0x70
85 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
86 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)
90 #define IF_SPI_HICT_WAKE_UP (1<<0)
92 #define IF_SPI_HICT_WLAN_READY (1<<1)
97 #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO (1<<5)
99 #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO (1<<6)
101 #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO (1<<7)
103 #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO (1<<8)
107 #define IF_SPI_CIC_TX_DOWNLOAD_OVER (1<<0)
109 #define IF_SPI_CIC_RX_UPLOAD_OVER (1<<1)
111 #define IF_SPI_CIC_CMD_DOWNLOAD_OVER (1<<2)
113 #define IF_SPI_CIC_HOST_EVENT (1<<3)
115 #define IF_SPI_CIC_CMD_UPLOAD_OVER (1<<4)
117 #define IF_SPI_CIC_POWER_DOWN (1<<5)
120 #define IF_SPI_CIS_TX_DOWNLOAD_OVER (1<<0)
121 #define IF_SPI_CIS_RX_UPLOAD_OVER (1<<1)
122 #define IF_SPI_CIS_CMD_DOWNLOAD_OVER (1<<2)
123 #define IF_SPI_CIS_HOST_EVENT (1<<3)
124 #define IF_SPI_CIS_CMD_UPLOAD_OVER (1<<4)
125 #define IF_SPI_CIS_POWER_DOWN (1<<5)
128 #define IF_SPI_HICU_TX_DOWNLOAD_RDY (1<<0)
129 #define IF_SPI_HICU_RX_UPLOAD_RDY (1<<1)
130 #define IF_SPI_HICU_CMD_DOWNLOAD_RDY (1<<2)
131 #define IF_SPI_HICU_CARD_EVENT (1<<3)
132 #define IF_SPI_HICU_CMD_UPLOAD_RDY (1<<4)
133 #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW (1<<5)
134 #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW (1<<6)
135 #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW (1<<7)
136 #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW (1<<8)
137 #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW (1<<9)
138 #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW (1<<10)
142 #define IF_SPI_HIST_TX_DOWNLOAD_RDY (1<<0)
144 #define IF_SPI_HIST_RX_UPLOAD_RDY (1<<1)
146 #define IF_SPI_HIST_CMD_DOWNLOAD_RDY (1<<2)
148 #define IF_SPI_HIST_CARD_EVENT (1<<3)
150 #define IF_SPI_HIST_CMD_UPLOAD_RDY (1<<4)
152 #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW (1<<5)
154 #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW (1<<6)
156 #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW (1<<7)
158 #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW (1<<8)
160 #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW (1<<9)
162 #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW (1<<10)
166 #define IF_SPI_HISM_TX_DOWNLOAD_RDY (1<<0)
168 #define IF_SPI_HISM_RX_UPLOAD_RDY (1<<1)
170 #define IF_SPI_HISM_CMD_DOWNLOAD_RDY (1<<2)
172 #define IF_SPI_HISM_CARDEVENT (1<<3)
174 #define IF_SPI_HISM_CMD_UPLOAD_RDY (1<<4)
176 #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW (1<<5)
178 #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW (1<<6)
180 #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW (1<<7)
182 #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW (1<<8)
184 #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW (1<<9)
186 #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW (1<<10)
190 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8
191 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0
197 #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4
198 #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0
201 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00
202 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01
203 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02
204 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03