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if_spi.h File Reference

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Macros

#define IPFIELD_ALIGN_OFFSET   2
 
#define IF_SPI_CMD_BUF_SIZE   2400
 
#define IF_SPI_FW_NAME_MAX   30
 
#define MAX_MAIN_FW_LOAD_CRC_ERR   10
 
#define HELPER_FW_LOAD_CHUNK_SZ   64
 
#define FIRMWARE_DNLD_OK   0x0000
 
#define SUCCESSFUL_FW_DOWNLOAD_MAGIC   0x88888888
 
#define IF_SPI_READ_OPERATION_MASK   0x0
 
#define IF_SPI_WRITE_OPERATION_MASK   0x8000
 
#define IF_SPI_DEVICEID_CTRL_REG   0x00 /* DeviceID controller reg */
 
#define IF_SPI_IO_READBASE_REG   0x04 /* Read I/O base reg */
 
#define IF_SPI_IO_WRITEBASE_REG   0x08 /* Write I/O base reg */
 
#define IF_SPI_IO_RDWRPORT_REG   0x0C /* Read/Write I/O port reg */
 
#define IF_SPI_CMD_READBASE_REG   0x10 /* Read command base reg */
 
#define IF_SPI_CMD_WRITEBASE_REG   0x14 /* Write command base reg */
 
#define IF_SPI_CMD_RDWRPORT_REG   0x18 /* Read/Write command port reg */
 
#define IF_SPI_DATA_READBASE_REG   0x1C /* Read data base reg */
 
#define IF_SPI_DATA_WRITEBASE_REG   0x20 /* Write data base reg */
 
#define IF_SPI_DATA_RDWRPORT_REG   0x24 /* Read/Write data port reg */
 
#define IF_SPI_SCRATCH_1_REG   0x28 /* Scratch reg 1 */
 
#define IF_SPI_SCRATCH_2_REG   0x2C /* Scratch reg 2 */
 
#define IF_SPI_SCRATCH_3_REG   0x30 /* Scratch reg 3 */
 
#define IF_SPI_SCRATCH_4_REG   0x34 /* Scratch reg 4 */
 
#define IF_SPI_TX_FRAME_SEQ_NUM_REG   0x38 /* Tx frame sequence number reg */
 
#define IF_SPI_TX_FRAME_STATUS_REG   0x3C /* Tx frame status reg */
 
#define IF_SPI_HOST_INT_CTRL_REG   0x40 /* Host interrupt controller reg */
 
#define IF_SPI_CARD_INT_CAUSE_REG   0x44 /* Card interrupt cause reg */
 
#define IF_SPI_CARD_INT_STATUS_REG   0x48 /* Card interrupt status reg */
 
#define IF_SPI_CARD_INT_EVENT_MASK_REG   0x4C /* Card interrupt event mask */
 
#define IF_SPI_CARD_INT_STATUS_MASK_REG   0x50 /* Card interrupt status mask */
 
#define IF_SPI_CARD_INT_RESET_SELECT_REG   0x54 /* Card interrupt reset select */
 
#define IF_SPI_HOST_INT_CAUSE_REG   0x58 /* Host interrupt cause reg */
 
#define IF_SPI_HOST_INT_STATUS_REG   0x5C /* Host interrupt status reg */
 
#define IF_SPI_HOST_INT_EVENT_MASK_REG   0x60 /* Host interrupt event mask */
 
#define IF_SPI_HOST_INT_STATUS_MASK_REG   0x64 /* Host interrupt status mask */
 
#define IF_SPI_HOST_INT_RESET_SELECT_REG   0x68 /* Host interrupt reset select */
 
#define IF_SPI_DELAY_READ_REG   0x6C /* Delay read reg */
 
#define IF_SPI_SPU_BUS_MODE_REG   0x70 /* SPU BUS mode reg */
 
#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc)   ((dc & 0xffff0000)>>16)
 
#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc)   (dc & 0x000000ff)
 
#define IF_SPI_HICT_WAKE_UP   (1<<0)
 
#define IF_SPI_HICT_WLAN_READY   (1<<1)
 
#define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO   (1<<5)
 
#define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO   (1<<6)
 
#define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO   (1<<7)
 
#define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO   (1<<8)
 
#define IF_SPI_CIC_TX_DOWNLOAD_OVER   (1<<0)
 
#define IF_SPI_CIC_RX_UPLOAD_OVER   (1<<1)
 
#define IF_SPI_CIC_CMD_DOWNLOAD_OVER   (1<<2)
 
#define IF_SPI_CIC_HOST_EVENT   (1<<3)
 
#define IF_SPI_CIC_CMD_UPLOAD_OVER   (1<<4)
 
#define IF_SPI_CIC_POWER_DOWN   (1<<5)
 
#define IF_SPI_CIS_TX_DOWNLOAD_OVER   (1<<0)
 
#define IF_SPI_CIS_RX_UPLOAD_OVER   (1<<1)
 
#define IF_SPI_CIS_CMD_DOWNLOAD_OVER   (1<<2)
 
#define IF_SPI_CIS_HOST_EVENT   (1<<3)
 
#define IF_SPI_CIS_CMD_UPLOAD_OVER   (1<<4)
 
#define IF_SPI_CIS_POWER_DOWN   (1<<5)
 
#define IF_SPI_HICU_TX_DOWNLOAD_RDY   (1<<0)
 
#define IF_SPI_HICU_RX_UPLOAD_RDY   (1<<1)
 
#define IF_SPI_HICU_CMD_DOWNLOAD_RDY   (1<<2)
 
#define IF_SPI_HICU_CARD_EVENT   (1<<3)
 
#define IF_SPI_HICU_CMD_UPLOAD_RDY   (1<<4)
 
#define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW   (1<<5)
 
#define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW   (1<<6)
 
#define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW   (1<<7)
 
#define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW   (1<<8)
 
#define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW   (1<<9)
 
#define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW   (1<<10)
 
#define IF_SPI_HIST_TX_DOWNLOAD_RDY   (1<<0)
 
#define IF_SPI_HIST_RX_UPLOAD_RDY   (1<<1)
 
#define IF_SPI_HIST_CMD_DOWNLOAD_RDY   (1<<2)
 
#define IF_SPI_HIST_CARD_EVENT   (1<<3)
 
#define IF_SPI_HIST_CMD_UPLOAD_RDY   (1<<4)
 
#define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW   (1<<5)
 
#define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW   (1<<6)
 
#define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW   (1<<7)
 
#define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW   (1<<8)
 
#define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW   (1<<9)
 
#define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW   (1<<10)
 
#define IF_SPI_HISM_TX_DOWNLOAD_RDY   (1<<0)
 
#define IF_SPI_HISM_RX_UPLOAD_RDY   (1<<1)
 
#define IF_SPI_HISM_CMD_DOWNLOAD_RDY   (1<<2)
 
#define IF_SPI_HISM_CARDEVENT   (1<<3)
 
#define IF_SPI_HISM_CMD_UPLOAD_RDY   (1<<4)
 
#define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW   (1<<5)
 
#define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW   (1<<6)
 
#define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW   (1<<7)
 
#define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW   (1<<8)
 
#define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW   (1<<9)
 
#define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW   (1<<10)
 
#define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING   0x8
 
#define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING   0x0
 
#define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK   0x4
 
#define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED   0x0
 
#define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA   0x00
 
#define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA   0x01
 
#define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA   0x02
 
#define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA   0x03
 

Macro Definition Documentation

#define FIRMWARE_DNLD_OK   0x0000

Definition at line 34 of file if_spi.h.

#define HELPER_FW_LOAD_CHUNK_SZ   64

Definition at line 31 of file if_spi.h.

#define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA   0x02

Definition at line 203 of file if_spi.h.

#define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA   0x03

Definition at line 204 of file if_spi.h.

#define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA   0x00

Definition at line 201 of file if_spi.h.

#define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA   0x01

Definition at line 202 of file if_spi.h.

#define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK   0x4

Definition at line 197 of file if_spi.h.

#define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED   0x0

Definition at line 198 of file if_spi.h.

#define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING   0x8

Definition at line 190 of file if_spi.h.

#define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING   0x0

Definition at line 191 of file if_spi.h.

#define IF_SPI_CARD_INT_CAUSE_REG   0x44 /* Card interrupt cause reg */

Definition at line 68 of file if_spi.h.

#define IF_SPI_CARD_INT_EVENT_MASK_REG   0x4C /* Card interrupt event mask */

Definition at line 70 of file if_spi.h.

#define IF_SPI_CARD_INT_RESET_SELECT_REG   0x54 /* Card interrupt reset select */

Definition at line 73 of file if_spi.h.

#define IF_SPI_CARD_INT_STATUS_MASK_REG   0x50 /* Card interrupt status mask */

Definition at line 71 of file if_spi.h.

#define IF_SPI_CARD_INT_STATUS_REG   0x48 /* Card interrupt status reg */

Definition at line 69 of file if_spi.h.

#define IF_SPI_CIC_CMD_DOWNLOAD_OVER   (1<<2)

Definition at line 111 of file if_spi.h.

#define IF_SPI_CIC_CMD_UPLOAD_OVER   (1<<4)

Definition at line 115 of file if_spi.h.

#define IF_SPI_CIC_HOST_EVENT   (1<<3)

Definition at line 113 of file if_spi.h.

#define IF_SPI_CIC_POWER_DOWN   (1<<5)

Definition at line 117 of file if_spi.h.

#define IF_SPI_CIC_RX_UPLOAD_OVER   (1<<1)

Definition at line 109 of file if_spi.h.

#define IF_SPI_CIC_TX_DOWNLOAD_OVER   (1<<0)

Definition at line 107 of file if_spi.h.

#define IF_SPI_CIS_CMD_DOWNLOAD_OVER   (1<<2)

Definition at line 122 of file if_spi.h.

#define IF_SPI_CIS_CMD_UPLOAD_OVER   (1<<4)

Definition at line 124 of file if_spi.h.

#define IF_SPI_CIS_HOST_EVENT   (1<<3)

Definition at line 123 of file if_spi.h.

#define IF_SPI_CIS_POWER_DOWN   (1<<5)

Definition at line 125 of file if_spi.h.

#define IF_SPI_CIS_RX_UPLOAD_OVER   (1<<1)

Definition at line 121 of file if_spi.h.

#define IF_SPI_CIS_TX_DOWNLOAD_OVER   (1<<0)

Definition at line 120 of file if_spi.h.

#define IF_SPI_CMD_BUF_SIZE   2400

Definition at line 22 of file if_spi.h.

#define IF_SPI_CMD_RDWRPORT_REG   0x18 /* Read/Write command port reg */

Definition at line 52 of file if_spi.h.

#define IF_SPI_CMD_READBASE_REG   0x10 /* Read command base reg */

Definition at line 50 of file if_spi.h.

#define IF_SPI_CMD_WRITEBASE_REG   0x14 /* Write command base reg */

Definition at line 51 of file if_spi.h.

#define IF_SPI_DATA_RDWRPORT_REG   0x24 /* Read/Write data port reg */

Definition at line 56 of file if_spi.h.

#define IF_SPI_DATA_READBASE_REG   0x1C /* Read data base reg */

Definition at line 54 of file if_spi.h.

#define IF_SPI_DATA_WRITEBASE_REG   0x20 /* Write data base reg */

Definition at line 55 of file if_spi.h.

#define IF_SPI_DELAY_READ_REG   0x6C /* Delay read reg */

Definition at line 81 of file if_spi.h.

#define IF_SPI_DEVICEID_CTRL_REG   0x00 /* DeviceID controller reg */

Definition at line 45 of file if_spi.h.

#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID (   dc)    ((dc & 0xffff0000)>>16)

Definition at line 85 of file if_spi.h.

#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV (   dc)    (dc & 0x000000ff)

Definition at line 86 of file if_spi.h.

#define IF_SPI_FW_NAME_MAX   30

Definition at line 26 of file if_spi.h.

#define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO   (1<<7)

Definition at line 101 of file if_spi.h.

#define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO   (1<<8)

Definition at line 103 of file if_spi.h.

#define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO   (1<<6)

Definition at line 99 of file if_spi.h.

#define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO   (1<<5)

Definition at line 97 of file if_spi.h.

#define IF_SPI_HICT_WAKE_UP   (1<<0)

Definition at line 90 of file if_spi.h.

#define IF_SPI_HICT_WLAN_READY   (1<<1)

Definition at line 92 of file if_spi.h.

#define IF_SPI_HICU_CARD_EVENT   (1<<3)

Definition at line 131 of file if_spi.h.

#define IF_SPI_HICU_CMD_DOWNLOAD_RDY   (1<<2)

Definition at line 130 of file if_spi.h.

#define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW   (1<<10)

Definition at line 138 of file if_spi.h.

#define IF_SPI_HICU_CMD_UPLOAD_RDY   (1<<4)

Definition at line 132 of file if_spi.h.

#define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW   (1<<9)

Definition at line 137 of file if_spi.h.

#define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW   (1<<8)

Definition at line 136 of file if_spi.h.

#define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW   (1<<7)

Definition at line 135 of file if_spi.h.

#define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW   (1<<6)

Definition at line 134 of file if_spi.h.

#define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW   (1<<5)

Definition at line 133 of file if_spi.h.

#define IF_SPI_HICU_RX_UPLOAD_RDY   (1<<1)

Definition at line 129 of file if_spi.h.

#define IF_SPI_HICU_TX_DOWNLOAD_RDY   (1<<0)

Definition at line 128 of file if_spi.h.

#define IF_SPI_HISM_CARDEVENT   (1<<3)

Definition at line 172 of file if_spi.h.

#define IF_SPI_HISM_CMD_DOWNLOAD_RDY   (1<<2)

Definition at line 170 of file if_spi.h.

#define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW   (1<<10)

Definition at line 186 of file if_spi.h.

#define IF_SPI_HISM_CMD_UPLOAD_RDY   (1<<4)

Definition at line 174 of file if_spi.h.

#define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW   (1<<9)

Definition at line 184 of file if_spi.h.

#define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW   (1<<8)

Definition at line 182 of file if_spi.h.

#define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW   (1<<7)

Definition at line 180 of file if_spi.h.

#define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW   (1<<6)

Definition at line 178 of file if_spi.h.

#define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW   (1<<5)

Definition at line 176 of file if_spi.h.

#define IF_SPI_HISM_RX_UPLOAD_RDY   (1<<1)

Definition at line 168 of file if_spi.h.

#define IF_SPI_HISM_TX_DOWNLOAD_RDY   (1<<0)

Definition at line 166 of file if_spi.h.

#define IF_SPI_HIST_CARD_EVENT   (1<<3)

Definition at line 148 of file if_spi.h.

#define IF_SPI_HIST_CMD_DOWNLOAD_RDY   (1<<2)

Definition at line 146 of file if_spi.h.

#define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW   (1<<10)

Definition at line 162 of file if_spi.h.

#define IF_SPI_HIST_CMD_UPLOAD_RDY   (1<<4)

Definition at line 150 of file if_spi.h.

#define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW   (1<<9)

Definition at line 160 of file if_spi.h.

#define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW   (1<<8)

Definition at line 158 of file if_spi.h.

#define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW   (1<<7)

Definition at line 156 of file if_spi.h.

#define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW   (1<<6)

Definition at line 154 of file if_spi.h.

#define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW   (1<<5)

Definition at line 152 of file if_spi.h.

#define IF_SPI_HIST_RX_UPLOAD_RDY   (1<<1)

Definition at line 144 of file if_spi.h.

#define IF_SPI_HIST_TX_DOWNLOAD_RDY   (1<<0)

Definition at line 142 of file if_spi.h.

#define IF_SPI_HOST_INT_CAUSE_REG   0x58 /* Host interrupt cause reg */

Definition at line 75 of file if_spi.h.

#define IF_SPI_HOST_INT_CTRL_REG   0x40 /* Host interrupt controller reg */

Definition at line 66 of file if_spi.h.

#define IF_SPI_HOST_INT_EVENT_MASK_REG   0x60 /* Host interrupt event mask */

Definition at line 77 of file if_spi.h.

#define IF_SPI_HOST_INT_RESET_SELECT_REG   0x68 /* Host interrupt reset select */

Definition at line 79 of file if_spi.h.

#define IF_SPI_HOST_INT_STATUS_MASK_REG   0x64 /* Host interrupt status mask */

Definition at line 78 of file if_spi.h.

#define IF_SPI_HOST_INT_STATUS_REG   0x5C /* Host interrupt status reg */

Definition at line 76 of file if_spi.h.

#define IF_SPI_IO_RDWRPORT_REG   0x0C /* Read/Write I/O port reg */

Definition at line 48 of file if_spi.h.

#define IF_SPI_IO_READBASE_REG   0x04 /* Read I/O base reg */

Definition at line 46 of file if_spi.h.

#define IF_SPI_IO_WRITEBASE_REG   0x08 /* Write I/O base reg */

Definition at line 47 of file if_spi.h.

#define IF_SPI_READ_OPERATION_MASK   0x0

Definition at line 41 of file if_spi.h.

#define IF_SPI_SCRATCH_1_REG   0x28 /* Scratch reg 1 */

Definition at line 58 of file if_spi.h.

#define IF_SPI_SCRATCH_2_REG   0x2C /* Scratch reg 2 */

Definition at line 59 of file if_spi.h.

#define IF_SPI_SCRATCH_3_REG   0x30 /* Scratch reg 3 */

Definition at line 60 of file if_spi.h.

#define IF_SPI_SCRATCH_4_REG   0x34 /* Scratch reg 4 */

Definition at line 61 of file if_spi.h.

#define IF_SPI_SPU_BUS_MODE_REG   0x70 /* SPU BUS mode reg */

Definition at line 82 of file if_spi.h.

#define IF_SPI_TX_FRAME_SEQ_NUM_REG   0x38 /* Tx frame sequence number reg */

Definition at line 63 of file if_spi.h.

#define IF_SPI_TX_FRAME_STATUS_REG   0x3C /* Tx frame status reg */

Definition at line 64 of file if_spi.h.

#define IF_SPI_WRITE_OPERATION_MASK   0x8000

Definition at line 42 of file if_spi.h.

#define IPFIELD_ALIGN_OFFSET   2

Definition at line 21 of file if_spi.h.

#define MAX_MAIN_FW_LOAD_CRC_ERR   10

Definition at line 28 of file if_spi.h.

#define SUCCESSFUL_FW_DOWNLOAD_MAGIC   0x88888888

Definition at line 37 of file if_spi.h.