r8a66597.h File Reference

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Data Structures
struct	r8a66597_platdata

Macros
#define	R8A66597_PLATDATA_XTAL_12MHZ   0x01
#define	R8A66597_PLATDATA_XTAL_24MHZ   0x02
#define	R8A66597_PLATDATA_XTAL_48MHZ   0x03
#define	SYSCFG0   0x00
#define	SYSCFG1   0x02
#define	SYSSTS0   0x04
#define	SYSSTS1   0x06
#define	DVSTCTR0   0x08
#define	DVSTCTR1   0x0A
#define	TESTMODE   0x0C
#define	PINCFG   0x0E
#define	DMA0CFG   0x10
#define	DMA1CFG   0x12
#define	CFIFO   0x14
#define	D0FIFO   0x18
#define	D1FIFO   0x1C
#define	CFIFOSEL   0x20
#define	CFIFOCTR   0x22
#define	CFIFOSIE   0x24
#define	D0FIFOSEL   0x28
#define	D0FIFOCTR   0x2A
#define	D1FIFOSEL   0x2C
#define	D1FIFOCTR   0x2E
#define	INTENB0   0x30
#define	INTENB1   0x32
#define	INTENB2   0x34
#define	BRDYENB   0x36
#define	NRDYENB   0x38
#define	BEMPENB   0x3A
#define	SOFCFG   0x3C
#define	INTSTS0   0x40
#define	INTSTS1   0x42
#define	INTSTS2   0x44
#define	BRDYSTS   0x46
#define	NRDYSTS   0x48
#define	BEMPSTS   0x4A
#define	FRMNUM   0x4C
#define	UFRMNUM   0x4E
#define	USBADDR   0x50
#define	USBREQ   0x54
#define	USBVAL   0x56
#define	USBINDX   0x58
#define	USBLENG   0x5A
#define	DCPCFG   0x5C
#define	DCPMAXP   0x5E
#define	DCPCTR   0x60
#define	PIPESEL   0x64
#define	PIPECFG   0x68
#define	PIPEBUF   0x6A
#define	PIPEMAXP   0x6C
#define	PIPEPERI   0x6E
#define	PIPE1CTR   0x70
#define	PIPE2CTR   0x72
#define	PIPE3CTR   0x74
#define	PIPE4CTR   0x76
#define	PIPE5CTR   0x78
#define	PIPE6CTR   0x7A
#define	PIPE7CTR   0x7C
#define	PIPE8CTR   0x7E
#define	PIPE9CTR   0x80
#define	PIPE1TRE   0x90
#define	PIPE1TRN   0x92
#define	PIPE2TRE   0x94
#define	PIPE2TRN   0x96
#define	PIPE3TRE   0x98
#define	PIPE3TRN   0x9A
#define	PIPE4TRE   0x9C
#define	PIPE4TRN   0x9E
#define	PIPE5TRE   0xA0
#define	PIPE5TRN   0xA2
#define	DEVADD0   0xD0
#define	DEVADD1   0xD2
#define	DEVADD2   0xD4
#define	DEVADD3   0xD6
#define	DEVADD4   0xD8
#define	DEVADD5   0xDA
#define	DEVADD6   0xDC
#define	DEVADD7   0xDE
#define	DEVADD8   0xE0
#define	DEVADD9   0xE2
#define	DEVADDA   0xE4
#define	XTAL   0xC000 /* b15-14: Crystal selection */
#define	XTAL48   0x8000 /* 48MHz */
#define	XTAL24   0x4000 /* 24MHz */
#define	XTAL12   0x0000 /* 12MHz */
#define	XCKE   0x2000 /* b13: External clock enable */
#define	PLLC   0x0800 /* b11: PLL control */
#define	SCKE   0x0400 /* b10: USB clock enable */
#define	PCSDIS   0x0200 /* b9: not CS wakeup */
#define	LPSME   0x0100 /* b8: Low power sleep mode */
#define	HSE   0x0080 /* b7: Hi-speed enable */
#define	DCFM   0x0040 /* b6: Controller function select */
#define	DRPD   0x0020 /* b5: D+/- pull down control */
#define	DPRPU   0x0010 /* b4: D+ pull up control */
#define	USBE   0x0001 /* b0: USB module operation enable */
#define	OVCBIT   0x8000 /* b15-14: Over-current bit */
#define	OVCMON   0xC000 /* b15-14: Over-current monitor */
#define	SOFEA   0x0020 /* b5: SOF monitor */
#define	IDMON   0x0004 /* b3: ID-pin monitor */
#define	LNST   0x0003 /* b1-0: D+, D- line status */
#define	SE1   0x0003 /* SE1 */
#define	FS_KSTS   0x0002 /* Full-Speed K State */
#define	FS_JSTS   0x0001 /* Full-Speed J State */
#define	LS_JSTS   0x0002 /* Low-Speed J State */
#define	LS_KSTS   0x0001 /* Low-Speed K State */
#define	SE0   0x0000 /* SE0 */
#define	EXTLP0   0x0400 /* b10: External port */
#define	VBOUT   0x0200 /* b9: VBUS output */
#define	WKUP   0x0100 /* b8: Remote wakeup */
#define	RWUPE   0x0080 /* b7: Remote wakeup sense */
#define	USBRST   0x0040 /* b6: USB reset enable */
#define	RESUME   0x0020 /* b5: Resume enable */
#define	UACT   0x0010 /* b4: USB bus enable */
#define	RHST   0x0007 /* b1-0: Reset handshake status */
#define	HSPROC   0x0004 /* HS handshake is processing */
#define	HSMODE   0x0003 /* Hi-Speed mode */
#define	FSMODE   0x0002 /* Full-Speed mode */
#define	LSMODE   0x0001 /* Low-Speed mode */
#define	UNDECID   0x0000 /* Undecided */
#define	UTST   0x000F /* b3-0: Test select */
#define	H_TST_PACKET   0x000C /* HOST TEST Packet */
#define	H_TST_SE0_NAK   0x000B /* HOST TEST SE0 NAK */
#define	H_TST_K   0x000A /* HOST TEST K */
#define	H_TST_J   0x0009 /* HOST TEST J */
#define	H_TST_NORMAL   0x0000 /* HOST Normal Mode */
#define	P_TST_PACKET   0x0004 /* PERI TEST Packet */
#define	P_TST_SE0_NAK   0x0003 /* PERI TEST SE0 NAK */
#define	P_TST_K   0x0002 /* PERI TEST K */
#define	P_TST_J   0x0001 /* PERI TEST J */
#define	P_TST_NORMAL   0x0000 /* PERI Normal Mode */
#define	LDRV   0x8000 /* b15: Drive Current Adjust */
#define	VIF1   0x0000 /* VIF = 1.8V */
#define	VIF3   0x8000 /* VIF = 3.3V */
#define	INTA   0x0001 /* b1: USB INT-pin active */
#define	DREQA   0x4000 /* b14: Dreq active select */
#define	BURST   0x2000 /* b13: Burst mode */
#define	DACKA   0x0400 /* b10: Dack active select */
#define	DFORM   0x0380 /* b9-7: DMA mode select */
#define	CPU_ADR_RD_WR   0x0000 /* Address + RD/WR mode (CPU bus) */
#define	CPU_DACK_RD_WR   0x0100 /* DACK + RD/WR mode (CPU bus) */
#define	CPU_DACK_ONLY   0x0180 /* DACK only mode (CPU bus) */
#define	SPLIT_DACK_ONLY   0x0200 /* DACK only mode (SPLIT bus) */
#define	DENDA   0x0040 /* b6: Dend active select */
#define	PKTM   0x0020 /* b5: Packet mode */
#define	DENDE   0x0010 /* b4: Dend enable */
#define	OBUS   0x0004 /* b2: OUTbus mode */
#define	RCNT   0x8000 /* b15: Read count mode */
#define	REW   0x4000 /* b14: Buffer rewind */
#define	DCLRM   0x2000 /* b13: DMA buffer clear mode */
#define	DREQE   0x1000 /* b12: DREQ output enable */
#define	MBW_8   0x0000 /* 8bit */
#define	MBW_16   0x0400 /* 16bit */
#define	MBW_32   0x0800 /* 32bit */
#define	BIGEND   0x0100 /* b8: Big endian mode */
#define	BYTE_LITTLE   0x0000 /* little dendian */
#define	BYTE_BIG   0x0100 /* big endifan */
#define	ISEL   0x0020 /* b5: DCP FIFO port direction select */
#define	CURPIPE   0x000F /* b2-0: PIPE select */
#define	BVAL   0x8000 /* b15: Buffer valid flag */
#define	BCLR   0x4000 /* b14: Buffer clear */
#define	FRDY   0x2000 /* b13: FIFO ready */
#define	DTLN   0x0FFF /* b11-0: FIFO received data length */
#define	VBSE   0x8000 /* b15: VBUS interrupt */
#define	RSME   0x4000 /* b14: Resume interrupt */
#define	SOFE   0x2000 /* b13: Frame update interrupt */
#define	DVSE   0x1000 /* b12: Device state transition interrupt */
#define	CTRE   0x0800 /* b11: Control transfer stage transition interrupt */
#define	BEMPE   0x0400 /* b10: Buffer empty interrupt */
#define	NRDYE   0x0200 /* b9: Buffer not ready interrupt */
#define	BRDYE   0x0100 /* b8: Buffer ready interrupt */
#define	OVRCRE   0x8000 /* b15: Over-current interrupt */
#define	BCHGE   0x4000 /* b14: USB us chenge interrupt */
#define	DTCHE   0x1000 /* b12: Detach sense interrupt */
#define	ATTCHE   0x0800 /* b11: Attach sense interrupt */
#define	EOFERRE   0x0040 /* b6: EOF error interrupt */
#define	SIGNE   0x0020 /* b5: SETUP IGNORE interrupt */
#define	SACKE   0x0010 /* b4: SETUP ACK interrupt */
#define	BRDY9   0x0200 /* b9: PIPE9 */
#define	BRDY8   0x0100 /* b8: PIPE8 */
#define	BRDY7   0x0080 /* b7: PIPE7 */
#define	BRDY6   0x0040 /* b6: PIPE6 */
#define	BRDY5   0x0020 /* b5: PIPE5 */
#define	BRDY4   0x0010 /* b4: PIPE4 */
#define	BRDY3   0x0008 /* b3: PIPE3 */
#define	BRDY2   0x0004 /* b2: PIPE2 */
#define	BRDY1   0x0002 /* b1: PIPE1 */
#define	BRDY0   0x0001 /* b1: PIPE0 */
#define	NRDY9   0x0200 /* b9: PIPE9 */
#define	NRDY8   0x0100 /* b8: PIPE8 */
#define	NRDY7   0x0080 /* b7: PIPE7 */
#define	NRDY6   0x0040 /* b6: PIPE6 */
#define	NRDY5   0x0020 /* b5: PIPE5 */
#define	NRDY4   0x0010 /* b4: PIPE4 */
#define	NRDY3   0x0008 /* b3: PIPE3 */
#define	NRDY2   0x0004 /* b2: PIPE2 */
#define	NRDY1   0x0002 /* b1: PIPE1 */
#define	NRDY0   0x0001 /* b1: PIPE0 */
#define	BEMP9   0x0200 /* b9: PIPE9 */
#define	BEMP8   0x0100 /* b8: PIPE8 */
#define	BEMP7   0x0080 /* b7: PIPE7 */
#define	BEMP6   0x0040 /* b6: PIPE6 */
#define	BEMP5   0x0020 /* b5: PIPE5 */
#define	BEMP4   0x0010 /* b4: PIPE4 */
#define	BEMP3   0x0008 /* b3: PIPE3 */
#define	BEMP2   0x0004 /* b2: PIPE2 */
#define	BEMP1   0x0002 /* b1: PIPE1 */
#define	BEMP0   0x0001 /* b0: PIPE0 */
#define	TRNENSEL   0x0100 /* b8: Select transaction enable period */
#define	BRDYM   0x0040 /* b6: BRDY clear timing */
#define	INTL   0x0020 /* b5: Interrupt sense select */
#define	EDGESTS   0x0010 /* b4: */
#define	SOFMODE   0x000C /* b3-2: SOF pin select */
#define	SOF_125US   0x0008 /* SOF OUT 125us Frame Signal */
#define	SOF_1MS   0x0004 /* SOF OUT 1ms Frame Signal */
#define	SOF_DISABLE   0x0000 /* SOF OUT Disable */
#define	VBINT   0x8000 /* b15: VBUS interrupt */
#define	RESM   0x4000 /* b14: Resume interrupt */
#define	SOFR   0x2000 /* b13: SOF frame update interrupt */
#define	DVST   0x1000 /* b12: Device state transition interrupt */
#define	CTRT   0x0800 /* b11: Control transfer stage transition interrupt */
#define	BEMP   0x0400 /* b10: Buffer empty interrupt */
#define	NRDY   0x0200 /* b9: Buffer not ready interrupt */
#define	BRDY   0x0100 /* b8: Buffer ready interrupt */
#define	VBSTS   0x0080 /* b7: VBUS input port */
#define	DVSQ   0x0070 /* b6-4: Device state */
#define	DS_SPD_CNFG   0x0070 /* Suspend Configured */
#define	DS_SPD_ADDR   0x0060 /* Suspend Address */
#define	DS_SPD_DFLT   0x0050 /* Suspend Default */
#define	DS_SPD_POWR   0x0040 /* Suspend Powered */
#define	DS_SUSP   0x0040 /* Suspend */
#define	DS_CNFG   0x0030 /* Configured */
#define	DS_ADDS   0x0020 /* Address */
#define	DS_DFLT   0x0010 /* Default */
#define	DS_POWR   0x0000 /* Powered */
#define	DVSQS   0x0030 /* b5-4: Device state */
#define	VALID   0x0008 /* b3: Setup packet detected flag */
#define	CTSQ   0x0007 /* b2-0: Control transfer stage */
#define	CS_SQER   0x0006 /* Sequence error */
#define	CS_WRND   0x0005 /* Control write nodata status stage */
#define	CS_WRSS   0x0004 /* Control write status stage */
#define	CS_WRDS   0x0003 /* Control write data stage */
#define	CS_RDSS   0x0002 /* Control read status stage */
#define	CS_RDDS   0x0001 /* Control read data stage */
#define	CS_IDST   0x0000 /* Idle or setup stage */
#define	OVRCR   0x8000 /* b15: Over-current interrupt */
#define	BCHG   0x4000 /* b14: USB bus chenge interrupt */
#define	DTCH   0x1000 /* b12: Detach sense interrupt */
#define	ATTCH   0x0800 /* b11: Attach sense interrupt */
#define	EOFERR   0x0040 /* b6: EOF-error interrupt */
#define	SIGN   0x0020 /* b5: Setup ignore interrupt */
#define	SACK   0x0010 /* b4: Setup acknowledge interrupt */
#define	OVRN   0x8000 /* b15: Overrun error */
#define	CRCE   0x4000 /* b14: Received data error */
#define	FRNM   0x07FF /* b10-0: Frame number */
#define	UFRNM   0x0007 /* b2-0: Micro frame number */
#define	DEVSEL   0xF000 /* b15-14: Device address select */
#define	MAXP   0x007F /* b6-0: Maxpacket size of default control pipe */
#define	BSTS   0x8000 /* b15: Buffer status */
#define	SUREQ   0x4000 /* b14: Send USB request */
#define	CSCLR   0x2000 /* b13: complete-split status clear */
#define	CSSTS   0x1000 /* b12: complete-split status */
#define	SUREQCLR   0x0800 /* b11: stop setup request */
#define	SQCLR   0x0100 /* b8: Sequence toggle bit clear */
#define	SQSET   0x0080 /* b7: Sequence toggle bit set */
#define	SQMON   0x0040 /* b6: Sequence toggle bit monitor */
#define	PBUSY   0x0020 /* b5: pipe busy */
#define	PINGE   0x0010 /* b4: ping enable */
#define	CCPL   0x0004 /* b2: Enable control transfer complete */
#define	PID   0x0003 /* b1-0: Response PID */
#define	PID_STALL11   0x0003 /* STALL */
#define	PID_STALL   0x0002 /* STALL */
#define	PID_BUF   0x0001 /* BUF */
#define	PID_NAK   0x0000 /* NAK */
#define	PIPENM   0x0007 /* b2-0: Pipe select */
#define	R8A66597_TYP   0xC000 /* b15-14: Transfer type */
#define	R8A66597_ISO   0xC000 /* Isochronous */
#define	R8A66597_INT   0x8000 /* Interrupt */
#define	R8A66597_BULK   0x4000 /* Bulk */
#define	R8A66597_BFRE   0x0400 /* b10: Buffer ready interrupt mode select */
#define	R8A66597_DBLB   0x0200 /* b9: Double buffer mode select */
#define	R8A66597_CNTMD   0x0100 /* b8: Continuous transfer mode select */
#define	R8A66597_SHTNAK   0x0080 /* b7: Transfer end NAK */
#define	R8A66597_DIR   0x0010 /* b4: Transfer direction select */
#define	R8A66597_EPNUM   0x000F /* b3-0: Eendpoint number select */
#define	BUFSIZE   0x7C00 /* b14-10: Pipe buffer size */
#define	BUFNMB   0x007F /* b6-0: Pipe buffer number */
#define	PIPE0BUF   256
#define	PIPExBUF   64
#define	MXPS   0x07FF /* b10-0: Maxpacket size */
#define	IFIS   0x1000 /* b12: Isochronous in-buffer flush mode select */
#define	IITV   0x0007 /* b2-0: Isochronous interval */
#define	BSTS   0x8000 /* b15: Buffer status */
#define	INBUFM   0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
#define	CSCLR   0x2000 /* b13: complete-split status clear */
#define	CSSTS   0x1000 /* b12: complete-split status */
#define	ATREPM   0x0400 /* b10: Auto repeat mode */
#define	ACLRM   0x0200 /* b9: Out buffer auto clear mode */
#define	SQCLR   0x0100 /* b8: Sequence toggle bit clear */
#define	SQSET   0x0080 /* b7: Sequence toggle bit set */
#define	SQMON   0x0040 /* b6: Sequence toggle bit monitor */
#define	PBUSY   0x0020 /* b5: pipe busy */
#define	PID   0x0003 /* b1-0: Response PID */
#define	TRENB   0x0200 /* b9: Transaction counter enable */
#define	TRCLR   0x0100 /* b8: Transaction counter clear */
#define	TRNCNT   0xFFFF /* b15-0: Transaction counter */
#define	UPPHUB   0x7800
#define	HUBPORT   0x0700
#define	USBSPD   0x00C0
#define	RTPORT   0x0001
#define	CH0CFG   0x00
#define	CH1CFG   0x04
#define	CH0BA   0x10
#define	CH1BA   0x14
#define	CH0BBC   0x18
#define	CH1BBC   0x1C
#define	CH0CA   0x20
#define	CH1CA   0x24
#define	CH0CBC   0x28
#define	CH1CBC   0x2C
#define	CH0DEN   0x30
#define	CH1DEN   0x34
#define	DSTSCLR   0x38
#define	DBUFCTRL   0x3C
#define	DINTCTRL   0x40
#define	DINTSTS   0x44
#define	DINTSTSCLR   0x48
#define	CH0SHCTRL   0x50
#define	CH1SHCTRL   0x54
#define	SENDBUFM   0x1000 /* b12: Transmit Buffer Mode */
#define	RCVENDM   0x0100 /* b8: Receive Data Transfer End Mode */
#define	LBA_WAIT   0x0030 /* b5-4: Local Bus Access Wait */
#define	DEN   0x0001 /* b1: DMA Transfer Enable */
#define	CH1STCLR   0x0002 /* b2: Ch1 DMA Status Clear */
#define	CH0STCLR   0x0001 /* b1: Ch0 DMA Status Clear */
#define	CH1BUFW   0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
#define	CH0BUFW   0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
#define	CH1BUFS   0x0002 /* b2: Ch1 DMA Buffer Data Status */
#define	CH0BUFS   0x0001 /* b1: Ch0 DMA Buffer Data Status */
#define	CH1ERRE   0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
#define	CH0ERRE   0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
#define	CH1ENDE   0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
#define	CH0ENDE   0x0001 /* b1: Ch0 DMA Transfer End Int Enable */
#define	CH1ERRS   0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */
#define	CH0ERRS   0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */
#define	CH1ENDS   0x0002 /* b2: Ch1 DMA Transfer End Int Status */
#define	CH0ENDS   0x0001 /* b1: Ch0 DMA Transfer End Int Status */
#define	CH1ERRC   0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */
#define	CH0ERRC   0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */
#define	CH1ENDC   0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */
#define	CH0ENDC   0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */

Macro Definition Documentation

#define ACLRM   0x0200 /* b9: Out buffer auto clear mode */

Definition at line 403 of file r8a66597.h.

#define ATREPM   0x0400 /* b10: Auto repeat mode */

Definition at line 402 of file r8a66597.h.

#define ATTCH   0x0800 /* b11: Attach sense interrupt */

Definition at line 333 of file r8a66597.h.

#define ATTCHE   0x0800 /* b11: Attach sense interrupt */

Definition at line 247 of file r8a66597.h.

#define BCHG   0x4000 /* b14: USB bus chenge interrupt */

Definition at line 331 of file r8a66597.h.

#define BCHGE   0x4000 /* b14: USB us chenge interrupt */

Definition at line 245 of file r8a66597.h.

#define BCLR   0x4000 /* b14: Buffer clear */

Definition at line 229 of file r8a66597.h.

#define BEMP   0x0400 /* b10: Buffer empty interrupt */

Definition at line 304 of file r8a66597.h.

#define BEMP0   0x0001 /* b0: PIPE0 */

Definition at line 286 of file r8a66597.h.

#define BEMP1   0x0002 /* b1: PIPE1 */

Definition at line 285 of file r8a66597.h.

#define BEMP2   0x0004 /* b2: PIPE2 */

Definition at line 284 of file r8a66597.h.

#define BEMP3   0x0008 /* b3: PIPE3 */

Definition at line 283 of file r8a66597.h.

#define BEMP4   0x0010 /* b4: PIPE4 */

Definition at line 282 of file r8a66597.h.

#define BEMP5   0x0020 /* b5: PIPE5 */

Definition at line 281 of file r8a66597.h.

#define BEMP6   0x0040 /* b6: PIPE6 */

Definition at line 280 of file r8a66597.h.

#define BEMP7   0x0080 /* b7: PIPE7 */

Definition at line 279 of file r8a66597.h.

#define BEMP8   0x0100 /* b8: PIPE8 */

Definition at line 278 of file r8a66597.h.

#define BEMP9   0x0200 /* b9: PIPE9 */

Definition at line 277 of file r8a66597.h.

#define BEMPE   0x0400 /* b10: Buffer empty interrupt */

Definition at line 239 of file r8a66597.h.

#define BEMPENB   0x3A

Definition at line 82 of file r8a66597.h.

#define BEMPSTS   0x4A

Definition at line 89 of file r8a66597.h.

#define BIGEND   0x0100 /* b8: Big endian mode */

Definition at line 221 of file r8a66597.h.

#define BRDY   0x0100 /* b8: Buffer ready interrupt */

Definition at line 306 of file r8a66597.h.

#define BRDY0   0x0001 /* b1: PIPE0 */

Definition at line 262 of file r8a66597.h.

#define BRDY1   0x0002 /* b1: PIPE1 */

Definition at line 261 of file r8a66597.h.

#define BRDY2   0x0004 /* b2: PIPE2 */

Definition at line 260 of file r8a66597.h.

#define BRDY3   0x0008 /* b3: PIPE3 */

Definition at line 259 of file r8a66597.h.

#define BRDY4   0x0010 /* b4: PIPE4 */

Definition at line 258 of file r8a66597.h.

#define BRDY5   0x0020 /* b5: PIPE5 */

Definition at line 257 of file r8a66597.h.

#define BRDY6   0x0040 /* b6: PIPE6 */

Definition at line 256 of file r8a66597.h.

#define BRDY7   0x0080 /* b7: PIPE7 */

Definition at line 255 of file r8a66597.h.

#define BRDY8   0x0100 /* b8: PIPE8 */

Definition at line 254 of file r8a66597.h.

#define BRDY9   0x0200 /* b9: PIPE9 */

Definition at line 253 of file r8a66597.h.

#define BRDYE   0x0100 /* b8: Buffer ready interrupt */

Definition at line 241 of file r8a66597.h.

#define BRDYENB   0x36

Definition at line 80 of file r8a66597.h.

#define BRDYM   0x0040 /* b6: BRDY clear timing */

Definition at line 290 of file r8a66597.h.

#define BRDYSTS   0x46

Definition at line 87 of file r8a66597.h.

#define BSTS   0x8000 /* b15: Buffer status */

Definition at line 398 of file r8a66597.h.

#define BSTS   0x8000 /* b15: Buffer status */

Definition at line 398 of file r8a66597.h.

#define BUFNMB   0x007F /* b6-0: Pipe buffer number */

Definition at line 386 of file r8a66597.h.

#define BUFSIZE   0x7C00 /* b14-10: Pipe buffer size */

Definition at line 385 of file r8a66597.h.

#define BURST   0x2000 /* b13: Burst mode */

Definition at line 201 of file r8a66597.h.

#define BVAL   0x8000 /* b15: Buffer valid flag */

Definition at line 228 of file r8a66597.h.

#define BYTE_BIG   0x0100 /* big endifan */

Definition at line 223 of file r8a66597.h.

#define BYTE_LITTLE   0x0000 /* little dendian */

Definition at line 222 of file r8a66597.h.

#define CCPL   0x0004 /* b2: Enable control transfer complete */

Definition at line 362 of file r8a66597.h.

#define CFIFO   0x14

Definition at line 67 of file r8a66597.h.

#define CFIFOCTR   0x22

Definition at line 71 of file r8a66597.h.

#define CFIFOSEL   0x20

Definition at line 70 of file r8a66597.h.

#define CFIFOSIE   0x24

Definition at line 72 of file r8a66597.h.

#define CH0BA   0x10

Definition at line 426 of file r8a66597.h.

#define CH0BBC   0x18

Definition at line 428 of file r8a66597.h.

#define CH0BUFS   0x0001 /* b1: Ch0 DMA Buffer Data Status */

Definition at line 460 of file r8a66597.h.

#define CH0BUFW   0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */

Definition at line 458 of file r8a66597.h.

#define CH0CA   0x20

Definition at line 430 of file r8a66597.h.

#define CH0CBC   0x28

Definition at line 432 of file r8a66597.h.

#define CH0CFG   0x00

Definition at line 424 of file r8a66597.h.

#define CH0DEN   0x30

Definition at line 434 of file r8a66597.h.

#define CH0ENDC   0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */

Definition at line 478 of file r8a66597.h.

#define CH0ENDE   0x0001 /* b1: Ch0 DMA Transfer End Int Enable */

Definition at line 466 of file r8a66597.h.

#define CH0ENDS   0x0001 /* b1: Ch0 DMA Transfer End Int Status */

Definition at line 472 of file r8a66597.h.

#define CH0ERRC   0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */

Definition at line 476 of file r8a66597.h.

#define CH0ERRE   0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */

Definition at line 464 of file r8a66597.h.

#define CH0ERRS   0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */

Definition at line 470 of file r8a66597.h.

#define CH0SHCTRL   0x50

Definition at line 441 of file r8a66597.h.

#define CH0STCLR   0x0001 /* b1: Ch0 DMA Status Clear */

Definition at line 454 of file r8a66597.h.

#define CH1BA   0x14

Definition at line 427 of file r8a66597.h.

#define CH1BBC   0x1C

Definition at line 429 of file r8a66597.h.

#define CH1BUFS   0x0002 /* b2: Ch1 DMA Buffer Data Status */

Definition at line 459 of file r8a66597.h.

#define CH1BUFW   0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */

Definition at line 457 of file r8a66597.h.

#define CH1CA   0x24

Definition at line 431 of file r8a66597.h.

#define CH1CBC   0x2C

Definition at line 433 of file r8a66597.h.

#define CH1CFG   0x04

Definition at line 425 of file r8a66597.h.

#define CH1DEN   0x34

Definition at line 435 of file r8a66597.h.

#define CH1ENDC   0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */

Definition at line 477 of file r8a66597.h.

#define CH1ENDE   0x0002 /* b2: Ch1 DMA Transfer End Int Enable */

Definition at line 465 of file r8a66597.h.

#define CH1ENDS   0x0002 /* b2: Ch1 DMA Transfer End Int Status */

Definition at line 471 of file r8a66597.h.

#define CH1ERRC   0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */

Definition at line 475 of file r8a66597.h.

#define CH1ERRE   0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */

Definition at line 463 of file r8a66597.h.

#define CH1ERRS   0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */

Definition at line 469 of file r8a66597.h.

#define CH1SHCTRL   0x54

Definition at line 442 of file r8a66597.h.

#define CH1STCLR   0x0002 /* b2: Ch1 DMA Status Clear */

Definition at line 453 of file r8a66597.h.

#define CPU_ADR_RD_WR   0x0000 /* Address + RD/WR mode (CPU bus) */

Definition at line 204 of file r8a66597.h.

#define CPU_DACK_ONLY   0x0180 /* DACK only mode (CPU bus) */

Definition at line 206 of file r8a66597.h.

#define CPU_DACK_RD_WR   0x0100 /* DACK + RD/WR mode (CPU bus) */

Definition at line 205 of file r8a66597.h.

#define CRCE   0x4000 /* b14: Received data error */

Definition at line 340 of file r8a66597.h.

#define CS_IDST   0x0000 /* Idle or setup stage */

Definition at line 327 of file r8a66597.h.

#define CS_RDDS   0x0001 /* Control read data stage */

Definition at line 326 of file r8a66597.h.

#define CS_RDSS   0x0002 /* Control read status stage */

Definition at line 325 of file r8a66597.h.

#define CS_SQER   0x0006 /* Sequence error */

Definition at line 321 of file r8a66597.h.

#define CS_WRDS   0x0003 /* Control write data stage */

Definition at line 324 of file r8a66597.h.

#define CS_WRND   0x0005 /* Control write nodata status stage */

Definition at line 322 of file r8a66597.h.

#define CS_WRSS   0x0004 /* Control write status stage */

Definition at line 323 of file r8a66597.h.

#define CSCLR   0x2000 /* b13: complete-split status clear */

Definition at line 400 of file r8a66597.h.

#define CSCLR   0x2000 /* b13: complete-split status clear */

Definition at line 400 of file r8a66597.h.

#define CSSTS   0x1000 /* b12: complete-split status */

Definition at line 401 of file r8a66597.h.

#define CSSTS   0x1000 /* b12: complete-split status */

Definition at line 401 of file r8a66597.h.

#define CTRE   0x0800 /* b11: Control transfer stage transition interrupt */

Definition at line 238 of file r8a66597.h.

#define CTRT   0x0800 /* b11: Control transfer stage transition interrupt */

Definition at line 303 of file r8a66597.h.

#define CTSQ   0x0007 /* b2-0: Control transfer stage */

Definition at line 320 of file r8a66597.h.

#define CURPIPE   0x000F /* b2-0: PIPE select */

Definition at line 225 of file r8a66597.h.

#define D0FIFO   0x18

Definition at line 68 of file r8a66597.h.

#define D0FIFOCTR   0x2A

Definition at line 74 of file r8a66597.h.

#define D0FIFOSEL   0x28

Definition at line 73 of file r8a66597.h.

#define D1FIFO   0x1C

Definition at line 69 of file r8a66597.h.

#define D1FIFOCTR   0x2E

Definition at line 76 of file r8a66597.h.

#define D1FIFOSEL   0x2C

Definition at line 75 of file r8a66597.h.

#define DACKA   0x0400 /* b10: Dack active select */

Definition at line 202 of file r8a66597.h.

#define DBUFCTRL   0x3C

Definition at line 437 of file r8a66597.h.

#define DCFM   0x0040 /* b6: Controller function select */

Definition at line 147 of file r8a66597.h.

#define DCLRM   0x2000 /* b13: DMA buffer clear mode */

Definition at line 216 of file r8a66597.h.

#define DCPCFG   0x5C

Definition at line 97 of file r8a66597.h.

#define DCPCTR   0x60

Definition at line 99 of file r8a66597.h.

#define DCPMAXP   0x5E

Definition at line 98 of file r8a66597.h.

#define DEN   0x0001 /* b1: DMA Transfer Enable */

Definition at line 450 of file r8a66597.h.

#define DENDA   0x0040 /* b6: Dend active select */

Definition at line 208 of file r8a66597.h.

#define DENDE   0x0010 /* b4: Dend enable */

Definition at line 210 of file r8a66597.h.

#define DEVADD0   0xD0

Definition at line 124 of file r8a66597.h.

#define DEVADD1   0xD2

Definition at line 125 of file r8a66597.h.

#define DEVADD2   0xD4

Definition at line 126 of file r8a66597.h.

#define DEVADD3   0xD6

Definition at line 127 of file r8a66597.h.

#define DEVADD4   0xD8

Definition at line 128 of file r8a66597.h.

#define DEVADD5   0xDA

Definition at line 129 of file r8a66597.h.

#define DEVADD6   0xDC

Definition at line 130 of file r8a66597.h.

#define DEVADD7   0xDE

Definition at line 131 of file r8a66597.h.

#define DEVADD8   0xE0

Definition at line 132 of file r8a66597.h.

#define DEVADD9   0xE2

Definition at line 133 of file r8a66597.h.

#define DEVADDA   0xE4

Definition at line 134 of file r8a66597.h.

#define DEVSEL   0xF000 /* b15-14: Device address select */

Definition at line 348 of file r8a66597.h.

#define DFORM   0x0380 /* b9-7: DMA mode select */

Definition at line 203 of file r8a66597.h.

#define DINTCTRL   0x40

Definition at line 438 of file r8a66597.h.

#define DINTSTS   0x44

Definition at line 439 of file r8a66597.h.

#define DINTSTSCLR   0x48

Definition at line 440 of file r8a66597.h.

#define DMA0CFG   0x10

Definition at line 65 of file r8a66597.h.

#define DMA1CFG   0x12

Definition at line 66 of file r8a66597.h.

#define DPRPU   0x0010 /* b4: D+ pull up control */

Definition at line 149 of file r8a66597.h.

#define DREQA   0x4000 /* b14: Dreq active select */

Definition at line 200 of file r8a66597.h.

#define DREQE   0x1000 /* b12: DREQ output enable */

Definition at line 217 of file r8a66597.h.

#define DRPD   0x0020 /* b5: D+/- pull down control */

Definition at line 148 of file r8a66597.h.

#define DS_ADDS   0x0020 /* Address */

Definition at line 315 of file r8a66597.h.

#define DS_CNFG   0x0030 /* Configured */

Definition at line 314 of file r8a66597.h.

#define DS_DFLT   0x0010 /* Default */

Definition at line 316 of file r8a66597.h.

#define DS_POWR   0x0000 /* Powered */

Definition at line 317 of file r8a66597.h.

#define DS_SPD_ADDR   0x0060 /* Suspend Address */

Definition at line 310 of file r8a66597.h.

#define DS_SPD_CNFG   0x0070 /* Suspend Configured */

Definition at line 309 of file r8a66597.h.

#define DS_SPD_DFLT   0x0050 /* Suspend Default */

Definition at line 311 of file r8a66597.h.

#define DS_SPD_POWR   0x0040 /* Suspend Powered */

Definition at line 312 of file r8a66597.h.

#define DS_SUSP   0x0040 /* Suspend */

Definition at line 313 of file r8a66597.h.

#define DSTSCLR   0x38

Definition at line 436 of file r8a66597.h.

#define DTCH   0x1000 /* b12: Detach sense interrupt */

Definition at line 332 of file r8a66597.h.

#define DTCHE   0x1000 /* b12: Detach sense interrupt */

Definition at line 246 of file r8a66597.h.

#define DTLN   0x0FFF /* b11-0: FIFO received data length */

Definition at line 231 of file r8a66597.h.

#define DVSE   0x1000 /* b12: Device state transition interrupt */

Definition at line 237 of file r8a66597.h.

#define DVSQ   0x0070 /* b6-4: Device state */

Definition at line 308 of file r8a66597.h.

#define DVSQS   0x0030 /* b5-4: Device state */

Definition at line 318 of file r8a66597.h.

#define DVST   0x1000 /* b12: Device state transition interrupt */

Definition at line 302 of file r8a66597.h.

#define DVSTCTR0   0x08

Definition at line 61 of file r8a66597.h.

#define DVSTCTR1   0x0A

Definition at line 62 of file r8a66597.h.

#define EDGESTS   0x0010 /* b4: */

Definition at line 292 of file r8a66597.h.

#define EOFERR   0x0040 /* b6: EOF-error interrupt */

Definition at line 334 of file r8a66597.h.

#define EOFERRE   0x0040 /* b6: EOF error interrupt */

Definition at line 248 of file r8a66597.h.

#define EXTLP0   0x0400 /* b10: External port */

Definition at line 166 of file r8a66597.h.

#define FRDY   0x2000 /* b13: FIFO ready */

Definition at line 230 of file r8a66597.h.

#define FRMNUM   0x4C

Definition at line 90 of file r8a66597.h.

#define FRNM   0x07FF /* b10-0: Frame number */

Definition at line 341 of file r8a66597.h.

#define FS_JSTS   0x0001 /* Full-Speed J State */

Definition at line 160 of file r8a66597.h.

#define FS_KSTS   0x0002 /* Full-Speed K State */

Definition at line 159 of file r8a66597.h.

#define FSMODE   0x0002 /* Full-Speed mode */

Definition at line 176 of file r8a66597.h.

#define H_TST_J   0x0009 /* HOST TEST J */

Definition at line 185 of file r8a66597.h.

#define H_TST_K   0x000A /* HOST TEST K */

Definition at line 184 of file r8a66597.h.

#define H_TST_NORMAL   0x0000 /* HOST Normal Mode */

Definition at line 186 of file r8a66597.h.

#define H_TST_PACKET   0x000C /* HOST TEST Packet */

Definition at line 182 of file r8a66597.h.

#define H_TST_SE0_NAK   0x000B /* HOST TEST SE0 NAK */

Definition at line 183 of file r8a66597.h.

#define HSE   0x0080 /* b7: Hi-speed enable */

Definition at line 146 of file r8a66597.h.

#define HSMODE   0x0003 /* Hi-Speed mode */

Definition at line 175 of file r8a66597.h.

#define HSPROC   0x0004 /* HS handshake is processing */

Definition at line 174 of file r8a66597.h.

#define HUBPORT   0x0700

Definition at line 419 of file r8a66597.h.

#define IDMON   0x0004 /* b3: ID-pin monitor */

Definition at line 156 of file r8a66597.h.

#define IFIS   0x1000 /* b12: Isochronous in-buffer flush mode select */

Definition at line 394 of file r8a66597.h.

#define IITV   0x0007 /* b2-0: Isochronous interval */

Definition at line 395 of file r8a66597.h.

#define INBUFM   0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */

Definition at line 399 of file r8a66597.h.

#define INTA   0x0001 /* b1: USB INT-pin active */

Definition at line 197 of file r8a66597.h.

#define INTENB0   0x30

Definition at line 77 of file r8a66597.h.

#define INTENB1   0x32

Definition at line 78 of file r8a66597.h.

#define INTENB2   0x34

Definition at line 79 of file r8a66597.h.

#define INTL   0x0020 /* b5: Interrupt sense select */

Definition at line 291 of file r8a66597.h.

#define INTSTS0   0x40

Definition at line 84 of file r8a66597.h.

#define INTSTS1   0x42

Definition at line 85 of file r8a66597.h.

#define INTSTS2   0x44

Definition at line 86 of file r8a66597.h.

#define ISEL   0x0020 /* b5: DCP FIFO port direction select */

Definition at line 224 of file r8a66597.h.

#define LBA_WAIT   0x0030 /* b5-4: Local Bus Access Wait */

Definition at line 447 of file r8a66597.h.

#define LDRV   0x8000 /* b15: Drive Current Adjust */

Definition at line 194 of file r8a66597.h.

#define LNST   0x0003 /* b1-0: D+, D- line status */

Definition at line 157 of file r8a66597.h.

#define LPSME   0x0100 /* b8: Low power sleep mode */

Definition at line 145 of file r8a66597.h.

#define LS_JSTS   0x0002 /* Low-Speed J State */

Definition at line 161 of file r8a66597.h.

#define LS_KSTS   0x0001 /* Low-Speed K State */

Definition at line 162 of file r8a66597.h.

#define LSMODE   0x0001 /* Low-Speed mode */

Definition at line 177 of file r8a66597.h.

#define MAXP   0x007F /* b6-0: Maxpacket size of default control pipe */

Definition at line 349 of file r8a66597.h.

#define MBW_16   0x0400 /* 16bit */

Definition at line 219 of file r8a66597.h.

#define MBW_32   0x0800 /* 32bit */

Definition at line 220 of file r8a66597.h.

#define MBW_8   0x0000 /* 8bit */

Definition at line 218 of file r8a66597.h.

#define MXPS   0x07FF /* b10-0: Maxpacket size */

Definition at line 391 of file r8a66597.h.

#define NRDY   0x0200 /* b9: Buffer not ready interrupt */

Definition at line 305 of file r8a66597.h.

#define NRDY0   0x0001 /* b1: PIPE0 */

Definition at line 274 of file r8a66597.h.

#define NRDY1   0x0002 /* b1: PIPE1 */

Definition at line 273 of file r8a66597.h.

#define NRDY2   0x0004 /* b2: PIPE2 */

Definition at line 272 of file r8a66597.h.

#define NRDY3   0x0008 /* b3: PIPE3 */

Definition at line 271 of file r8a66597.h.

#define NRDY4   0x0010 /* b4: PIPE4 */

Definition at line 270 of file r8a66597.h.

#define NRDY5   0x0020 /* b5: PIPE5 */

Definition at line 269 of file r8a66597.h.

#define NRDY6   0x0040 /* b6: PIPE6 */

Definition at line 268 of file r8a66597.h.

#define NRDY7   0x0080 /* b7: PIPE7 */

Definition at line 267 of file r8a66597.h.

#define NRDY8   0x0100 /* b8: PIPE8 */

Definition at line 266 of file r8a66597.h.

#define NRDY9   0x0200 /* b9: PIPE9 */

Definition at line 265 of file r8a66597.h.

#define NRDYE   0x0200 /* b9: Buffer not ready interrupt */

Definition at line 240 of file r8a66597.h.

#define NRDYENB   0x38

Definition at line 81 of file r8a66597.h.

#define NRDYSTS   0x48

Definition at line 88 of file r8a66597.h.

#define OBUS   0x0004 /* b2: OUTbus mode */

Definition at line 211 of file r8a66597.h.

#define OVCBIT   0x8000 /* b15-14: Over-current bit */

Definition at line 153 of file r8a66597.h.

#define OVCMON   0xC000 /* b15-14: Over-current monitor */

Definition at line 154 of file r8a66597.h.

#define OVRCR   0x8000 /* b15: Over-current interrupt */

Definition at line 330 of file r8a66597.h.

#define OVRCRE   0x8000 /* b15: Over-current interrupt */

Definition at line 244 of file r8a66597.h.

#define OVRN   0x8000 /* b15: Overrun error */

Definition at line 339 of file r8a66597.h.

#define P_TST_J   0x0001 /* PERI TEST J */

Definition at line 190 of file r8a66597.h.

#define P_TST_K   0x0002 /* PERI TEST K */

Definition at line 189 of file r8a66597.h.

#define P_TST_NORMAL   0x0000 /* PERI Normal Mode */

Definition at line 191 of file r8a66597.h.

#define P_TST_PACKET   0x0004 /* PERI TEST Packet */

Definition at line 187 of file r8a66597.h.

#define P_TST_SE0_NAK   0x0003 /* PERI TEST SE0 NAK */

Definition at line 188 of file r8a66597.h.

#define PBUSY   0x0020 /* b5: pipe busy */

Definition at line 407 of file r8a66597.h.

#define PBUSY   0x0020 /* b5: pipe busy */

Definition at line 407 of file r8a66597.h.

#define PCSDIS   0x0200 /* b9: not CS wakeup */

Definition at line 144 of file r8a66597.h.

#define PID   0x0003 /* b1-0: Response PID */

Definition at line 408 of file r8a66597.h.

#define PID   0x0003 /* b1-0: Response PID */

Definition at line 408 of file r8a66597.h.

#define PID_BUF   0x0001 /* BUF */

Definition at line 366 of file r8a66597.h.

#define PID_NAK   0x0000 /* NAK */

Definition at line 367 of file r8a66597.h.

#define PID_STALL   0x0002 /* STALL */

Definition at line 365 of file r8a66597.h.

#define PID_STALL11   0x0003 /* STALL */

Definition at line 364 of file r8a66597.h.

#define PINCFG   0x0E

Definition at line 64 of file r8a66597.h.

#define PINGE   0x0010 /* b4: ping enable */

Definition at line 361 of file r8a66597.h.

#define PIPE0BUF   256

Definition at line 387 of file r8a66597.h.

#define PIPE1CTR   0x70

Definition at line 105 of file r8a66597.h.

#define PIPE1TRE   0x90

Definition at line 114 of file r8a66597.h.

#define PIPE1TRN   0x92

Definition at line 115 of file r8a66597.h.

#define PIPE2CTR   0x72

Definition at line 106 of file r8a66597.h.

#define PIPE2TRE   0x94

Definition at line 116 of file r8a66597.h.

#define PIPE2TRN   0x96

Definition at line 117 of file r8a66597.h.

#define PIPE3CTR   0x74

Definition at line 107 of file r8a66597.h.

#define PIPE3TRE   0x98

Definition at line 118 of file r8a66597.h.

#define PIPE3TRN   0x9A

Definition at line 119 of file r8a66597.h.

#define PIPE4CTR   0x76

Definition at line 108 of file r8a66597.h.

#define PIPE4TRE   0x9C

Definition at line 120 of file r8a66597.h.

#define PIPE4TRN   0x9E

Definition at line 121 of file r8a66597.h.

#define PIPE5CTR   0x78

Definition at line 109 of file r8a66597.h.

#define PIPE5TRE   0xA0

Definition at line 122 of file r8a66597.h.

#define PIPE5TRN   0xA2

Definition at line 123 of file r8a66597.h.

#define PIPE6CTR   0x7A

Definition at line 110 of file r8a66597.h.

#define PIPE7CTR   0x7C

Definition at line 111 of file r8a66597.h.

#define PIPE8CTR   0x7E

Definition at line 112 of file r8a66597.h.

#define PIPE9CTR   0x80

Definition at line 113 of file r8a66597.h.

#define PIPEBUF   0x6A

Definition at line 102 of file r8a66597.h.

#define PIPECFG   0x68

Definition at line 101 of file r8a66597.h.

#define PIPEMAXP   0x6C

Definition at line 103 of file r8a66597.h.

#define PIPENM   0x0007 /* b2-0: Pipe select */

Definition at line 370 of file r8a66597.h.

#define PIPEPERI   0x6E

Definition at line 104 of file r8a66597.h.

#define PIPESEL   0x64

Definition at line 100 of file r8a66597.h.

#define PIPExBUF   64

Definition at line 388 of file r8a66597.h.

#define PKTM   0x0020 /* b5: Packet mode */

Definition at line 209 of file r8a66597.h.

#define PLLC   0x0800 /* b11: PLL control */

Definition at line 142 of file r8a66597.h.

#define R8A66597_BFRE   0x0400 /* b10: Buffer ready interrupt mode select */

Definition at line 377 of file r8a66597.h.

#define R8A66597_BULK   0x4000 /* Bulk */

Definition at line 376 of file r8a66597.h.

#define R8A66597_CNTMD   0x0100 /* b8: Continuous transfer mode select */

Definition at line 379 of file r8a66597.h.

#define R8A66597_DBLB   0x0200 /* b9: Double buffer mode select */

Definition at line 378 of file r8a66597.h.

#define R8A66597_DIR   0x0010 /* b4: Transfer direction select */

Definition at line 381 of file r8a66597.h.

#define R8A66597_EPNUM   0x000F /* b3-0: Eendpoint number select */

Definition at line 382 of file r8a66597.h.

#define R8A66597_INT   0x8000 /* Interrupt */

Definition at line 375 of file r8a66597.h.

#define R8A66597_ISO   0xC000 /* Isochronous */

Definition at line 374 of file r8a66597.h.

#define R8A66597_PLATDATA_XTAL_12MHZ   0x01

Definition at line 26 of file r8a66597.h.

#define R8A66597_PLATDATA_XTAL_24MHZ   0x02

Definition at line 27 of file r8a66597.h.

#define R8A66597_PLATDATA_XTAL_48MHZ   0x03

Definition at line 28 of file r8a66597.h.

#define R8A66597_SHTNAK   0x0080 /* b7: Transfer end NAK */

Definition at line 380 of file r8a66597.h.

#define R8A66597_TYP   0xC000 /* b15-14: Transfer type */

Definition at line 373 of file r8a66597.h.

#define RCNT   0x8000 /* b15: Read count mode */

Definition at line 214 of file r8a66597.h.

#define RCVENDM   0x0100 /* b8: Receive Data Transfer End Mode */

Definition at line 446 of file r8a66597.h.

#define RESM   0x4000 /* b14: Resume interrupt */

Definition at line 300 of file r8a66597.h.

#define RESUME   0x0020 /* b5: Resume enable */

Definition at line 171 of file r8a66597.h.

#define REW   0x4000 /* b14: Buffer rewind */

Definition at line 215 of file r8a66597.h.

#define RHST   0x0007 /* b1-0: Reset handshake status */

Definition at line 173 of file r8a66597.h.

#define RSME   0x4000 /* b14: Resume interrupt */

Definition at line 235 of file r8a66597.h.

#define RTPORT   0x0001

Definition at line 421 of file r8a66597.h.

#define RWUPE   0x0080 /* b7: Remote wakeup sense */

Definition at line 169 of file r8a66597.h.

#define SACK   0x0010 /* b4: Setup acknowledge interrupt */

Definition at line 336 of file r8a66597.h.

#define SACKE   0x0010 /* b4: SETUP ACK interrupt */

Definition at line 250 of file r8a66597.h.

#define SCKE   0x0400 /* b10: USB clock enable */

Definition at line 143 of file r8a66597.h.

#define SE0   0x0000 /* SE0 */

Definition at line 163 of file r8a66597.h.

#define SE1   0x0003 /* SE1 */

Definition at line 158 of file r8a66597.h.

#define SENDBUFM   0x1000 /* b12: Transmit Buffer Mode */

Definition at line 445 of file r8a66597.h.

#define SIGN   0x0020 /* b5: Setup ignore interrupt */

Definition at line 335 of file r8a66597.h.

#define SIGNE   0x0020 /* b5: SETUP IGNORE interrupt */

Definition at line 249 of file r8a66597.h.

#define SOF_125US   0x0008 /* SOF OUT 125us Frame Signal */

Definition at line 294 of file r8a66597.h.

#define SOF_1MS   0x0004 /* SOF OUT 1ms Frame Signal */

Definition at line 295 of file r8a66597.h.

#define SOF_DISABLE   0x0000 /* SOF OUT Disable */

Definition at line 296 of file r8a66597.h.

#define SOFCFG   0x3C

Definition at line 83 of file r8a66597.h.

#define SOFE   0x2000 /* b13: Frame update interrupt */

Definition at line 236 of file r8a66597.h.

#define SOFEA   0x0020 /* b5: SOF monitor */

Definition at line 155 of file r8a66597.h.

#define SOFMODE   0x000C /* b3-2: SOF pin select */

Definition at line 293 of file r8a66597.h.

#define SOFR   0x2000 /* b13: SOF frame update interrupt */

Definition at line 301 of file r8a66597.h.

#define SPLIT_DACK_ONLY   0x0200 /* DACK only mode (SPLIT bus) */

Definition at line 207 of file r8a66597.h.

#define SQCLR   0x0100 /* b8: Sequence toggle bit clear */

Definition at line 404 of file r8a66597.h.

#define SQCLR   0x0100 /* b8: Sequence toggle bit clear */

Definition at line 404 of file r8a66597.h.

#define SQMON   0x0040 /* b6: Sequence toggle bit monitor */

Definition at line 406 of file r8a66597.h.

#define SQMON   0x0040 /* b6: Sequence toggle bit monitor */

Definition at line 406 of file r8a66597.h.

#define SQSET   0x0080 /* b7: Sequence toggle bit set */

Definition at line 405 of file r8a66597.h.

#define SQSET   0x0080 /* b7: Sequence toggle bit set */

Definition at line 405 of file r8a66597.h.

#define SUREQ   0x4000 /* b14: Send USB request */

Definition at line 353 of file r8a66597.h.

#define SUREQCLR   0x0800 /* b11: stop setup request */

Definition at line 356 of file r8a66597.h.

#define SYSCFG0   0x00

Definition at line 57 of file r8a66597.h.

#define SYSCFG1   0x02

Definition at line 58 of file r8a66597.h.

#define SYSSTS0   0x04

Definition at line 59 of file r8a66597.h.

#define SYSSTS1   0x06

Definition at line 60 of file r8a66597.h.

#define TESTMODE   0x0C

Definition at line 63 of file r8a66597.h.

#define TRCLR   0x0100 /* b8: Transaction counter clear */

Definition at line 412 of file r8a66597.h.

#define TRENB   0x0200 /* b9: Transaction counter enable */

Definition at line 411 of file r8a66597.h.

#define TRNCNT   0xFFFF /* b15-0: Transaction counter */

Definition at line 415 of file r8a66597.h.

#define TRNENSEL   0x0100 /* b8: Select transaction enable period */

Definition at line 289 of file r8a66597.h.

#define UACT   0x0010 /* b4: USB bus enable */

Definition at line 172 of file r8a66597.h.

#define UFRMNUM   0x4E

Definition at line 91 of file r8a66597.h.

#define UFRNM   0x0007 /* b2-0: Micro frame number */

Definition at line 344 of file r8a66597.h.

#define UNDECID   0x0000 /* Undecided */

Definition at line 178 of file r8a66597.h.

#define UPPHUB   0x7800

Definition at line 418 of file r8a66597.h.

#define USBADDR   0x50

Definition at line 92 of file r8a66597.h.

#define USBE   0x0001 /* b0: USB module operation enable */

Definition at line 150 of file r8a66597.h.

#define USBINDX   0x58

Definition at line 95 of file r8a66597.h.

#define USBLENG   0x5A

Definition at line 96 of file r8a66597.h.

#define USBREQ   0x54

Definition at line 93 of file r8a66597.h.

#define USBRST   0x0040 /* b6: USB reset enable */

Definition at line 170 of file r8a66597.h.

#define USBSPD   0x00C0

Definition at line 420 of file r8a66597.h.

#define USBVAL   0x56

Definition at line 94 of file r8a66597.h.

#define UTST   0x000F /* b3-0: Test select */

Definition at line 181 of file r8a66597.h.

#define VALID   0x0008 /* b3: Setup packet detected flag */

Definition at line 319 of file r8a66597.h.

#define VBINT   0x8000 /* b15: VBUS interrupt */

Definition at line 299 of file r8a66597.h.

#define VBOUT   0x0200 /* b9: VBUS output */

Definition at line 167 of file r8a66597.h.

#define VBSE   0x8000 /* b15: VBUS interrupt */

Definition at line 234 of file r8a66597.h.

#define VBSTS   0x0080 /* b7: VBUS input port */

Definition at line 307 of file r8a66597.h.

#define VIF1   0x0000 /* VIF = 1.8V */

Definition at line 195 of file r8a66597.h.

#define VIF3   0x8000 /* VIF = 3.3V */

Definition at line 196 of file r8a66597.h.

#define WKUP   0x0100 /* b8: Remote wakeup */

Definition at line 168 of file r8a66597.h.

#define XCKE   0x2000 /* b13: External clock enable */

Definition at line 141 of file r8a66597.h.

#define XTAL   0xC000 /* b15-14: Crystal selection */

Definition at line 137 of file r8a66597.h.

#define XTAL12   0x0000 /* 12MHz */

Definition at line 140 of file r8a66597.h.

#define XTAL24   0x4000 /* 24MHz */

Definition at line 139 of file r8a66597.h.

#define XTAL48   0x8000 /* 48MHz */

Definition at line 138 of file r8a66597.h.