intc-simr.c File Reference

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/traps.h>

Go to the source code of this file.

Macros
#define	EINT0   64 /* Is not actually used, but spot reserved for it */
#define	EINT1   65 /* EDGE Port interrupt 1 */
#define	EINT7   71 /* EDGE Port interrupt 7 */

Functions
void __init	init_IRQ (void)

Macro Definition Documentation

#define EINT0   64 /* Is not actually used, but spot reserved for it */

Definition at line 50 of file intc-simr.c.

#define EINT1   65 /* EDGE Port interrupt 1 */

Definition at line 51 of file intc-simr.c.

#define EINT7   71 /* EDGE Port interrupt 7 */

Definition at line 52 of file intc-simr.c.

Function Documentation

void __init init_IRQ

(

void

)

The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.

The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.

Definition at line 177 of file intc-simr.c.