intel-agp.h File Reference

Go to the source code of this file.

Macros
#define	INTEL_APSIZE   0xb4
#define	INTEL_ATTBASE   0xb8
#define	INTEL_AGPCTRL   0xb0
#define	INTEL_NBXCFG   0x50
#define	INTEL_ERRSTS   0x91
#define	I830_GMCH_CTRL   0x52
#define	I830_GMCH_ENABLED   0x4
#define	I830_GMCH_MEM_MASK   0x1
#define	I830_GMCH_MEM_64M   0x1
#define	I830_GMCH_MEM_128M   0
#define	I830_GMCH_GMS_MASK   0x70
#define	I830_GMCH_GMS_DISABLED   0x00
#define	I830_GMCH_GMS_LOCAL   0x10
#define	I830_GMCH_GMS_STOLEN_512   0x20
#define	I830_GMCH_GMS_STOLEN_1024   0x30
#define	I830_GMCH_GMS_STOLEN_8192   0x40
#define	I830_RDRAM_CHANNEL_TYPE   0x03010
#define	I830_RDRAM_ND(x)   (((x) & 0x20) >> 5)
#define	I830_RDRAM_DDT(x)   (((x) & 0x18) >> 3)
#define	INTEL_I830_ERRSTS   0x92
#define	I855_GMCH_GMS_MASK   0xF0
#define	I855_GMCH_GMS_STOLEN_0M   0x0
#define	I855_GMCH_GMS_STOLEN_1M   (0x1 << 4)
#define	I855_GMCH_GMS_STOLEN_4M   (0x2 << 4)
#define	I855_GMCH_GMS_STOLEN_8M   (0x3 << 4)
#define	I855_GMCH_GMS_STOLEN_16M   (0x4 << 4)
#define	I855_GMCH_GMS_STOLEN_32M   (0x5 << 4)
#define	I85X_CAPID   0x44
#define	I85X_VARIANT_MASK   0x7
#define	I85X_VARIANT_SHIFT   5
#define	I855_GME   0x0
#define	I855_GM   0x4
#define	I852_GME   0x2
#define	I852_GM   0x5
#define	INTEL_I845_AGPM   0x51
#define	INTEL_I845_ERRSTS   0xc8
#define	INTEL_I860_MCHCFG   0x50
#define	INTEL_I860_ERRSTS   0xc8
#define	I810_GMADDR   0x10
#define	I810_MMADDR   0x14
#define	I810_PTE_BASE   0x10000
#define	I810_PTE_MAIN_UNCACHED   0x00000000
#define	I810_PTE_LOCAL   0x00000002
#define	I810_PTE_VALID   0x00000001
#define	I830_PTE_SYSTEM_CACHED   0x00000006
#define	GEN6_PTE_UNCACHED   0x00000002
#define	HSW_PTE_UNCACHED   0x00000000
#define	GEN6_PTE_LLC   0x00000004
#define	GEN6_PTE_LLC_MLC   0x00000006
#define	GEN6_PTE_GFDT   0x00000008
#define	I810_SMRAM_MISCC   0x70
#define	I810_GFX_MEM_WIN_SIZE   0x00010000
#define	I810_GFX_MEM_WIN_32M   0x00010000
#define	I810_GMS   0x000000c0
#define	I810_GMS_DISABLE   0x00000000
#define	I810_PGETBL_CTL   0x2020
#define	I810_PGETBL_ENABLED   0x00000001
#define	I965_PGETBL_CTL2   0x20c4
#define	I965_PGETBL_SIZE_MASK   0x0000000e
#define	I965_PGETBL_SIZE_512KB   (0 << 1)
#define	I965_PGETBL_SIZE_256KB   (1 << 1)
#define	I965_PGETBL_SIZE_128KB   (2 << 1)
#define	I965_PGETBL_SIZE_1MB   (3 << 1)
#define	I965_PGETBL_SIZE_2MB   (4 << 1)
#define	I965_PGETBL_SIZE_1_5MB   (5 << 1)
#define	G33_GMCH_SIZE_MASK   (3 << 8)
#define	G33_GMCH_SIZE_1M   (1 << 8)
#define	G33_GMCH_SIZE_2M   (2 << 8)
#define	G4x_GMCH_SIZE_MASK   (0xf << 8)
#define	G4x_GMCH_SIZE_1M   (0x1 << 8)
#define	G4x_GMCH_SIZE_2M   (0x3 << 8)
#define	G4x_GMCH_SIZE_VT_EN   (0x8 << 8)
#define	G4x_GMCH_SIZE_VT_1M   (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
#define	G4x_GMCH_SIZE_VT_1_5M   ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
#define	G4x_GMCH_SIZE_VT_2M   (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
#define	GFX_FLSH_CNTL   0x2170 /* 915+ */
#define	GFX_FLSH_CNTL_VLV   0x101008
#define	I810_DRAM_CTL   0x3000
#define	I810_DRAM_ROW_0   0x00000001
#define	I810_DRAM_ROW_0_SDRAM   0x00000001
#define	INTEL_815_APCONT   0x51
#define	INTEL_815_ATTBASE_MASK   ~0x1FFFFFFF
#define	INTEL_I820_RDCR   0x51
#define	INTEL_I820_ERRSTS   0xc8
#define	INTEL_I840_MCHCFG   0x50
#define	INTEL_I840_ERRSTS   0xc8
#define	INTEL_I850_MCHCFG   0x50
#define	INTEL_I850_ERRSTS   0xc8
#define	I915_GMADDR   0x18
#define	I915_MMADDR   0x10
#define	I915_PTEADDR   0x1C
#define	I915_GMCH_GMS_STOLEN_48M   (0x6 << 4)
#define	I915_GMCH_GMS_STOLEN_64M   (0x7 << 4)
#define	G33_GMCH_GMS_STOLEN_128M   (0x8 << 4)
#define	G33_GMCH_GMS_STOLEN_256M   (0x9 << 4)
#define	INTEL_GMCH_GMS_STOLEN_96M   (0xa << 4)
#define	INTEL_GMCH_GMS_STOLEN_160M   (0xb << 4)
#define	INTEL_GMCH_GMS_STOLEN_224M   (0xc << 4)
#define	INTEL_GMCH_GMS_STOLEN_352M   (0xd << 4)
#define	I915_IFPADDR   0x60
#define	I830_HIC   0x70
#define	I965_MSAC   0x62
#define	I965_IFPADDR   0x70
#define	INTEL_I7505_APSIZE   0x74
#define	INTEL_I7505_NCAPID   0x60
#define	INTEL_I7505_NISTAT   0x6c
#define	INTEL_I7505_ATTBASE   0x78
#define	INTEL_I7505_ERRSTS   0x42
#define	INTEL_I7505_AGPCTRL   0x70
#define	INTEL_I7505_MCHCFG   0x50
#define	SNB_GMCH_CTRL   0x50
#define	SNB_GMCH_GMS_STOLEN_MASK   0xF8
#define	SNB_GMCH_GMS_STOLEN_32M   (1 << 3)
#define	SNB_GMCH_GMS_STOLEN_64M   (2 << 3)
#define	SNB_GMCH_GMS_STOLEN_96M   (3 << 3)
#define	SNB_GMCH_GMS_STOLEN_128M   (4 << 3)
#define	SNB_GMCH_GMS_STOLEN_160M   (5 << 3)
#define	SNB_GMCH_GMS_STOLEN_192M   (6 << 3)
#define	SNB_GMCH_GMS_STOLEN_224M   (7 << 3)
#define	SNB_GMCH_GMS_STOLEN_256M   (8 << 3)
#define	SNB_GMCH_GMS_STOLEN_288M   (9 << 3)
#define	SNB_GMCH_GMS_STOLEN_320M   (0xa << 3)
#define	SNB_GMCH_GMS_STOLEN_352M   (0xb << 3)
#define	SNB_GMCH_GMS_STOLEN_384M   (0xc << 3)
#define	SNB_GMCH_GMS_STOLEN_416M   (0xd << 3)
#define	SNB_GMCH_GMS_STOLEN_448M   (0xe << 3)
#define	SNB_GMCH_GMS_STOLEN_480M   (0xf << 3)
#define	SNB_GMCH_GMS_STOLEN_512M   (0x10 << 3)
#define	SNB_GTT_SIZE_0M   (0 << 8)
#define	SNB_GTT_SIZE_1M   (1 << 8)
#define	SNB_GTT_SIZE_2M   (2 << 8)
#define	SNB_GTT_SIZE_MASK   (3 << 8)
#define	PCI_DEVICE_ID_INTEL_E7221_HB   0x2588
#define	PCI_DEVICE_ID_INTEL_E7221_IG   0x258a
#define	PCI_DEVICE_ID_INTEL_82946GZ_HB   0x2970
#define	PCI_DEVICE_ID_INTEL_82946GZ_IG   0x2972
#define	PCI_DEVICE_ID_INTEL_82G35_HB   0x2980
#define	PCI_DEVICE_ID_INTEL_82G35_IG   0x2982
#define	PCI_DEVICE_ID_INTEL_82965Q_HB   0x2990
#define	PCI_DEVICE_ID_INTEL_82965Q_IG   0x2992
#define	PCI_DEVICE_ID_INTEL_82965G_HB   0x29A0
#define	PCI_DEVICE_ID_INTEL_82965G_IG   0x29A2
#define	PCI_DEVICE_ID_INTEL_82965GM_HB   0x2A00
#define	PCI_DEVICE_ID_INTEL_82965GM_IG   0x2A02
#define	PCI_DEVICE_ID_INTEL_82965GME_HB   0x2A10
#define	PCI_DEVICE_ID_INTEL_82965GME_IG   0x2A12
#define	PCI_DEVICE_ID_INTEL_82945GME_HB   0x27AC
#define	PCI_DEVICE_ID_INTEL_82945GME_IG   0x27AE
#define	PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB   0xA010
#define	PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG   0xA011
#define	PCI_DEVICE_ID_INTEL_PINEVIEW_HB   0xA000
#define	PCI_DEVICE_ID_INTEL_PINEVIEW_IG   0xA001
#define	PCI_DEVICE_ID_INTEL_G33_HB   0x29C0
#define	PCI_DEVICE_ID_INTEL_G33_IG   0x29C2
#define	PCI_DEVICE_ID_INTEL_Q35_HB   0x29B0
#define	PCI_DEVICE_ID_INTEL_Q35_IG   0x29B2
#define	PCI_DEVICE_ID_INTEL_Q33_HB   0x29D0
#define	PCI_DEVICE_ID_INTEL_Q33_IG   0x29D2
#define	PCI_DEVICE_ID_INTEL_B43_HB   0x2E40
#define	PCI_DEVICE_ID_INTEL_B43_IG   0x2E42
#define	PCI_DEVICE_ID_INTEL_B43_1_HB   0x2E90
#define	PCI_DEVICE_ID_INTEL_B43_1_IG   0x2E92
#define	PCI_DEVICE_ID_INTEL_GM45_HB   0x2A40
#define	PCI_DEVICE_ID_INTEL_GM45_IG   0x2A42
#define	PCI_DEVICE_ID_INTEL_EAGLELAKE_HB   0x2E00
#define	PCI_DEVICE_ID_INTEL_EAGLELAKE_IG   0x2E02
#define	PCI_DEVICE_ID_INTEL_Q45_HB   0x2E10
#define	PCI_DEVICE_ID_INTEL_Q45_IG   0x2E12
#define	PCI_DEVICE_ID_INTEL_G45_HB   0x2E20
#define	PCI_DEVICE_ID_INTEL_G45_IG   0x2E22
#define	PCI_DEVICE_ID_INTEL_G41_HB   0x2E30
#define	PCI_DEVICE_ID_INTEL_G41_IG   0x2E32
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB   0x0040
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB   0x0069
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG   0x0042
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB   0x0044
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB   0x0062
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB   0x006a
#define	PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG   0x0046
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB   0x0100 /* Desktop */
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG   0x0102
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG   0x0112
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG   0x0122
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB   0x0104 /* Mobile */
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG   0x0106
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG   0x0116
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG   0x0126
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB   0x0108 /* Server */
#define	PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG   0x010A
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB   0x0150 /* Desktop */
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG   0x0152
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG   0x0162
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB   0x0154 /* Mobile */
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG   0x0156
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG   0x0166
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB   0x0158 /* Server */
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG   0x015A
#define	PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG   0x016A
#define	PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB   0x0F00 /* VLV1 */
#define	PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG   0x0F30
#define	PCI_DEVICE_ID_INTEL_HASWELL_HB   0x0400 /* Desktop */
#define	PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG   0x0402
#define	PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG   0x0412
#define	PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG   0x0422
#define	PCI_DEVICE_ID_INTEL_HASWELL_M_HB   0x0404 /* Mobile */
#define	PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG   0x0406
#define	PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG   0x0416
#define	PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG   0x0426
#define	PCI_DEVICE_ID_INTEL_HASWELL_S_HB   0x0408 /* Server */
#define	PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG   0x040a
#define	PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG   0x041a
#define	PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG   0x042a
#define	PCI_DEVICE_ID_INTEL_HASWELL_E_HB   0x0c04
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG   0x0C02
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG   0x0C12
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG   0x0C22
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG   0x0C06
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG   0x0C16
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG   0x0C26
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG   0x0C0A
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG   0x0C1A
#define	PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG   0x0C2A
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG   0x0A02
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG   0x0A12
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG   0x0A22
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG   0x0A06
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG   0x0A16
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG   0x0A26
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG   0x0A0A
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG   0x0A1A
#define	PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG   0x0A2A
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG   0x0D12
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG   0x0D22
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG   0x0D32
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG   0x0D16
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG   0x0D26
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG   0x0D36
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG   0x0D1A
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG   0x0D2A
#define	PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG   0x0D3A

Macro Definition Documentation

#define G33_GMCH_GMS_STOLEN_128M   (0x8 << 4)

Definition at line 128 of file intel-agp.h.

#define G33_GMCH_GMS_STOLEN_256M   (0x9 << 4)

Definition at line 129 of file intel-agp.h.

#define G33_GMCH_SIZE_1M   (1 << 8)

Definition at line 89 of file intel-agp.h.

#define G33_GMCH_SIZE_2M   (2 << 8)

Definition at line 90 of file intel-agp.h.

#define G33_GMCH_SIZE_MASK   (3 << 8)

Definition at line 88 of file intel-agp.h.

#define G4x_GMCH_SIZE_1M   (0x1 << 8)

Definition at line 92 of file intel-agp.h.

#define G4x_GMCH_SIZE_2M   (0x3 << 8)

Definition at line 93 of file intel-agp.h.

#define G4x_GMCH_SIZE_MASK   (0xf << 8)

Definition at line 91 of file intel-agp.h.

#define G4x_GMCH_SIZE_VT_1_5M   ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)

Definition at line 96 of file intel-agp.h.

#define G4x_GMCH_SIZE_VT_1M   (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)

Definition at line 95 of file intel-agp.h.

#define G4x_GMCH_SIZE_VT_2M   (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)

Definition at line 97 of file intel-agp.h.

#define G4x_GMCH_SIZE_VT_EN   (0x8 << 8)

Definition at line 94 of file intel-agp.h.

#define GEN6_PTE_GFDT   0x00000008

Definition at line 70 of file intel-agp.h.

#define GEN6_PTE_LLC   0x00000004

Definition at line 68 of file intel-agp.h.

#define GEN6_PTE_LLC_MLC   0x00000006

Definition at line 69 of file intel-agp.h.

#define GEN6_PTE_UNCACHED   0x00000002

Definition at line 66 of file intel-agp.h.

#define GFX_FLSH_CNTL   0x2170 /* 915+ */

Definition at line 99 of file intel-agp.h.

#define GFX_FLSH_CNTL_VLV   0x101008

Definition at line 100 of file intel-agp.h.

#define HSW_PTE_UNCACHED   0x00000000

Definition at line 67 of file intel-agp.h.

#define I810_DRAM_CTL   0x3000

Definition at line 102 of file intel-agp.h.

#define I810_DRAM_ROW_0   0x00000001

Definition at line 103 of file intel-agp.h.

#define I810_DRAM_ROW_0_SDRAM   0x00000001

Definition at line 104 of file intel-agp.h.

#define I810_GFX_MEM_WIN_32M   0x00010000

Definition at line 74 of file intel-agp.h.

#define I810_GFX_MEM_WIN_SIZE   0x00010000

Definition at line 73 of file intel-agp.h.

#define I810_GMADDR   0x10

Definition at line 58 of file intel-agp.h.

#define I810_GMS   0x000000c0

Definition at line 75 of file intel-agp.h.

#define I810_GMS_DISABLE   0x00000000

Definition at line 76 of file intel-agp.h.

#define I810_MMADDR   0x14

Definition at line 59 of file intel-agp.h.

#define I810_PGETBL_CTL   0x2020

Definition at line 77 of file intel-agp.h.

#define I810_PGETBL_ENABLED   0x00000001

Definition at line 78 of file intel-agp.h.

#define I810_PTE_BASE   0x10000

Definition at line 60 of file intel-agp.h.

#define I810_PTE_LOCAL   0x00000002

Definition at line 62 of file intel-agp.h.

#define I810_PTE_MAIN_UNCACHED   0x00000000

Definition at line 61 of file intel-agp.h.

#define I810_PTE_VALID   0x00000001

Definition at line 63 of file intel-agp.h.

#define I810_SMRAM_MISCC   0x70

Definition at line 72 of file intel-agp.h.

#define I830_GMCH_CTRL   0x52

Definition at line 15 of file intel-agp.h.

#define I830_GMCH_ENABLED   0x4

Definition at line 16 of file intel-agp.h.

#define I830_GMCH_GMS_DISABLED   0x00

Definition at line 21 of file intel-agp.h.

#define I830_GMCH_GMS_LOCAL   0x10

Definition at line 22 of file intel-agp.h.

#define I830_GMCH_GMS_MASK   0x70

Definition at line 20 of file intel-agp.h.

#define I830_GMCH_GMS_STOLEN_1024   0x30

Definition at line 24 of file intel-agp.h.

#define I830_GMCH_GMS_STOLEN_512   0x20

Definition at line 23 of file intel-agp.h.

#define I830_GMCH_GMS_STOLEN_8192   0x40

Definition at line 25 of file intel-agp.h.

#define I830_GMCH_MEM_128M   0

Definition at line 19 of file intel-agp.h.

#define I830_GMCH_MEM_64M   0x1

Definition at line 18 of file intel-agp.h.

#define I830_GMCH_MEM_MASK   0x1

Definition at line 17 of file intel-agp.h.

#define I830_HIC   0x70

Definition at line 136 of file intel-agp.h.

#define I830_PTE_SYSTEM_CACHED   0x00000006

Definition at line 64 of file intel-agp.h.

#define I830_RDRAM_CHANNEL_TYPE   0x03010

Definition at line 26 of file intel-agp.h.

#define I830_RDRAM_DDT

(

x

)

(((x) & 0x18) >> 3)

Definition at line 28 of file intel-agp.h.

#define I830_RDRAM_ND

(

x

)

(((x) & 0x20) >> 5)

Definition at line 27 of file intel-agp.h.

#define I852_GM   0x5

Definition at line 47 of file intel-agp.h.

#define I852_GME   0x2

Definition at line 46 of file intel-agp.h.

#define I855_GM   0x4

Definition at line 45 of file intel-agp.h.

#define I855_GMCH_GMS_MASK   0xF0

Definition at line 34 of file intel-agp.h.

#define I855_GMCH_GMS_STOLEN_0M   0x0

Definition at line 35 of file intel-agp.h.

#define I855_GMCH_GMS_STOLEN_16M   (0x4 << 4)

Definition at line 39 of file intel-agp.h.

#define I855_GMCH_GMS_STOLEN_1M   (0x1 << 4)

Definition at line 36 of file intel-agp.h.

#define I855_GMCH_GMS_STOLEN_32M   (0x5 << 4)

Definition at line 40 of file intel-agp.h.

#define I855_GMCH_GMS_STOLEN_4M   (0x2 << 4)

Definition at line 37 of file intel-agp.h.

#define I855_GMCH_GMS_STOLEN_8M   (0x3 << 4)

Definition at line 38 of file intel-agp.h.

#define I855_GME   0x0

Definition at line 44 of file intel-agp.h.

#define I85X_CAPID   0x44

Definition at line 41 of file intel-agp.h.

#define I85X_VARIANT_MASK   0x7

Definition at line 42 of file intel-agp.h.

#define I85X_VARIANT_SHIFT   5

Definition at line 43 of file intel-agp.h.

#define I915_GMADDR   0x18

Definition at line 123 of file intel-agp.h.

#define I915_GMCH_GMS_STOLEN_48M   (0x6 << 4)

Definition at line 126 of file intel-agp.h.

#define I915_GMCH_GMS_STOLEN_64M   (0x7 << 4)

Definition at line 127 of file intel-agp.h.

#define I915_IFPADDR   0x60

Definition at line 135 of file intel-agp.h.

#define I915_MMADDR   0x10

Definition at line 124 of file intel-agp.h.

#define I915_PTEADDR   0x1C

Definition at line 125 of file intel-agp.h.

#define I965_IFPADDR   0x70

Definition at line 140 of file intel-agp.h.

#define I965_MSAC   0x62

Definition at line 139 of file intel-agp.h.

#define I965_PGETBL_CTL2   0x20c4

Definition at line 80 of file intel-agp.h.

#define I965_PGETBL_SIZE_128KB   (2 << 1)

Definition at line 84 of file intel-agp.h.

#define I965_PGETBL_SIZE_1_5MB   (5 << 1)

Definition at line 87 of file intel-agp.h.

#define I965_PGETBL_SIZE_1MB   (3 << 1)

Definition at line 85 of file intel-agp.h.

#define I965_PGETBL_SIZE_256KB   (1 << 1)

Definition at line 83 of file intel-agp.h.

#define I965_PGETBL_SIZE_2MB   (4 << 1)

Definition at line 86 of file intel-agp.h.

#define I965_PGETBL_SIZE_512KB   (0 << 1)

Definition at line 82 of file intel-agp.h.

#define I965_PGETBL_SIZE_MASK   0x0000000e

Definition at line 81 of file intel-agp.h.

#define INTEL_815_APCONT   0x51

Definition at line 107 of file intel-agp.h.

#define INTEL_815_ATTBASE_MASK   ~0x1FFFFFFF

Definition at line 108 of file intel-agp.h.

#define INTEL_AGPCTRL   0xb0

Definition at line 10 of file intel-agp.h.

#define INTEL_APSIZE   0xb4

Definition at line 8 of file intel-agp.h.

#define INTEL_ATTBASE   0xb8

Definition at line 9 of file intel-agp.h.

#define INTEL_ERRSTS   0x91

Definition at line 12 of file intel-agp.h.

#define INTEL_GMCH_GMS_STOLEN_160M   (0xb << 4)

Definition at line 131 of file intel-agp.h.

#define INTEL_GMCH_GMS_STOLEN_224M   (0xc << 4)

Definition at line 132 of file intel-agp.h.

#define INTEL_GMCH_GMS_STOLEN_352M   (0xd << 4)

Definition at line 133 of file intel-agp.h.

#define INTEL_GMCH_GMS_STOLEN_96M   (0xa << 4)

Definition at line 130 of file intel-agp.h.

#define INTEL_I7505_AGPCTRL   0x70

Definition at line 148 of file intel-agp.h.

#define INTEL_I7505_APSIZE   0x74

Definition at line 143 of file intel-agp.h.

#define INTEL_I7505_ATTBASE   0x78

Definition at line 146 of file intel-agp.h.

#define INTEL_I7505_ERRSTS   0x42

Definition at line 147 of file intel-agp.h.

#define INTEL_I7505_MCHCFG   0x50

Definition at line 149 of file intel-agp.h.

#define INTEL_I7505_NCAPID   0x60

Definition at line 144 of file intel-agp.h.

#define INTEL_I7505_NISTAT   0x6c

Definition at line 145 of file intel-agp.h.

#define INTEL_I820_ERRSTS   0xc8

Definition at line 112 of file intel-agp.h.

#define INTEL_I820_RDCR   0x51

Definition at line 111 of file intel-agp.h.

#define INTEL_I830_ERRSTS   0x92

Definition at line 31 of file intel-agp.h.

#define INTEL_I840_ERRSTS   0xc8

Definition at line 116 of file intel-agp.h.

#define INTEL_I840_MCHCFG   0x50

Definition at line 115 of file intel-agp.h.

#define INTEL_I845_AGPM   0x51

Definition at line 50 of file intel-agp.h.

#define INTEL_I845_ERRSTS   0xc8

Definition at line 51 of file intel-agp.h.

#define INTEL_I850_ERRSTS   0xc8

Definition at line 120 of file intel-agp.h.

#define INTEL_I850_MCHCFG   0x50

Definition at line 119 of file intel-agp.h.

#define INTEL_I860_ERRSTS   0xc8

Definition at line 55 of file intel-agp.h.

#define INTEL_I860_MCHCFG   0x50

Definition at line 54 of file intel-agp.h.

#define INTEL_NBXCFG   0x50

Definition at line 11 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82945GME_HB   0x27AC

Definition at line 189 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82945GME_IG   0x27AE

Definition at line 190 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82946GZ_HB   0x2970

Definition at line 177 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82946GZ_IG   0x2972

Definition at line 178 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965G_HB   0x29A0

Definition at line 183 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965G_IG   0x29A2

Definition at line 184 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965GM_HB   0x2A00

Definition at line 185 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965GM_IG   0x2A02

Definition at line 186 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965GME_HB   0x2A10

Definition at line 187 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965GME_IG   0x2A12

Definition at line 188 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965Q_HB   0x2990

Definition at line 181 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82965Q_IG   0x2992

Definition at line 182 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82G35_HB   0x2980

Definition at line 179 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_82G35_IG   0x2982

Definition at line 180 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_B43_1_HB   0x2E90

Definition at line 203 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_B43_1_IG   0x2E92

Definition at line 204 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_B43_HB   0x2E40

Definition at line 201 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_B43_IG   0x2E42

Definition at line 202 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_E7221_HB   0x2588

Definition at line 175 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_E7221_IG   0x258a

Definition at line 176 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB   0x2E00

Definition at line 207 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG   0x2E02

Definition at line 208 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_G33_HB   0x29C0

Definition at line 195 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_G33_IG   0x29C2

Definition at line 196 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_G41_HB   0x2E30

Definition at line 213 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_G41_IG   0x2E32

Definition at line 214 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_G45_HB   0x2E20

Definition at line 211 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_G45_IG   0x2E22

Definition at line 212 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_GM45_HB   0x2A40

Definition at line 205 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_GM45_IG   0x2A42

Definition at line 206 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG   0x0D12

Definition at line 274 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG   0x0D22

Definition at line 275 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG   0x0D32

Definition at line 276 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG   0x0D16

Definition at line 277 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG   0x0D26

Definition at line 278 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG   0x0D36

Definition at line 279 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG   0x0D1A

Definition at line 280 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG   0x0D2A

Definition at line 281 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG   0x0D3A

Definition at line 282 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG   0x0402

Definition at line 244 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG   0x0412

Definition at line 245 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG   0x0422

Definition at line 246 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB   0x0c04

Definition at line 255 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_HB   0x0400 /* Desktop */

Definition at line 243 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG   0x0406

Definition at line 248 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG   0x0416

Definition at line 249 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG   0x0426

Definition at line 250 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB   0x0404 /* Mobile */

Definition at line 247 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG   0x040a

Definition at line 252 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG   0x041a

Definition at line 253 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG   0x042a

Definition at line 254 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB   0x0408 /* Server */

Definition at line 251 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG   0x0C02

Definition at line 256 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG   0x0C12

Definition at line 257 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG   0x0C22

Definition at line 258 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG   0x0C06

Definition at line 259 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG   0x0C16

Definition at line 260 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG   0x0C26

Definition at line 261 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG   0x0C0A

Definition at line 262 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG   0x0C1A

Definition at line 263 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG   0x0C2A

Definition at line 264 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG   0x0A02

Definition at line 265 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG   0x0A12

Definition at line 266 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG   0x0A22

Definition at line 267 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG   0x0A06

Definition at line 268 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG   0x0A16

Definition at line 269 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG   0x0A26

Definition at line 270 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG   0x0A0A

Definition at line 271 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG   0x0A1A

Definition at line 272 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG   0x0A2A

Definition at line 273 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB   0x0069

Definition at line 216 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB   0x0040

Definition at line 215 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG   0x0042

Definition at line 217 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB   0x0044

Definition at line 218 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG   0x0046

Definition at line 221 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB   0x0062

Definition at line 219 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB   0x006a

Definition at line 220 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG   0x0152

Definition at line 233 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG   0x0162

Definition at line 234 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB   0x0150 /* Desktop */

Definition at line 232 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG   0x0156

Definition at line 236 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG   0x0166

Definition at line 237 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB   0x0154 /* Mobile */

Definition at line 235 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG   0x015A

Definition at line 239 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG   0x016A

Definition at line 240 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB   0x0158 /* Server */

Definition at line 238 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB   0xA000

Definition at line 193 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG   0xA001

Definition at line 194 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB   0xA010

Definition at line 191 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG   0xA011

Definition at line 192 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_Q33_HB   0x29D0

Definition at line 199 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_Q33_IG   0x29D2

Definition at line 200 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_Q35_HB   0x29B0

Definition at line 197 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_Q35_IG   0x29B2

Definition at line 198 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_Q45_HB   0x2E10

Definition at line 209 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_Q45_IG   0x2E12

Definition at line 210 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG   0x0102

Definition at line 223 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG   0x0112

Definition at line 224 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG   0x0122

Definition at line 225 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB   0x0100 /* Desktop */

Definition at line 222 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG   0x0106

Definition at line 227 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG   0x0116

Definition at line 228 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG   0x0126

Definition at line 229 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB   0x0104 /* Mobile */

Definition at line 226 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB   0x0108 /* Server */

Definition at line 230 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG   0x010A

Definition at line 231 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB   0x0F00 /* VLV1 */

Definition at line 241 of file intel-agp.h.

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG   0x0F30

Definition at line 242 of file intel-agp.h.

#define SNB_GMCH_CTRL   0x50

Definition at line 151 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_128M   (4 << 3)

Definition at line 156 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_160M   (5 << 3)

Definition at line 157 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_192M   (6 << 3)

Definition at line 158 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_224M   (7 << 3)

Definition at line 159 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_256M   (8 << 3)

Definition at line 160 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_288M   (9 << 3)

Definition at line 161 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_320M   (0xa << 3)

Definition at line 162 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_32M   (1 << 3)

Definition at line 153 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_352M   (0xb << 3)

Definition at line 163 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_384M   (0xc << 3)

Definition at line 164 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_416M   (0xd << 3)

Definition at line 165 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_448M   (0xe << 3)

Definition at line 166 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_480M   (0xf << 3)

Definition at line 167 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_512M   (0x10 << 3)

Definition at line 168 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_64M   (2 << 3)

Definition at line 154 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_96M   (3 << 3)

Definition at line 155 of file intel-agp.h.

#define SNB_GMCH_GMS_STOLEN_MASK   0xF8

Definition at line 152 of file intel-agp.h.

#define SNB_GTT_SIZE_0M   (0 << 8)

Definition at line 169 of file intel-agp.h.

#define SNB_GTT_SIZE_1M   (1 << 8)

Definition at line 170 of file intel-agp.h.

#define SNB_GTT_SIZE_2M   (2 << 8)

Definition at line 171 of file intel-agp.h.

#define SNB_GTT_SIZE_MASK   (3 << 8)

Definition at line 172 of file intel-agp.h.