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intel_sdvo_regs.h
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1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  * Eric Anholt <[email protected]>
25  */
26 
31 #define SDVO_OUTPUT_FIRST (0)
32 #define SDVO_OUTPUT_TMDS0 (1 << 0)
33 #define SDVO_OUTPUT_RGB0 (1 << 1)
34 #define SDVO_OUTPUT_CVBS0 (1 << 2)
35 #define SDVO_OUTPUT_SVID0 (1 << 3)
36 #define SDVO_OUTPUT_YPRPB0 (1 << 4)
37 #define SDVO_OUTPUT_SCART0 (1 << 5)
38 #define SDVO_OUTPUT_LVDS0 (1 << 6)
39 #define SDVO_OUTPUT_TMDS1 (1 << 8)
40 #define SDVO_OUTPUT_RGB1 (1 << 9)
41 #define SDVO_OUTPUT_CVBS1 (1 << 10)
42 #define SDVO_OUTPUT_SVID1 (1 << 11)
43 #define SDVO_OUTPUT_YPRPB1 (1 << 12)
44 #define SDVO_OUTPUT_SCART1 (1 << 13)
45 #define SDVO_OUTPUT_LVDS1 (1 << 14)
46 #define SDVO_OUTPUT_LAST (14)
47 
48 struct intel_sdvo_caps {
49  u8 vendor_id;
50  u8 device_id;
51  u8 device_rev_id;
52  u8 sdvo_version_major;
53  u8 sdvo_version_minor;
54  unsigned int sdvo_inputs_mask:2;
55  unsigned int smooth_scaling:1;
56  unsigned int sharp_scaling:1;
57  unsigned int up_scaling:1;
58  unsigned int down_scaling:1;
59  unsigned int stall_support:1;
60  unsigned int pad:1;
61  u16 output_flags;
62 } __attribute__((packed));
63 
64 /* Note: SDVO detailed timing flags match EDID misc flags. */
65 #define DTD_FLAG_HSYNC_POSITIVE (1 << 1)
66 #define DTD_FLAG_VSYNC_POSITIVE (1 << 2)
67 #define DTD_FLAG_INTERLACE (1 << 7)
68 
70 struct intel_sdvo_dtd {
71  struct {
72  u16 clock;
73  u8 h_active;
74  u8 h_blank;
75  u8 h_high;
76  u8 v_active;
77  u8 v_blank;
78  u8 v_high;
79  } part1;
80 
81  struct {
82  u8 h_sync_off;
83  u8 h_sync_width;
85  u8 v_sync_off_width;
90  u8 sync_off_width_high;
91  u8 dtd_flags;
92  u8 sdvo_flags;
94  u8 v_sync_off_high;
95  u8 reserved;
96  } part2;
97 } __attribute__((packed));
98 
99 struct intel_sdvo_pixel_clock_range {
100  u16 min;
101  u16 max;
102 } __attribute__((packed));
103 
104 struct intel_sdvo_preferred_input_timing_args {
105  u16 clock;
106  u16 width;
107  u16 height;
108  u8 interlace:1;
109  u8 scaled:1;
110  u8 pad:6;
111 } __attribute__((packed));
112 
113 /* I2C registers for SDVO */
114 #define SDVO_I2C_ARG_0 0x07
115 #define SDVO_I2C_ARG_1 0x06
116 #define SDVO_I2C_ARG_2 0x05
117 #define SDVO_I2C_ARG_3 0x04
118 #define SDVO_I2C_ARG_4 0x03
119 #define SDVO_I2C_ARG_5 0x02
120 #define SDVO_I2C_ARG_6 0x01
121 #define SDVO_I2C_ARG_7 0x00
122 #define SDVO_I2C_OPCODE 0x08
123 #define SDVO_I2C_CMD_STATUS 0x09
124 #define SDVO_I2C_RETURN_0 0x0a
125 #define SDVO_I2C_RETURN_1 0x0b
126 #define SDVO_I2C_RETURN_2 0x0c
127 #define SDVO_I2C_RETURN_3 0x0d
128 #define SDVO_I2C_RETURN_4 0x0e
129 #define SDVO_I2C_RETURN_5 0x0f
130 #define SDVO_I2C_RETURN_6 0x10
131 #define SDVO_I2C_RETURN_7 0x11
132 #define SDVO_I2C_VENDOR_BEGIN 0x20
133 
134 /* Status results */
135 #define SDVO_CMD_STATUS_POWER_ON 0x0
136 #define SDVO_CMD_STATUS_SUCCESS 0x1
137 #define SDVO_CMD_STATUS_NOTSUPP 0x2
138 #define SDVO_CMD_STATUS_INVALID_ARG 0x3
139 #define SDVO_CMD_STATUS_PENDING 0x4
140 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
141 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
142 
143 /* SDVO commands, argument/result registers */
144 
145 #define SDVO_CMD_RESET 0x01
146 
148 #define SDVO_CMD_GET_DEVICE_CAPS 0x02
149 
150 #define SDVO_CMD_GET_FIRMWARE_REV 0x86
151 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
152 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
153 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
154 
160 #define SDVO_CMD_GET_TRAINED_INPUTS 0x03
161 struct intel_sdvo_get_trained_inputs_response {
162  unsigned int input0_trained:1;
163  unsigned int input1_trained:1;
164  unsigned int pad:6;
165 } __attribute__((packed));
166 
168 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
169 
176 #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
177 
183 #define SDVO_CMD_GET_IN_OUT_MAP 0x06
184 struct intel_sdvo_in_out_map {
185  u16 in0, in1;
186 };
187 
193 #define SDVO_CMD_SET_IN_OUT_MAP 0x07
194 
198 #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
199 
203 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
204 
208 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
209 
214 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
215 
216 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
217 struct intel_sdvo_get_interrupt_event_source_response {
218  u16 interrupt_status;
219  unsigned int ambient_light_interrupt:1;
220  unsigned int hdmi_audio_encrypt_change:1;
221  unsigned int pad:6;
222 } __attribute__((packed));
223 
231 #define SDVO_CMD_SET_TARGET_INPUT 0x10
232 struct intel_sdvo_set_target_input_args {
233  unsigned int target_1:1;
234  unsigned int pad:7;
235 } __attribute__((packed));
236 
244 #define SDVO_CMD_SET_TARGET_OUTPUT 0x11
245 
246 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
247 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
248 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
249 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
250 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
251 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
252 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
253 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
254 /* Part 1 */
255 # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
256 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
257 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
258 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
259 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
260 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
261 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
262 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
263 /* Part 2 */
264 # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
265 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
266 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
267 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
268 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
269 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
270 # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
271 # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
272 # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
273 # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
274 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
275 # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
276 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
277 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
278 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
279 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
280 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
281 # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
282 
289 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
290 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
291 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
292 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
293 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
294 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
295 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
296 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
297 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
298 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
299 
300 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
301 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
302 
304 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
305 
306 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
307 
309 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
310 
312 #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
313 
314 #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
315 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
316 # define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
317 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
318 
319 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
320 
321 struct intel_sdvo_tv_format {
322  unsigned int ntsc_m:1;
323  unsigned int ntsc_j:1;
324  unsigned int ntsc_443:1;
325  unsigned int pal_b:1;
326  unsigned int pal_d:1;
327  unsigned int pal_g:1;
328  unsigned int pal_h:1;
329  unsigned int pal_i:1;
330 
331  unsigned int pal_m:1;
332  unsigned int pal_n:1;
333  unsigned int pal_nc:1;
334  unsigned int pal_60:1;
335  unsigned int secam_b:1;
336  unsigned int secam_d:1;
337  unsigned int secam_g:1;
338  unsigned int secam_k:1;
339 
340  unsigned int secam_k1:1;
341  unsigned int secam_l:1;
342  unsigned int secam_60:1;
343  unsigned int hdtv_std_smpte_240m_1080i_59:1;
344  unsigned int hdtv_std_smpte_240m_1080i_60:1;
345  unsigned int hdtv_std_smpte_260m_1080i_59:1;
346  unsigned int hdtv_std_smpte_260m_1080i_60:1;
347  unsigned int hdtv_std_smpte_274m_1080i_50:1;
348 
349  unsigned int hdtv_std_smpte_274m_1080i_59:1;
350  unsigned int hdtv_std_smpte_274m_1080i_60:1;
351  unsigned int hdtv_std_smpte_274m_1080p_23:1;
352  unsigned int hdtv_std_smpte_274m_1080p_24:1;
353  unsigned int hdtv_std_smpte_274m_1080p_25:1;
354  unsigned int hdtv_std_smpte_274m_1080p_29:1;
355  unsigned int hdtv_std_smpte_274m_1080p_30:1;
356  unsigned int hdtv_std_smpte_274m_1080p_50:1;
357 
358  unsigned int hdtv_std_smpte_274m_1080p_59:1;
359  unsigned int hdtv_std_smpte_274m_1080p_60:1;
360  unsigned int hdtv_std_smpte_295m_1080i_50:1;
361  unsigned int hdtv_std_smpte_295m_1080p_50:1;
362  unsigned int hdtv_std_smpte_296m_720p_59:1;
363  unsigned int hdtv_std_smpte_296m_720p_60:1;
364  unsigned int hdtv_std_smpte_296m_720p_50:1;
365  unsigned int hdtv_std_smpte_293m_480p_59:1;
366 
367  unsigned int hdtv_std_smpte_170m_480i_59:1;
368  unsigned int hdtv_std_iturbt601_576i_50:1;
369  unsigned int hdtv_std_iturbt601_576p_50:1;
370  unsigned int hdtv_std_eia_7702a_480i_60:1;
371  unsigned int hdtv_std_eia_7702a_480p_60:1;
372  unsigned int pad:3;
373 } __attribute__((packed));
374 
375 #define SDVO_CMD_GET_TV_FORMAT 0x28
376 
377 #define SDVO_CMD_SET_TV_FORMAT 0x29
378 
380 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
381 struct intel_sdvo_sdtv_resolution_request {
382  unsigned int ntsc_m:1;
383  unsigned int ntsc_j:1;
384  unsigned int ntsc_443:1;
385  unsigned int pal_b:1;
386  unsigned int pal_d:1;
387  unsigned int pal_g:1;
388  unsigned int pal_h:1;
389  unsigned int pal_i:1;
390 
391  unsigned int pal_m:1;
392  unsigned int pal_n:1;
393  unsigned int pal_nc:1;
394  unsigned int pal_60:1;
395  unsigned int secam_b:1;
396  unsigned int secam_d:1;
397  unsigned int secam_g:1;
398  unsigned int secam_k:1;
399 
400  unsigned int secam_k1:1;
401  unsigned int secam_l:1;
402  unsigned int secam_60:1;
403  unsigned int pad:5;
404 } __attribute__((packed));
405 
406 struct intel_sdvo_sdtv_resolution_reply {
407  unsigned int res_320x200:1;
408  unsigned int res_320x240:1;
409  unsigned int res_400x300:1;
410  unsigned int res_640x350:1;
411  unsigned int res_640x400:1;
412  unsigned int res_640x480:1;
413  unsigned int res_704x480:1;
414  unsigned int res_704x576:1;
415 
416  unsigned int res_720x350:1;
417  unsigned int res_720x400:1;
418  unsigned int res_720x480:1;
419  unsigned int res_720x540:1;
420  unsigned int res_720x576:1;
421  unsigned int res_768x576:1;
422  unsigned int res_800x600:1;
423  unsigned int res_832x624:1;
424 
425  unsigned int res_920x766:1;
426  unsigned int res_1024x768:1;
427  unsigned int res_1280x1024:1;
428  unsigned int pad:5;
429 } __attribute__((packed));
430 
431 /* Get supported resolution with squire pixel aspect ratio that can be
432  scaled for the requested HDTV format */
433 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
434 
435 struct intel_sdvo_hdtv_resolution_request {
436  unsigned int hdtv_std_smpte_240m_1080i_59:1;
437  unsigned int hdtv_std_smpte_240m_1080i_60:1;
438  unsigned int hdtv_std_smpte_260m_1080i_59:1;
439  unsigned int hdtv_std_smpte_260m_1080i_60:1;
440  unsigned int hdtv_std_smpte_274m_1080i_50:1;
441  unsigned int hdtv_std_smpte_274m_1080i_59:1;
442  unsigned int hdtv_std_smpte_274m_1080i_60:1;
443  unsigned int hdtv_std_smpte_274m_1080p_23:1;
444 
445  unsigned int hdtv_std_smpte_274m_1080p_24:1;
446  unsigned int hdtv_std_smpte_274m_1080p_25:1;
447  unsigned int hdtv_std_smpte_274m_1080p_29:1;
448  unsigned int hdtv_std_smpte_274m_1080p_30:1;
449  unsigned int hdtv_std_smpte_274m_1080p_50:1;
450  unsigned int hdtv_std_smpte_274m_1080p_59:1;
451  unsigned int hdtv_std_smpte_274m_1080p_60:1;
452  unsigned int hdtv_std_smpte_295m_1080i_50:1;
453 
454  unsigned int hdtv_std_smpte_295m_1080p_50:1;
455  unsigned int hdtv_std_smpte_296m_720p_59:1;
456  unsigned int hdtv_std_smpte_296m_720p_60:1;
457  unsigned int hdtv_std_smpte_296m_720p_50:1;
458  unsigned int hdtv_std_smpte_293m_480p_59:1;
459  unsigned int hdtv_std_smpte_170m_480i_59:1;
460  unsigned int hdtv_std_iturbt601_576i_50:1;
461  unsigned int hdtv_std_iturbt601_576p_50:1;
462 
463  unsigned int hdtv_std_eia_7702a_480i_60:1;
464  unsigned int hdtv_std_eia_7702a_480p_60:1;
465  unsigned int pad:6;
466 } __attribute__((packed));
467 
468 struct intel_sdvo_hdtv_resolution_reply {
469  unsigned int res_640x480:1;
470  unsigned int res_800x600:1;
471  unsigned int res_1024x768:1;
472  unsigned int res_1280x960:1;
473  unsigned int res_1400x1050:1;
474  unsigned int res_1600x1200:1;
475  unsigned int res_1920x1440:1;
476  unsigned int res_2048x1536:1;
477 
478  unsigned int res_2560x1920:1;
479  unsigned int res_3200x2400:1;
480  unsigned int res_3840x2880:1;
481  unsigned int pad1:5;
482 
483  unsigned int res_848x480:1;
484  unsigned int res_1064x600:1;
485  unsigned int res_1280x720:1;
486  unsigned int res_1360x768:1;
487  unsigned int res_1704x960:1;
488  unsigned int res_1864x1050:1;
489  unsigned int res_1920x1080:1;
490  unsigned int res_2128x1200:1;
491 
492  unsigned int res_2560x1400:1;
493  unsigned int res_2728x1536:1;
494  unsigned int res_3408x1920:1;
495  unsigned int res_4264x2400:1;
496  unsigned int res_5120x2880:1;
497  unsigned int pad2:3;
498 
499  unsigned int res_768x480:1;
500  unsigned int res_960x600:1;
501  unsigned int res_1152x720:1;
502  unsigned int res_1124x768:1;
503  unsigned int res_1536x960:1;
504  unsigned int res_1680x1050:1;
505  unsigned int res_1728x1080:1;
506  unsigned int res_1920x1200:1;
507 
508  unsigned int res_2304x1440:1;
509  unsigned int res_2456x1536:1;
510  unsigned int res_3072x1920:1;
511  unsigned int res_3840x2400:1;
512  unsigned int res_4608x2880:1;
513  unsigned int pad3:3;
514 
515  unsigned int res_1280x1024:1;
516  unsigned int pad4:7;
517 
518  unsigned int res_1280x768:1;
519  unsigned int pad5:7;
520 } __attribute__((packed));
521 
522 /* Get supported power state returns info for encoder and monitor, rely on
523  last SetTargetInput and SetTargetOutput calls */
524 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
525 /* Get power state returns info for encoder and monitor, rely on last
526  SetTargetInput and SetTargetOutput calls */
527 #define SDVO_CMD_GET_POWER_STATE 0x2b
528 #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
529 #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
530 # define SDVO_ENCODER_STATE_ON (1 << 0)
531 # define SDVO_ENCODER_STATE_STANDBY (1 << 1)
532 # define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
533 # define SDVO_ENCODER_STATE_OFF (1 << 3)
534 # define SDVO_MONITOR_STATE_ON (1 << 4)
535 # define SDVO_MONITOR_STATE_STANDBY (1 << 5)
536 # define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
537 # define SDVO_MONITOR_STATE_OFF (1 << 7)
538 
539 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
540 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
541 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
542 
546 struct sdvo_panel_power_sequencing {
547  u8 t0;
548  u8 t1;
549  u8 t2;
550  u8 t3;
551  u8 t4;
552 
553  unsigned int t0_high:2;
554  unsigned int t1_high:2;
555  unsigned int t2_high:2;
556  unsigned int t3_high:2;
557 
558  unsigned int t4_high:2;
559  unsigned int pad:6;
560 } __attribute__((packed));
561 
562 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
563 struct sdvo_max_backlight_reply {
564  u8 max_value;
565  u8 default_value;
566 } __attribute__((packed));
567 
568 #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
569 #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
570 
571 #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
572 struct sdvo_get_ambient_light_reply {
573  u16 trip_low;
574  u16 trip_high;
575  u16 value;
576 } __attribute__((packed));
577 #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
578 struct sdvo_set_ambient_light_reply {
579  u16 trip_low;
580  u16 trip_high;
581  unsigned int enable:1;
582  unsigned int pad:7;
583 } __attribute__((packed));
584 
585 /* Set display power state */
586 #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
587 # define SDVO_DISPLAY_STATE_ON (1 << 0)
588 # define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
589 # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
590 # define SDVO_DISPLAY_STATE_OFF (1 << 3)
591 
592 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
593 struct intel_sdvo_enhancements_reply {
594  unsigned int flicker_filter:1;
595  unsigned int flicker_filter_adaptive:1;
596  unsigned int flicker_filter_2d:1;
597  unsigned int saturation:1;
598  unsigned int hue:1;
599  unsigned int brightness:1;
600  unsigned int contrast:1;
601  unsigned int overscan_h:1;
602 
603  unsigned int overscan_v:1;
604  unsigned int hpos:1;
605  unsigned int vpos:1;
606  unsigned int sharpness:1;
607  unsigned int dot_crawl:1;
608  unsigned int dither:1;
609  unsigned int tv_chroma_filter:1;
610  unsigned int tv_luma_filter:1;
611 } __attribute__((packed));
612 
613 /* Picture enhancement limits below are dependent on the current TV format,
614  * and thus need to be queried and set after it.
615  */
616 #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d
617 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b
618 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52
619 #define SDVO_CMD_GET_MAX_SATURATION 0x55
620 #define SDVO_CMD_GET_MAX_HUE 0x58
621 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
622 #define SDVO_CMD_GET_MAX_CONTRAST 0x5e
623 #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
624 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
625 #define SDVO_CMD_GET_MAX_HPOS 0x67
626 #define SDVO_CMD_GET_MAX_VPOS 0x6a
627 #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d
628 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
629 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
630 struct intel_sdvo_enhancement_limits_reply {
631  u16 max_value;
632  u16 default_value;
633 } __attribute__((packed));
634 
635 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
636 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
637 # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
638 # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
639 # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
640 # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
641 # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
642 # define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
643 
644 #define SDVO_CMD_GET_FLICKER_FILTER 0x4e
645 #define SDVO_CMD_SET_FLICKER_FILTER 0x4f
646 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50
647 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51
648 #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53
649 #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54
650 #define SDVO_CMD_GET_SATURATION 0x56
651 #define SDVO_CMD_SET_SATURATION 0x57
652 #define SDVO_CMD_GET_HUE 0x59
653 #define SDVO_CMD_SET_HUE 0x5a
654 #define SDVO_CMD_GET_BRIGHTNESS 0x5c
655 #define SDVO_CMD_SET_BRIGHTNESS 0x5d
656 #define SDVO_CMD_GET_CONTRAST 0x5f
657 #define SDVO_CMD_SET_CONTRAST 0x60
658 #define SDVO_CMD_GET_OVERSCAN_H 0x62
659 #define SDVO_CMD_SET_OVERSCAN_H 0x63
660 #define SDVO_CMD_GET_OVERSCAN_V 0x65
661 #define SDVO_CMD_SET_OVERSCAN_V 0x66
662 #define SDVO_CMD_GET_HPOS 0x68
663 #define SDVO_CMD_SET_HPOS 0x69
664 #define SDVO_CMD_GET_VPOS 0x6b
665 #define SDVO_CMD_SET_VPOS 0x6c
666 #define SDVO_CMD_GET_SHARPNESS 0x6e
667 #define SDVO_CMD_SET_SHARPNESS 0x6f
668 #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75
669 #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76
670 #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
671 #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
672 struct intel_sdvo_enhancements_arg {
673  u16 value;
674 } __attribute__((packed));
675 
676 #define SDVO_CMD_GET_DOT_CRAWL 0x70
677 #define SDVO_CMD_SET_DOT_CRAWL 0x71
678 # define SDVO_DOT_CRAWL_ON (1 << 0)
679 # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
680 
681 #define SDVO_CMD_GET_DITHER 0x72
682 #define SDVO_CMD_SET_DITHER 0x73
683 # define SDVO_DITHER_ON (1 << 0)
684 # define SDVO_DITHER_DEFAULT_ON (1 << 1)
685 
686 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
687 # define SDVO_CONTROL_BUS_PROM (1 << 0)
688 # define SDVO_CONTROL_BUS_DDC1 (1 << 1)
689 # define SDVO_CONTROL_BUS_DDC2 (1 << 2)
690 # define SDVO_CONTROL_BUS_DDC3 (1 << 3)
691 
692 /* HDMI op codes */
693 #define SDVO_CMD_GET_SUPP_ENCODE 0x9d
694 #define SDVO_CMD_GET_ENCODE 0x9e
695 #define SDVO_CMD_SET_ENCODE 0x9f
696  #define SDVO_ENCODE_DVI 0x0
697  #define SDVO_ENCODE_HDMI 0x1
698 #define SDVO_CMD_SET_PIXEL_REPLI 0x8b
699 #define SDVO_CMD_GET_PIXEL_REPLI 0x8c
700 #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
701 #define SDVO_CMD_SET_COLORIMETRY 0x8e
702  #define SDVO_COLORIMETRY_RGB256 0x0
703  #define SDVO_COLORIMETRY_RGB220 0x1
704  #define SDVO_COLORIMETRY_YCrCb422 0x3
705  #define SDVO_COLORIMETRY_YCrCb444 0x4
706 #define SDVO_CMD_GET_COLORIMETRY 0x8f
707 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
708 #define SDVO_CMD_SET_AUDIO_STAT 0x91
709 #define SDVO_CMD_GET_AUDIO_STAT 0x92
710 #define SDVO_CMD_SET_HBUF_INDEX 0x93
711  #define SDVO_HBUF_INDEX_ELD 0
712  #define SDVO_HBUF_INDEX_AVI_IF 1
713 #define SDVO_CMD_GET_HBUF_INDEX 0x94
714 #define SDVO_CMD_GET_HBUF_INFO 0x95
715 #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
716 #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
717 #define SDVO_CMD_SET_HBUF_DATA 0x98
718 #define SDVO_CMD_GET_HBUF_DATA 0x99
719 #define SDVO_CMD_SET_HBUF_TXRATE 0x9a
720 #define SDVO_CMD_GET_HBUF_TXRATE 0x9b
721  #define SDVO_HBUF_TX_DISABLED (0 << 6)
722  #define SDVO_HBUF_TX_ONCE (2 << 6)
723  #define SDVO_HBUF_TX_VSYNC (3 << 6)
724 #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
725 #define SDVO_NEED_TO_STALL (1 << 7)
726 
727 struct intel_sdvo_encode {
728  u8 dvi_rev;
729  u8 hdmi_rev;
730 } __attribute__ ((packed));
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