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| #define MMU_CAM_P (1 << 3) |
| #define MMU_CAM_PGSZ_16M (3 << 0) |
| #define MMU_CAM_PGSZ_1M (0 << 0) |
| #define MMU_CAM_PGSZ_4K (2 << 0) |
| #define MMU_CAM_PGSZ_64K (1 << 0) |
| #define MMU_CAM_PGSZ_MASK 3 |
| #define MMU_CAM_V (1 << 2) |
| #define MMU_CAM_VATAG_MASK ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) |
| #define MMU_CAM_VATAG_SHIFT 12 |
| #define MMU_EMU_FAULT_AD 0x70 |
| #define MMU_FAULT_AD 0x48 |
| #define MMU_FLUSH_ENTRY 0x64 |
| #define MMU_IRQENABLE 0x1c |
| #define MMU_IRQSTATUS 0x18 |
| #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) |
| #define MMU_LOCK_BASE_SHIFT 10 |
| #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) |
| #define MMU_LOCK_VICT_SHIFT 4 |
| #define MMU_RAM_ELSZ_SHIFT 7 |
| #define MMU_RAM_ENDIAN_SHIFT 9 |
| #define MMU_RAM_MIXED_SHIFT 6 |
| #define MMU_RAM_PADDR_MASK ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) |
| #define MMU_RAM_PADDR_SHIFT 12 |
| #define MMU_READ_CAM 0x68 |
| #define MMU_READ_RAM 0x6c |
| #define MMU_REVISION 0x00 |
| #define MMU_SYSCONFIG 0x10 |
| #define MMU_SYSSTATUS 0x14 |
| #define MMU_WALKING_ST 0x40 |
1.8.2