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Data Structures | Macros
iommu_32.h File Reference
#include <asm/page.h>
#include <asm/bitext.h>

Go to the source code of this file.

Data Structures

struct  iommu_regs
 
struct  iommu_struct
 

Macros

#define IOMMU_CTRL_IMPL   0xf0000000 /* Implementation */
 
#define IOMMU_CTRL_VERS   0x0f000000 /* Version */
 
#define IOMMU_CTRL_RNGE   0x0000001c /* Mapping RANGE */
 
#define IOMMU_RNGE_16MB   0x00000000 /* 0xff000000 -> 0xffffffff */
 
#define IOMMU_RNGE_32MB   0x00000004 /* 0xfe000000 -> 0xffffffff */
 
#define IOMMU_RNGE_64MB   0x00000008 /* 0xfc000000 -> 0xffffffff */
 
#define IOMMU_RNGE_128MB   0x0000000c /* 0xf8000000 -> 0xffffffff */
 
#define IOMMU_RNGE_256MB   0x00000010 /* 0xf0000000 -> 0xffffffff */
 
#define IOMMU_RNGE_512MB   0x00000014 /* 0xe0000000 -> 0xffffffff */
 
#define IOMMU_RNGE_1GB   0x00000018 /* 0xc0000000 -> 0xffffffff */
 
#define IOMMU_RNGE_2GB   0x0000001c /* 0x80000000 -> 0xffffffff */
 
#define IOMMU_CTRL_ENAB   0x00000001 /* IOMMU Enable */
 
#define IOMMU_AFSR_ERR   0x80000000 /* LE, TO, or BE asserted */
 
#define IOMMU_AFSR_LE   0x40000000 /* SBUS reports error after transaction */
 
#define IOMMU_AFSR_TO   0x20000000 /* Write access took more than 12.8 us. */
 
#define IOMMU_AFSR_BE   0x10000000 /* Write access received error acknowledge */
 
#define IOMMU_AFSR_SIZE   0x0e000000 /* Size of transaction causing error */
 
#define IOMMU_AFSR_S   0x01000000 /* Sparc was in supervisor mode */
 
#define IOMMU_AFSR_RESV   0x00f00000 /* Reserver, forced to 0x8 by hardware */
 
#define IOMMU_AFSR_ME   0x00080000 /* Multiple errors occurred */
 
#define IOMMU_AFSR_RD   0x00040000 /* A read operation was in progress */
 
#define IOMMU_AFSR_FAV   0x00020000 /* IOMMU afar has valid contents */
 
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
 
#define IOMMU_SBCFG_BA16   0x00000004 /* Slave supports 16 byte bursts */
 
#define IOMMU_SBCFG_BA8   0x00000002 /* Slave supports 8 byte bursts */
 
#define IOMMU_SBCFG_BYPASS
 
#define IOMMU_MFSR_ERR   0x80000000 /* One or more of PERR1 or PERR0 */
 
#define IOMMU_MFSR_S   0x01000000 /* Sparc was in supervisor mode */
 
#define IOMMU_MFSR_CPU   0x00800000 /* CPU transaction caused parity error */
 
#define IOMMU_MFSR_ME   0x00080000 /* Multiple parity errors occurred */
 
#define IOMMU_MFSR_PERR
 
#define IOMMU_MFSR_BM   0x00001000 /* Error occurred while in boot mode */
 
#define IOMMU_MFSR_C   0x00000800 /* Address causing error was marked cacheable */
 
#define IOMMU_MFSR_RTYP   0x000000f0 /* Memory request transaction type */
 
#define IOMMU_MID_SBAE   0x001f0000 /* SBus arbitration enable */
 
#define IOMMU_MID_SE   0x00100000 /* Enables SCSI/ETHERNET arbitration */
 
#define IOMMU_MID_SB3   0x00080000 /* Enable SBUS device 3 arbitration */
 
#define IOMMU_MID_SB2   0x00040000 /* Enable SBUS device 2 arbitration */
 
#define IOMMU_MID_SB1   0x00020000 /* Enable SBUS device 1 arbitration */
 
#define IOMMU_MID_SB0   0x00010000 /* Enable SBUS device 0 arbitration */
 
#define IOMMU_MID_MID   0x0000000f /* Module-id, hardcoded to 0x8 */
 
#define IOPTE_PAGE   0x07ffff00 /* Physical page number (PA[30:12]) */
 
#define IOPTE_CACHE   0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
 
#define IOPTE_WRITE   0x00000004 /* Writeable */
 
#define IOPTE_VALID   0x00000002 /* IOPTE is valid */
 
#define IOPTE_WAZ   0x00000001 /* Write as zeros */
 

Macro Definition Documentation

#define IOMMU_AFSR_BE   0x10000000 /* Write access received error acknowledge */

Definition at line 60 of file iommu_32.h.

#define IOMMU_AFSR_ERR   0x80000000 /* LE, TO, or BE asserted */

Definition at line 57 of file iommu_32.h.

#define IOMMU_AFSR_FAV   0x00020000 /* IOMMU afar has valid contents */

Definition at line 66 of file iommu_32.h.

#define IOMMU_AFSR_LE   0x40000000 /* SBUS reports error after transaction */

Definition at line 58 of file iommu_32.h.

#define IOMMU_AFSR_ME   0x00080000 /* Multiple errors occurred */

Definition at line 64 of file iommu_32.h.

#define IOMMU_AFSR_RD   0x00040000 /* A read operation was in progress */

Definition at line 65 of file iommu_32.h.

#define IOMMU_AFSR_RESV   0x00f00000 /* Reserver, forced to 0x8 by hardware */

Definition at line 63 of file iommu_32.h.

#define IOMMU_AFSR_S   0x01000000 /* Sparc was in supervisor mode */

Definition at line 62 of file iommu_32.h.

#define IOMMU_AFSR_SIZE   0x0e000000 /* Size of transaction causing error */

Definition at line 61 of file iommu_32.h.

#define IOMMU_AFSR_TO   0x20000000 /* Write access took more than 12.8 us. */

Definition at line 59 of file iommu_32.h.

#define IOMMU_CTRL_ENAB   0x00000001 /* IOMMU Enable */

Definition at line 55 of file iommu_32.h.

#define IOMMU_CTRL_IMPL   0xf0000000 /* Implementation */

Definition at line 44 of file iommu_32.h.

#define IOMMU_CTRL_RNGE   0x0000001c /* Mapping RANGE */

Definition at line 46 of file iommu_32.h.

#define IOMMU_CTRL_VERS   0x0f000000 /* Version */

Definition at line 45 of file iommu_32.h.

#define IOMMU_MFSR_BM   0x00001000 /* Error occurred while in boot mode */

Definition at line 78 of file iommu_32.h.

#define IOMMU_MFSR_C   0x00000800 /* Address causing error was marked cacheable */

Definition at line 79 of file iommu_32.h.

#define IOMMU_MFSR_CPU   0x00800000 /* CPU transaction caused parity error */

Definition at line 75 of file iommu_32.h.

#define IOMMU_MFSR_ERR   0x80000000 /* One or more of PERR1 or PERR0 */

Definition at line 73 of file iommu_32.h.

#define IOMMU_MFSR_ME   0x00080000 /* Multiple parity errors occurred */

Definition at line 76 of file iommu_32.h.

#define IOMMU_MFSR_PERR
Value:
0x00006000 /* high bit indicates parity error occurred
on the even word of the access, low bit
indicated odd word caused the parity error */

Definition at line 77 of file iommu_32.h.

#define IOMMU_MFSR_RTYP   0x000000f0 /* Memory request transaction type */

Definition at line 80 of file iommu_32.h.

#define IOMMU_MFSR_S   0x01000000 /* Sparc was in supervisor mode */

Definition at line 74 of file iommu_32.h.

#define IOMMU_MID_MID   0x0000000f /* Module-id, hardcoded to 0x8 */

Definition at line 88 of file iommu_32.h.

#define IOMMU_MID_SB0   0x00010000 /* Enable SBUS device 0 arbitration */

Definition at line 87 of file iommu_32.h.

#define IOMMU_MID_SB1   0x00020000 /* Enable SBUS device 1 arbitration */

Definition at line 86 of file iommu_32.h.

#define IOMMU_MID_SB2   0x00040000 /* Enable SBUS device 2 arbitration */

Definition at line 85 of file iommu_32.h.

#define IOMMU_MID_SB3   0x00080000 /* Enable SBUS device 3 arbitration */

Definition at line 84 of file iommu_32.h.

#define IOMMU_MID_SBAE   0x001f0000 /* SBus arbitration enable */

Definition at line 82 of file iommu_32.h.

#define IOMMU_MID_SE   0x00100000 /* Enables SCSI/ETHERNET arbitration */

Definition at line 83 of file iommu_32.h.

#define IOMMU_RNGE_128MB   0x0000000c /* 0xf8000000 -> 0xffffffff */

Definition at line 50 of file iommu_32.h.

#define IOMMU_RNGE_16MB   0x00000000 /* 0xff000000 -> 0xffffffff */

Definition at line 47 of file iommu_32.h.

#define IOMMU_RNGE_1GB   0x00000018 /* 0xc0000000 -> 0xffffffff */

Definition at line 53 of file iommu_32.h.

#define IOMMU_RNGE_256MB   0x00000010 /* 0xf0000000 -> 0xffffffff */

Definition at line 51 of file iommu_32.h.

#define IOMMU_RNGE_2GB   0x0000001c /* 0x80000000 -> 0xffffffff */

Definition at line 54 of file iommu_32.h.

#define IOMMU_RNGE_32MB   0x00000004 /* 0xfe000000 -> 0xffffffff */

Definition at line 48 of file iommu_32.h.

#define IOMMU_RNGE_512MB   0x00000014 /* 0xe0000000 -> 0xffffffff */

Definition at line 52 of file iommu_32.h.

#define IOMMU_RNGE_64MB   0x00000008 /* 0xfc000000 -> 0xffffffff */

Definition at line 49 of file iommu_32.h.

#define IOMMU_SBCFG_BA16   0x00000004 /* Slave supports 16 byte bursts */

Definition at line 69 of file iommu_32.h.

#define IOMMU_SBCFG_BA8   0x00000002 /* Slave supports 8 byte bursts */

Definition at line 70 of file iommu_32.h.

#define IOMMU_SBCFG_BYPASS
Value:
0x00000001 /* Bypass IOMMU, treat all addresses
produced by this device as pure
physical. */

Definition at line 71 of file iommu_32.h.

#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */

Definition at line 68 of file iommu_32.h.

#define IOPTE_CACHE   0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */

Definition at line 92 of file iommu_32.h.

#define IOPTE_PAGE   0x07ffff00 /* Physical page number (PA[30:12]) */

Definition at line 91 of file iommu_32.h.

#define IOPTE_VALID   0x00000002 /* IOPTE is valid */

Definition at line 94 of file iommu_32.h.

#define IOPTE_WAZ   0x00000001 /* Write as zeros */

Definition at line 95 of file iommu_32.h.

#define IOPTE_WRITE   0x00000004 /* Writeable */

Definition at line 93 of file iommu_32.h.