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irqs-8960.h File Reference

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Macros

#define GIC_PPI_START   16
 
#define GIC_SPI_START   32
 
#define INT_VGIC   (GIC_PPI_START + 0)
 
#define INT_DEBUG_TIMER_EXP   (GIC_PPI_START + 1)
 
#define INT_GP_TIMER_EXP   (GIC_PPI_START + 2)
 
#define INT_GP_TIMER2_EXP   (GIC_PPI_START + 3)
 
#define WDT0_ACCSCSSNBARK_INT   (GIC_PPI_START + 4)
 
#define WDT1_ACCSCSSNBARK_INT   (GIC_PPI_START + 5)
 
#define AVS_SVICINT   (GIC_PPI_START + 6)
 
#define AVS_SVICINTSWDONE   (GIC_PPI_START + 7)
 
#define CPU_DBGCPUXCOMMRXFULL   (GIC_PPI_START + 8)
 
#define CPU_DBGCPUXCOMMTXEMPTY   (GIC_PPI_START + 9)
 
#define CPU_SICCPUXPERFMONIRPTREQ   (GIC_PPI_START + 10)
 
#define SC_AVSCPUXDOWN   (GIC_PPI_START + 11)
 
#define SC_AVSCPUXUP   (GIC_PPI_START + 12)
 
#define SC_SICCPUXACGIRPTREQ   (GIC_PPI_START + 13)
 
#define SC_SICCPUXEXTFAULTIRPTREQ   (GIC_PPI_START + 14)
 
#define SC_SICMPUIRPTREQ   (GIC_SPI_START + 0)
 
#define SC_SICL2IRPTREQ   (GIC_SPI_START + 1)
 
#define SC_SICL2PERFMONIRPTREQ   (GIC_SPI_START + 2)
 
#define SC_SICAGCIRPTREQ   (GIC_SPI_START + 3)
 
#define TLMM_APCC_DIR_CONN_IRQ_0   (GIC_SPI_START + 4)
 
#define TLMM_APCC_DIR_CONN_IRQ_1   (GIC_SPI_START + 5)
 
#define TLMM_APCC_DIR_CONN_IRQ_2   (GIC_SPI_START + 6)
 
#define TLMM_APCC_DIR_CONN_IRQ_3   (GIC_SPI_START + 7)
 
#define TLMM_APCC_DIR_CONN_IRQ_4   (GIC_SPI_START + 8)
 
#define TLMM_APCC_DIR_CONN_IRQ_5   (GIC_SPI_START + 9)
 
#define TLMM_APCC_DIR_CONN_IRQ_6   (GIC_SPI_START + 10)
 
#define TLMM_APCC_DIR_CONN_IRQ_7   (GIC_SPI_START + 11)
 
#define TLMM_APCC_DIR_CONN_IRQ_8   (GIC_SPI_START + 12)
 
#define TLMM_APCC_DIR_CONN_IRQ_9   (GIC_SPI_START + 13)
 
#define PM8921_SEC_IRQ_103   (GIC_SPI_START + 14)
 
#define PM8018_SEC_IRQ_106   (GIC_SPI_START + 15)
 
#define TLMM_APCC_SUMMARY_IRQ   (GIC_SPI_START + 16)
 
#define SPDM_RT_1_IRQ   (GIC_SPI_START + 17)
 
#define SPDM_DIAG_IRQ   (GIC_SPI_START + 18)
 
#define RPM_APCC_CPU0_GP_HIGH_IRQ   (GIC_SPI_START + 19)
 
#define RPM_APCC_CPU0_GP_MEDIUM_IRQ   (GIC_SPI_START + 20)
 
#define RPM_APCC_CPU0_GP_LOW_IRQ   (GIC_SPI_START + 21)
 
#define RPM_APCC_CPU0_WAKE_UP_IRQ   (GIC_SPI_START + 22)
 
#define RPM_APCC_CPU1_GP_HIGH_IRQ   (GIC_SPI_START + 23)
 
#define RPM_APCC_CPU1_GP_MEDIUM_IRQ   (GIC_SPI_START + 24)
 
#define RPM_APCC_CPU1_GP_LOW_IRQ   (GIC_SPI_START + 25)
 
#define RPM_APCC_CPU1_WAKE_UP_IRQ   (GIC_SPI_START + 26)
 
#define SSBI2_2_SC_CPU0_SECURE_IRQ   (GIC_SPI_START + 27)
 
#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ   (GIC_SPI_START + 28)
 
#define SSBI2_1_SC_CPU0_SECURE_IRQ   (GIC_SPI_START + 29)
 
#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ   (GIC_SPI_START + 30)
 
#define MSMC_SC_SEC_CE_IRQ   (GIC_SPI_START + 31)
 
#define MSMC_SC_PRI_CE_IRQ   (GIC_SPI_START + 32)
 
#define SLIMBUS0_CORE_EE1_IRQ   (GIC_SPI_START + 33)
 
#define SLIMBUS0_BAM_EE1_IRQ   (GIC_SPI_START + 34)
 
#define Q6FW_WDOG_EXPIRED_IRQ   (GIC_SPI_START + 35)
 
#define Q6SW_WDOG_EXPIRED_IRQ   (GIC_SPI_START + 36)
 
#define MSS_TO_APPS_IRQ_0   (GIC_SPI_START + 37)
 
#define MSS_TO_APPS_IRQ_1   (GIC_SPI_START + 38)
 
#define MSS_TO_APPS_IRQ_2   (GIC_SPI_START + 39)
 
#define MSS_TO_APPS_IRQ_3   (GIC_SPI_START + 40)
 
#define MSS_TO_APPS_IRQ_4   (GIC_SPI_START + 41)
 
#define MSS_TO_APPS_IRQ_5   (GIC_SPI_START + 42)
 
#define MSS_TO_APPS_IRQ_6   (GIC_SPI_START + 43)
 
#define MSS_TO_APPS_IRQ_7   (GIC_SPI_START + 44)
 
#define MSS_TO_APPS_IRQ_8   (GIC_SPI_START + 45)
 
#define MSS_TO_APPS_IRQ_9   (GIC_SPI_START + 46)
 
#define VPE_IRQ   (GIC_SPI_START + 47)
 
#define VFE_IRQ   (GIC_SPI_START + 48)
 
#define VCODEC_IRQ   (GIC_SPI_START + 49)
 
#define TV_ENC_IRQ   (GIC_SPI_START + 50)
 
#define SMMU_VPE_CB_SC_SECURE_IRQ   (GIC_SPI_START + 51)
 
#define SMMU_VPE_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 52)
 
#define SMMU_VFE_CB_SC_SECURE_IRQ   (GIC_SPI_START + 53)
 
#define SMMU_VFE_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 54)
 
#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ   (GIC_SPI_START + 55)
 
#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 56)
 
#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ   (GIC_SPI_START + 57)
 
#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 58)
 
#define SMMU_ROT_CB_SC_SECURE_IRQ   (GIC_SPI_START + 59)
 
#define SMMU_ROT_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 60)
 
#define SMMU_MDP1_CB_SC_SECURE_IRQ   (GIC_SPI_START + 61)
 
#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 62)
 
#define SMMU_MDP0_CB_SC_SECURE_IRQ   (GIC_SPI_START + 63)
 
#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 64)
 
#define SMMU_JPEGD_CB_SC_SECURE_IRQ   (GIC_SPI_START + 65)
 
#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 66)
 
#define SMMU_IJPEG_CB_SC_SECURE_IRQ   (GIC_SPI_START + 67)
 
#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 68)
 
#define SMMU_GFX3D_CB_SC_SECURE_IRQ   (GIC_SPI_START + 69)
 
#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 70)
 
#define SMMU_GFX2D0_CB_SC_SECURE_IRQ   (GIC_SPI_START + 71)
 
#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 72)
 
#define ROT_IRQ   (GIC_SPI_START + 73)
 
#define MMSS_FABRIC_IRQ   (GIC_SPI_START + 74)
 
#define MDP_IRQ   (GIC_SPI_START + 75)
 
#define JPEGD_IRQ   (GIC_SPI_START + 76)
 
#define JPEG_IRQ   (GIC_SPI_START + 77)
 
#define MMSS_IMEM_IRQ   (GIC_SPI_START + 78)
 
#define HDMI_IRQ   (GIC_SPI_START + 79)
 
#define GFX3D_IRQ   (GIC_SPI_START + 80)
 
#define GFX2D0_IRQ   (GIC_SPI_START + 81)
 
#define DSI1_IRQ   (GIC_SPI_START + 82)
 
#define CSI_1_IRQ   (GIC_SPI_START + 83)
 
#define CSI_0_IRQ   (GIC_SPI_START + 84)
 
#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ   (GIC_SPI_START + 85)
 
#define LPASS_SCSS_MIDI_IRQ   (GIC_SPI_START + 86)
 
#define LPASS_Q6SS_WDOG_EXPIRED   (GIC_SPI_START + 87)
 
#define LPASS_SCSS_GP_LOW_IRQ   (GIC_SPI_START + 88)
 
#define LPASS_SCSS_GP_MEDIUM_IRQ   (GIC_SPI_START + 89)
 
#define LPASS_SCSS_GP_HIGH_IRQ   (GIC_SPI_START + 90)
 
#define TOP_IMEM_IRQ   (GIC_SPI_START + 91)
 
#define FABRIC_SYS_IRQ   (GIC_SPI_START + 92)
 
#define FABRIC_APPS_IRQ   (GIC_SPI_START + 93)
 
#define USB1_HS_BAM_IRQ   (GIC_SPI_START + 94)
 
#define SDC4_BAM_IRQ   (GIC_SPI_START + 95)
 
#define SDC3_BAM_IRQ   (GIC_SPI_START + 96)
 
#define SDC2_BAM_IRQ   (GIC_SPI_START + 97)
 
#define SDC1_BAM_IRQ   (GIC_SPI_START + 98)
 
#define FABRIC_SPS_IRQ   (GIC_SPI_START + 99)
 
#define USB1_HS_IRQ   (GIC_SPI_START + 100)
 
#define SDC4_IRQ_0   (GIC_SPI_START + 101)
 
#define SDC3_IRQ_0   (GIC_SPI_START + 102)
 
#define SDC2_IRQ_0   (GIC_SPI_START + 103)
 
#define SDC1_IRQ_0   (GIC_SPI_START + 104)
 
#define SPS_BAM_DMA_IRQ   (GIC_SPI_START + 105)
 
#define SPS_SEC_VIOL_IRQ   (GIC_SPI_START + 106)
 
#define SPS_MTI_0   (GIC_SPI_START + 107)
 
#define SPS_MTI_1   (GIC_SPI_START + 108)
 
#define SPS_MTI_2   (GIC_SPI_START + 109)
 
#define SPS_MTI_3   (GIC_SPI_START + 110)
 
#define SPS_MTI_4   (GIC_SPI_START + 111)
 
#define SPS_MTI_5   (GIC_SPI_START + 112)
 
#define SPS_MTI_6   (GIC_SPI_START + 113)
 
#define SPS_MTI_7   (GIC_SPI_START + 114)
 
#define SPS_MTI_8   (GIC_SPI_START + 115)
 
#define SPS_MTI_9   (GIC_SPI_START + 116)
 
#define SPS_MTI_10   (GIC_SPI_START + 117)
 
#define SPS_MTI_11   (GIC_SPI_START + 118)
 
#define SPS_MTI_12   (GIC_SPI_START + 119)
 
#define SPS_MTI_13   (GIC_SPI_START + 120)
 
#define SPS_MTI_14   (GIC_SPI_START + 121)
 
#define SPS_MTI_15   (GIC_SPI_START + 122)
 
#define SPS_MTI_16   (GIC_SPI_START + 123)
 
#define SPS_MTI_17   (GIC_SPI_START + 124)
 
#define SPS_MTI_18   (GIC_SPI_START + 125)
 
#define SPS_MTI_19   (GIC_SPI_START + 126)
 
#define SPS_MTI_20   (GIC_SPI_START + 127)
 
#define SPS_MTI_21   (GIC_SPI_START + 128)
 
#define SPS_MTI_22   (GIC_SPI_START + 129)
 
#define SPS_MTI_23   (GIC_SPI_START + 130)
 
#define SPS_MTI_24   (GIC_SPI_START + 131)
 
#define SPS_MTI_25   (GIC_SPI_START + 132)
 
#define SPS_MTI_26   (GIC_SPI_START + 133)
 
#define SPS_MTI_27   (GIC_SPI_START + 134)
 
#define SPS_MTI_28   (GIC_SPI_START + 135)
 
#define SPS_MTI_29   (GIC_SPI_START + 136)
 
#define SPS_MTI_30   (GIC_SPI_START + 137)
 
#define SPS_MTI_31   (GIC_SPI_START + 138)
 
#define CSIPHY_4LN_IRQ   (GIC_SPI_START + 139)
 
#define CSIPHY_2LN_IRQ   (GIC_SPI_START + 140)
 
#define USB2_IRQ   (GIC_SPI_START + 141)
 
#define USB1_IRQ   (GIC_SPI_START + 142)
 
#define TSSC_SSBI_IRQ   (GIC_SPI_START + 143)
 
#define TSSC_SAMPLE_IRQ   (GIC_SPI_START + 144)
 
#define TSSC_PENUP_IRQ   (GIC_SPI_START + 145)
 
#define GSBI1_UARTDM_IRQ   (GIC_SPI_START + 146)
 
#define GSBI1_QUP_IRQ   (GIC_SPI_START + 147)
 
#define GSBI2_UARTDM_IRQ   (GIC_SPI_START + 148)
 
#define GSBI2_QUP_IRQ   (GIC_SPI_START + 149)
 
#define GSBI3_UARTDM_IRQ   (GIC_SPI_START + 150)
 
#define GSBI3_QUP_IRQ   (GIC_SPI_START + 151)
 
#define GSBI4_UARTDM_IRQ   (GIC_SPI_START + 152)
 
#define GSBI4_QUP_IRQ   (GIC_SPI_START + 153)
 
#define GSBI5_UARTDM_IRQ   (GIC_SPI_START + 154)
 
#define GSBI5_QUP_IRQ   (GIC_SPI_START + 155)
 
#define GSBI6_UARTDM_IRQ   (GIC_SPI_START + 156)
 
#define GSBI6_QUP_IRQ   (GIC_SPI_START + 157)
 
#define GSBI7_UARTDM_IRQ   (GIC_SPI_START + 158)
 
#define GSBI7_QUP_IRQ   (GIC_SPI_START + 159)
 
#define GSBI8_UARTDM_IRQ   (GIC_SPI_START + 160)
 
#define GSBI8_QUP_IRQ   (GIC_SPI_START + 161)
 
#define TSIF_TSPP_IRQ   (GIC_SPI_START + 162)
 
#define TSIF_BAM_IRQ   (GIC_SPI_START + 163)
 
#define TSIF2_IRQ   (GIC_SPI_START + 164)
 
#define TSIF1_IRQ   (GIC_SPI_START + 165)
 
#define DSI2_IRQ   (GIC_SPI_START + 166)
 
#define ISPIF_IRQ   (GIC_SPI_START + 167)
 
#define MSMC_SC_SEC_TMR_IRQ   (GIC_SPI_START + 168)
 
#define MSMC_SC_SEC_WDOG_BARK_IRQ   (GIC_SPI_START + 169)
 
#define INT_ADM0_SCSS_0_IRQ   (GIC_SPI_START + 170)
 
#define INT_ADM0_SCSS_1_IRQ   (GIC_SPI_START + 171)
 
#define INT_ADM0_SCSS_2_IRQ   (GIC_SPI_START + 172)
 
#define INT_ADM0_SCSS_3_IRQ   (GIC_SPI_START + 173)
 
#define CC_SCSS_WDT1CPU1BITEEXPIRED   (GIC_SPI_START + 174)
 
#define CC_SCSS_WDT1CPU0BITEEXPIRED   (GIC_SPI_START + 175)
 
#define CC_SCSS_WDT0CPU1BITEEXPIRED   (GIC_SPI_START + 176)
 
#define CC_SCSS_WDT0CPU0BITEEXPIRED   (GIC_SPI_START + 177)
 
#define TSENS_UPPER_LOWER_INT   (GIC_SPI_START + 178)
 
#define SSBI2_2_SC_CPU1_SECURE_INT   (GIC_SPI_START + 179)
 
#define SSBI2_2_SC_CPU1_NON_SECURE_INT   (GIC_SPI_START + 180)
 
#define SSBI2_1_SC_CPU1_SECURE_INT   (GIC_SPI_START + 181)
 
#define SSBI2_1_SC_CPU1_NON_SECURE_INT   (GIC_SPI_START + 182)
 
#define XPU_SUMMARY_IRQ   (GIC_SPI_START + 183)
 
#define BUS_EXCEPTION_SUMMARY_IRQ   (GIC_SPI_START + 184)
 
#define HSDDRX_EBI1CH0_IRQ   (GIC_SPI_START + 185)
 
#define HSDDRX_EBI1CH1_IRQ   (GIC_SPI_START + 186)
 
#define SDC5_BAM_IRQ   (GIC_SPI_START + 187)
 
#define SDC5_IRQ_0   (GIC_SPI_START + 188)
 
#define GSBI9_UARTDM_IRQ   (GIC_SPI_START + 189)
 
#define GSBI9_QUP_IRQ   (GIC_SPI_START + 190)
 
#define GSBI10_UARTDM_IRQ   (GIC_SPI_START + 191)
 
#define GSBI10_QUP_IRQ   (GIC_SPI_START + 192)
 
#define GSBI11_UARTDM_IRQ   (GIC_SPI_START + 193)
 
#define GSBI11_QUP_IRQ   (GIC_SPI_START + 194)
 
#define GSBI12_UARTDM_IRQ   (GIC_SPI_START + 195)
 
#define GSBI12_QUP_IRQ   (GIC_SPI_START + 196)
 
#define RIVA_APSS_LTECOEX_IRQ   (GIC_SPI_START + 197)
 
#define RIVA_APSS_SPARE_IRQ   (GIC_SPI_START + 198)
 
#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ   (GIC_SPI_START + 199)
 
#define RIVA_ASS_RESET_DONE_IRQ   (GIC_SPI_START + 200)
 
#define RIVA_APSS_ASIC_IRQ   (GIC_SPI_START + 201)
 
#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ   (GIC_SPI_START + 202)
 
#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ   (GIC_SPI_START + 203)
 
#define RIVA_APPS_WLAM_SMSM_IRQ   (GIC_SPI_START + 204)
 
#define RIVA_APPS_LOG_CTRL_IRQ   (GIC_SPI_START + 205)
 
#define RIVA_APPS_FM_CTRL_IRQ   (GIC_SPI_START + 206)
 
#define RIVA_APPS_HCI_IRQ   (GIC_SPI_START + 207)
 
#define RIVA_APPS_WLAN_CTRL_IRQ   (GIC_SPI_START + 208)
 
#define A2_BAM_IRQ   (GIC_SPI_START + 209)
 
#define SMMU_GFX2D1_CB_SC_SECURE_IRQ   (GIC_SPI_START + 210)
 
#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 211)
 
#define GFX2D1_IRQ   (GIC_SPI_START + 212)
 
#define PPSS_WDOG_TIMER_IRQ   (GIC_SPI_START + 213)
 
#define SPS_SLIMBUS_CORE_EE0_IRQ   (GIC_SPI_START + 214)
 
#define SPS_SLIMBUS_BAM_EE0_IRQ   (GIC_SPI_START + 215)
 
#define QDSS_ETB_IRQ   (GIC_SPI_START + 216)
 
#define QDSS_CTI2KPSS_CPU1_IRQ   (GIC_SPI_START + 217)
 
#define QDSS_CTI2KPSS_CPU0_IRQ   (GIC_SPI_START + 218)
 
#define TLMM_APCC_DIR_CONN_IRQ_16   (GIC_SPI_START + 219)
 
#define TLMM_APCC_DIR_CONN_IRQ_17   (GIC_SPI_START + 220)
 
#define TLMM_APCC_DIR_CONN_IRQ_18   (GIC_SPI_START + 221)
 
#define TLMM_APCC_DIR_CONN_IRQ_19   (GIC_SPI_START + 222)
 
#define TLMM_APCC_DIR_CONN_IRQ_20   (GIC_SPI_START + 223)
 
#define TLMM_APCC_DIR_CONN_IRQ_21   (GIC_SPI_START + 224)
 
#define PM8921_SEC_IRQ_104   (GIC_SPI_START + 225)
 
#define PM8018_SEC_IRQ_107   (GIC_SPI_START + 226)
 
#define NR_MSM_IRQS   1020
 
#define NR_BOARD_IRQS   0
 
#define NR_GPIO_IRQS   0
 

Macro Definition Documentation

#define A2_BAM_IRQ   (GIC_SPI_START + 209)

Definition at line 251 of file irqs-8960.h.

#define AVS_SVICINT   (GIC_PPI_START + 6)

Definition at line 31 of file irqs-8960.h.

#define AVS_SVICINTSWDONE   (GIC_PPI_START + 7)

Definition at line 32 of file irqs-8960.h.

#define BUS_EXCEPTION_SUMMARY_IRQ   (GIC_SPI_START + 184)

Definition at line 226 of file irqs-8960.h.

#define CC_SCSS_WDT0CPU0BITEEXPIRED   (GIC_SPI_START + 177)

Definition at line 219 of file irqs-8960.h.

#define CC_SCSS_WDT0CPU1BITEEXPIRED   (GIC_SPI_START + 176)

Definition at line 218 of file irqs-8960.h.

#define CC_SCSS_WDT1CPU0BITEEXPIRED   (GIC_SPI_START + 175)

Definition at line 217 of file irqs-8960.h.

#define CC_SCSS_WDT1CPU1BITEEXPIRED   (GIC_SPI_START + 174)

Definition at line 216 of file irqs-8960.h.

#define CPU_DBGCPUXCOMMRXFULL   (GIC_PPI_START + 8)

Definition at line 33 of file irqs-8960.h.

#define CPU_DBGCPUXCOMMTXEMPTY   (GIC_PPI_START + 9)

Definition at line 34 of file irqs-8960.h.

#define CPU_SICCPUXPERFMONIRPTREQ   (GIC_PPI_START + 10)

Definition at line 35 of file irqs-8960.h.

#define CSI_0_IRQ   (GIC_SPI_START + 84)

Definition at line 126 of file irqs-8960.h.

#define CSI_1_IRQ   (GIC_SPI_START + 83)

Definition at line 125 of file irqs-8960.h.

#define CSIPHY_2LN_IRQ   (GIC_SPI_START + 140)

Definition at line 182 of file irqs-8960.h.

#define CSIPHY_4LN_IRQ   (GIC_SPI_START + 139)

Definition at line 181 of file irqs-8960.h.

#define DSI1_IRQ   (GIC_SPI_START + 82)

Definition at line 124 of file irqs-8960.h.

#define DSI2_IRQ   (GIC_SPI_START + 166)

Definition at line 208 of file irqs-8960.h.

#define FABRIC_APPS_IRQ   (GIC_SPI_START + 93)

Definition at line 135 of file irqs-8960.h.

#define FABRIC_SPS_IRQ   (GIC_SPI_START + 99)

Definition at line 141 of file irqs-8960.h.

#define FABRIC_SYS_IRQ   (GIC_SPI_START + 92)

Definition at line 134 of file irqs-8960.h.

#define GFX2D0_IRQ   (GIC_SPI_START + 81)

Definition at line 123 of file irqs-8960.h.

#define GFX2D1_IRQ   (GIC_SPI_START + 212)

Definition at line 254 of file irqs-8960.h.

#define GFX3D_IRQ   (GIC_SPI_START + 80)

Definition at line 122 of file irqs-8960.h.

#define GIC_PPI_START   16

Definition at line 22 of file irqs-8960.h.

#define GIC_SPI_START   32

Definition at line 23 of file irqs-8960.h.

#define GSBI10_QUP_IRQ   (GIC_SPI_START + 192)

Definition at line 234 of file irqs-8960.h.

#define GSBI10_UARTDM_IRQ   (GIC_SPI_START + 191)

Definition at line 233 of file irqs-8960.h.

#define GSBI11_QUP_IRQ   (GIC_SPI_START + 194)

Definition at line 236 of file irqs-8960.h.

#define GSBI11_UARTDM_IRQ   (GIC_SPI_START + 193)

Definition at line 235 of file irqs-8960.h.

#define GSBI12_QUP_IRQ   (GIC_SPI_START + 196)

Definition at line 238 of file irqs-8960.h.

#define GSBI12_UARTDM_IRQ   (GIC_SPI_START + 195)

Definition at line 237 of file irqs-8960.h.

#define GSBI1_QUP_IRQ   (GIC_SPI_START + 147)

Definition at line 189 of file irqs-8960.h.

#define GSBI1_UARTDM_IRQ   (GIC_SPI_START + 146)

Definition at line 188 of file irqs-8960.h.

#define GSBI2_QUP_IRQ   (GIC_SPI_START + 149)

Definition at line 191 of file irqs-8960.h.

#define GSBI2_UARTDM_IRQ   (GIC_SPI_START + 148)

Definition at line 190 of file irqs-8960.h.

#define GSBI3_QUP_IRQ   (GIC_SPI_START + 151)

Definition at line 193 of file irqs-8960.h.

#define GSBI3_UARTDM_IRQ   (GIC_SPI_START + 150)

Definition at line 192 of file irqs-8960.h.

#define GSBI4_QUP_IRQ   (GIC_SPI_START + 153)

Definition at line 195 of file irqs-8960.h.

#define GSBI4_UARTDM_IRQ   (GIC_SPI_START + 152)

Definition at line 194 of file irqs-8960.h.

#define GSBI5_QUP_IRQ   (GIC_SPI_START + 155)

Definition at line 197 of file irqs-8960.h.

#define GSBI5_UARTDM_IRQ   (GIC_SPI_START + 154)

Definition at line 196 of file irqs-8960.h.

#define GSBI6_QUP_IRQ   (GIC_SPI_START + 157)

Definition at line 199 of file irqs-8960.h.

#define GSBI6_UARTDM_IRQ   (GIC_SPI_START + 156)

Definition at line 198 of file irqs-8960.h.

#define GSBI7_QUP_IRQ   (GIC_SPI_START + 159)

Definition at line 201 of file irqs-8960.h.

#define GSBI7_UARTDM_IRQ   (GIC_SPI_START + 158)

Definition at line 200 of file irqs-8960.h.

#define GSBI8_QUP_IRQ   (GIC_SPI_START + 161)

Definition at line 203 of file irqs-8960.h.

#define GSBI8_UARTDM_IRQ   (GIC_SPI_START + 160)

Definition at line 202 of file irqs-8960.h.

#define GSBI9_QUP_IRQ   (GIC_SPI_START + 190)

Definition at line 232 of file irqs-8960.h.

#define GSBI9_UARTDM_IRQ   (GIC_SPI_START + 189)

Definition at line 231 of file irqs-8960.h.

#define HDMI_IRQ   (GIC_SPI_START + 79)

Definition at line 121 of file irqs-8960.h.

#define HSDDRX_EBI1CH0_IRQ   (GIC_SPI_START + 185)

Definition at line 227 of file irqs-8960.h.

#define HSDDRX_EBI1CH1_IRQ   (GIC_SPI_START + 186)

Definition at line 228 of file irqs-8960.h.

#define INT_ADM0_SCSS_0_IRQ   (GIC_SPI_START + 170)

Definition at line 212 of file irqs-8960.h.

#define INT_ADM0_SCSS_1_IRQ   (GIC_SPI_START + 171)

Definition at line 213 of file irqs-8960.h.

#define INT_ADM0_SCSS_2_IRQ   (GIC_SPI_START + 172)

Definition at line 214 of file irqs-8960.h.

#define INT_ADM0_SCSS_3_IRQ   (GIC_SPI_START + 173)

Definition at line 215 of file irqs-8960.h.

#define INT_DEBUG_TIMER_EXP   (GIC_PPI_START + 1)

Definition at line 26 of file irqs-8960.h.

#define INT_GP_TIMER2_EXP   (GIC_PPI_START + 3)

Definition at line 28 of file irqs-8960.h.

#define INT_GP_TIMER_EXP   (GIC_PPI_START + 2)

Definition at line 27 of file irqs-8960.h.

#define INT_VGIC   (GIC_PPI_START + 0)

Definition at line 25 of file irqs-8960.h.

#define ISPIF_IRQ   (GIC_SPI_START + 167)

Definition at line 209 of file irqs-8960.h.

#define JPEG_IRQ   (GIC_SPI_START + 77)

Definition at line 119 of file irqs-8960.h.

#define JPEGD_IRQ   (GIC_SPI_START + 76)

Definition at line 118 of file irqs-8960.h.

#define LPASS_Q6SS_WDOG_EXPIRED   (GIC_SPI_START + 87)

Definition at line 129 of file irqs-8960.h.

#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ   (GIC_SPI_START + 85)

Definition at line 127 of file irqs-8960.h.

#define LPASS_SCSS_GP_HIGH_IRQ   (GIC_SPI_START + 90)

Definition at line 132 of file irqs-8960.h.

#define LPASS_SCSS_GP_LOW_IRQ   (GIC_SPI_START + 88)

Definition at line 130 of file irqs-8960.h.

#define LPASS_SCSS_GP_MEDIUM_IRQ   (GIC_SPI_START + 89)

Definition at line 131 of file irqs-8960.h.

#define LPASS_SCSS_MIDI_IRQ   (GIC_SPI_START + 86)

Definition at line 128 of file irqs-8960.h.

#define MDP_IRQ   (GIC_SPI_START + 75)

Definition at line 117 of file irqs-8960.h.

#define MMSS_FABRIC_IRQ   (GIC_SPI_START + 74)

Definition at line 116 of file irqs-8960.h.

#define MMSS_IMEM_IRQ   (GIC_SPI_START + 78)

Definition at line 120 of file irqs-8960.h.

#define MSMC_SC_PRI_CE_IRQ   (GIC_SPI_START + 32)

Definition at line 74 of file irqs-8960.h.

#define MSMC_SC_SEC_CE_IRQ   (GIC_SPI_START + 31)

Definition at line 73 of file irqs-8960.h.

#define MSMC_SC_SEC_TMR_IRQ   (GIC_SPI_START + 168)

Definition at line 210 of file irqs-8960.h.

#define MSMC_SC_SEC_WDOG_BARK_IRQ   (GIC_SPI_START + 169)

Definition at line 211 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_0   (GIC_SPI_START + 37)

Definition at line 79 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_1   (GIC_SPI_START + 38)

Definition at line 80 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_2   (GIC_SPI_START + 39)

Definition at line 81 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_3   (GIC_SPI_START + 40)

Definition at line 82 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_4   (GIC_SPI_START + 41)

Definition at line 83 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_5   (GIC_SPI_START + 42)

Definition at line 84 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_6   (GIC_SPI_START + 43)

Definition at line 85 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_7   (GIC_SPI_START + 44)

Definition at line 86 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_8   (GIC_SPI_START + 45)

Definition at line 87 of file irqs-8960.h.

#define MSS_TO_APPS_IRQ_9   (GIC_SPI_START + 46)

Definition at line 88 of file irqs-8960.h.

#define NR_BOARD_IRQS   0

Definition at line 273 of file irqs-8960.h.

#define NR_GPIO_IRQS   0

Definition at line 274 of file irqs-8960.h.

#define NR_MSM_IRQS   1020

Definition at line 272 of file irqs-8960.h.

#define PM8018_SEC_IRQ_106   (GIC_SPI_START + 15)

Definition at line 57 of file irqs-8960.h.

#define PM8018_SEC_IRQ_107   (GIC_SPI_START + 226)

Definition at line 268 of file irqs-8960.h.

#define PM8921_SEC_IRQ_103   (GIC_SPI_START + 14)

Definition at line 56 of file irqs-8960.h.

#define PM8921_SEC_IRQ_104   (GIC_SPI_START + 225)

Definition at line 267 of file irqs-8960.h.

#define PPSS_WDOG_TIMER_IRQ   (GIC_SPI_START + 213)

Definition at line 255 of file irqs-8960.h.

#define Q6FW_WDOG_EXPIRED_IRQ   (GIC_SPI_START + 35)

Definition at line 77 of file irqs-8960.h.

#define Q6SW_WDOG_EXPIRED_IRQ   (GIC_SPI_START + 36)

Definition at line 78 of file irqs-8960.h.

#define QDSS_CTI2KPSS_CPU0_IRQ   (GIC_SPI_START + 218)

Definition at line 260 of file irqs-8960.h.

#define QDSS_CTI2KPSS_CPU1_IRQ   (GIC_SPI_START + 217)

Definition at line 259 of file irqs-8960.h.

#define QDSS_ETB_IRQ   (GIC_SPI_START + 216)

Definition at line 258 of file irqs-8960.h.

#define RIVA_APPS_FM_CTRL_IRQ   (GIC_SPI_START + 206)

Definition at line 248 of file irqs-8960.h.

#define RIVA_APPS_HCI_IRQ   (GIC_SPI_START + 207)

Definition at line 249 of file irqs-8960.h.

#define RIVA_APPS_LOG_CTRL_IRQ   (GIC_SPI_START + 205)

Definition at line 247 of file irqs-8960.h.

#define RIVA_APPS_WLAM_SMSM_IRQ   (GIC_SPI_START + 204)

Definition at line 246 of file irqs-8960.h.

#define RIVA_APPS_WLAN_CTRL_IRQ   (GIC_SPI_START + 208)

Definition at line 250 of file irqs-8960.h.

#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ   (GIC_SPI_START + 203)

Definition at line 245 of file irqs-8960.h.

#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ   (GIC_SPI_START + 202)

Definition at line 244 of file irqs-8960.h.

#define RIVA_APSS_ASIC_IRQ   (GIC_SPI_START + 201)

Definition at line 243 of file irqs-8960.h.

#define RIVA_APSS_LTECOEX_IRQ   (GIC_SPI_START + 197)

Definition at line 239 of file irqs-8960.h.

#define RIVA_APSS_SPARE_IRQ   (GIC_SPI_START + 198)

Definition at line 240 of file irqs-8960.h.

#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ   (GIC_SPI_START + 199)

Definition at line 241 of file irqs-8960.h.

#define RIVA_ASS_RESET_DONE_IRQ   (GIC_SPI_START + 200)

Definition at line 242 of file irqs-8960.h.

#define ROT_IRQ   (GIC_SPI_START + 73)

Definition at line 115 of file irqs-8960.h.

#define RPM_APCC_CPU0_GP_HIGH_IRQ   (GIC_SPI_START + 19)

Definition at line 61 of file irqs-8960.h.

#define RPM_APCC_CPU0_GP_LOW_IRQ   (GIC_SPI_START + 21)

Definition at line 63 of file irqs-8960.h.

#define RPM_APCC_CPU0_GP_MEDIUM_IRQ   (GIC_SPI_START + 20)

Definition at line 62 of file irqs-8960.h.

#define RPM_APCC_CPU0_WAKE_UP_IRQ   (GIC_SPI_START + 22)

Definition at line 64 of file irqs-8960.h.

#define RPM_APCC_CPU1_GP_HIGH_IRQ   (GIC_SPI_START + 23)

Definition at line 65 of file irqs-8960.h.

#define RPM_APCC_CPU1_GP_LOW_IRQ   (GIC_SPI_START + 25)

Definition at line 67 of file irqs-8960.h.

#define RPM_APCC_CPU1_GP_MEDIUM_IRQ   (GIC_SPI_START + 24)

Definition at line 66 of file irqs-8960.h.

#define RPM_APCC_CPU1_WAKE_UP_IRQ   (GIC_SPI_START + 26)

Definition at line 68 of file irqs-8960.h.

#define SC_AVSCPUXDOWN   (GIC_PPI_START + 11)

Definition at line 36 of file irqs-8960.h.

#define SC_AVSCPUXUP   (GIC_PPI_START + 12)

Definition at line 37 of file irqs-8960.h.

#define SC_SICAGCIRPTREQ   (GIC_SPI_START + 3)

Definition at line 45 of file irqs-8960.h.

#define SC_SICCPUXACGIRPTREQ   (GIC_PPI_START + 13)

Definition at line 38 of file irqs-8960.h.

#define SC_SICCPUXEXTFAULTIRPTREQ   (GIC_PPI_START + 14)

Definition at line 39 of file irqs-8960.h.

#define SC_SICL2IRPTREQ   (GIC_SPI_START + 1)

Definition at line 43 of file irqs-8960.h.

#define SC_SICL2PERFMONIRPTREQ   (GIC_SPI_START + 2)

Definition at line 44 of file irqs-8960.h.

#define SC_SICMPUIRPTREQ   (GIC_SPI_START + 0)

Definition at line 42 of file irqs-8960.h.

#define SDC1_BAM_IRQ   (GIC_SPI_START + 98)

Definition at line 140 of file irqs-8960.h.

#define SDC1_IRQ_0   (GIC_SPI_START + 104)

Definition at line 146 of file irqs-8960.h.

#define SDC2_BAM_IRQ   (GIC_SPI_START + 97)

Definition at line 139 of file irqs-8960.h.

#define SDC2_IRQ_0   (GIC_SPI_START + 103)

Definition at line 145 of file irqs-8960.h.

#define SDC3_BAM_IRQ   (GIC_SPI_START + 96)

Definition at line 138 of file irqs-8960.h.

#define SDC3_IRQ_0   (GIC_SPI_START + 102)

Definition at line 144 of file irqs-8960.h.

#define SDC4_BAM_IRQ   (GIC_SPI_START + 95)

Definition at line 137 of file irqs-8960.h.

#define SDC4_IRQ_0   (GIC_SPI_START + 101)

Definition at line 143 of file irqs-8960.h.

#define SDC5_BAM_IRQ   (GIC_SPI_START + 187)

Definition at line 229 of file irqs-8960.h.

#define SDC5_IRQ_0   (GIC_SPI_START + 188)

Definition at line 230 of file irqs-8960.h.

#define SLIMBUS0_BAM_EE1_IRQ   (GIC_SPI_START + 34)

Definition at line 76 of file irqs-8960.h.

#define SLIMBUS0_CORE_EE1_IRQ   (GIC_SPI_START + 33)

Definition at line 75 of file irqs-8960.h.

#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 72)

Definition at line 114 of file irqs-8960.h.

#define SMMU_GFX2D0_CB_SC_SECURE_IRQ   (GIC_SPI_START + 71)

Definition at line 113 of file irqs-8960.h.

#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 211)

Definition at line 253 of file irqs-8960.h.

#define SMMU_GFX2D1_CB_SC_SECURE_IRQ   (GIC_SPI_START + 210)

Definition at line 252 of file irqs-8960.h.

#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 70)

Definition at line 112 of file irqs-8960.h.

#define SMMU_GFX3D_CB_SC_SECURE_IRQ   (GIC_SPI_START + 69)

Definition at line 111 of file irqs-8960.h.

#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 68)

Definition at line 110 of file irqs-8960.h.

#define SMMU_IJPEG_CB_SC_SECURE_IRQ   (GIC_SPI_START + 67)

Definition at line 109 of file irqs-8960.h.

#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 66)

Definition at line 108 of file irqs-8960.h.

#define SMMU_JPEGD_CB_SC_SECURE_IRQ   (GIC_SPI_START + 65)

Definition at line 107 of file irqs-8960.h.

#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 64)

Definition at line 106 of file irqs-8960.h.

#define SMMU_MDP0_CB_SC_SECURE_IRQ   (GIC_SPI_START + 63)

Definition at line 105 of file irqs-8960.h.

#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 62)

Definition at line 104 of file irqs-8960.h.

#define SMMU_MDP1_CB_SC_SECURE_IRQ   (GIC_SPI_START + 61)

Definition at line 103 of file irqs-8960.h.

#define SMMU_ROT_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 60)

Definition at line 102 of file irqs-8960.h.

#define SMMU_ROT_CB_SC_SECURE_IRQ   (GIC_SPI_START + 59)

Definition at line 101 of file irqs-8960.h.

#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 58)

Definition at line 100 of file irqs-8960.h.

#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ   (GIC_SPI_START + 57)

Definition at line 99 of file irqs-8960.h.

#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 56)

Definition at line 98 of file irqs-8960.h.

#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ   (GIC_SPI_START + 55)

Definition at line 97 of file irqs-8960.h.

#define SMMU_VFE_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 54)

Definition at line 96 of file irqs-8960.h.

#define SMMU_VFE_CB_SC_SECURE_IRQ   (GIC_SPI_START + 53)

Definition at line 95 of file irqs-8960.h.

#define SMMU_VPE_CB_SC_NON_SECURE_IRQ   (GIC_SPI_START + 52)

Definition at line 94 of file irqs-8960.h.

#define SMMU_VPE_CB_SC_SECURE_IRQ   (GIC_SPI_START + 51)

Definition at line 93 of file irqs-8960.h.

#define SPDM_DIAG_IRQ   (GIC_SPI_START + 18)

Definition at line 60 of file irqs-8960.h.

#define SPDM_RT_1_IRQ   (GIC_SPI_START + 17)

Definition at line 59 of file irqs-8960.h.

#define SPS_BAM_DMA_IRQ   (GIC_SPI_START + 105)

Definition at line 147 of file irqs-8960.h.

#define SPS_MTI_0   (GIC_SPI_START + 107)

Definition at line 149 of file irqs-8960.h.

#define SPS_MTI_1   (GIC_SPI_START + 108)

Definition at line 150 of file irqs-8960.h.

#define SPS_MTI_10   (GIC_SPI_START + 117)

Definition at line 159 of file irqs-8960.h.

#define SPS_MTI_11   (GIC_SPI_START + 118)

Definition at line 160 of file irqs-8960.h.

#define SPS_MTI_12   (GIC_SPI_START + 119)

Definition at line 161 of file irqs-8960.h.

#define SPS_MTI_13   (GIC_SPI_START + 120)

Definition at line 162 of file irqs-8960.h.

#define SPS_MTI_14   (GIC_SPI_START + 121)

Definition at line 163 of file irqs-8960.h.

#define SPS_MTI_15   (GIC_SPI_START + 122)

Definition at line 164 of file irqs-8960.h.

#define SPS_MTI_16   (GIC_SPI_START + 123)

Definition at line 165 of file irqs-8960.h.

#define SPS_MTI_17   (GIC_SPI_START + 124)

Definition at line 166 of file irqs-8960.h.

#define SPS_MTI_18   (GIC_SPI_START + 125)

Definition at line 167 of file irqs-8960.h.

#define SPS_MTI_19   (GIC_SPI_START + 126)

Definition at line 168 of file irqs-8960.h.

#define SPS_MTI_2   (GIC_SPI_START + 109)

Definition at line 151 of file irqs-8960.h.

#define SPS_MTI_20   (GIC_SPI_START + 127)

Definition at line 169 of file irqs-8960.h.

#define SPS_MTI_21   (GIC_SPI_START + 128)

Definition at line 170 of file irqs-8960.h.

#define SPS_MTI_22   (GIC_SPI_START + 129)

Definition at line 171 of file irqs-8960.h.

#define SPS_MTI_23   (GIC_SPI_START + 130)

Definition at line 172 of file irqs-8960.h.

#define SPS_MTI_24   (GIC_SPI_START + 131)

Definition at line 173 of file irqs-8960.h.

#define SPS_MTI_25   (GIC_SPI_START + 132)

Definition at line 174 of file irqs-8960.h.

#define SPS_MTI_26   (GIC_SPI_START + 133)

Definition at line 175 of file irqs-8960.h.

#define SPS_MTI_27   (GIC_SPI_START + 134)

Definition at line 176 of file irqs-8960.h.

#define SPS_MTI_28   (GIC_SPI_START + 135)

Definition at line 177 of file irqs-8960.h.

#define SPS_MTI_29   (GIC_SPI_START + 136)

Definition at line 178 of file irqs-8960.h.

#define SPS_MTI_3   (GIC_SPI_START + 110)

Definition at line 152 of file irqs-8960.h.

#define SPS_MTI_30   (GIC_SPI_START + 137)

Definition at line 179 of file irqs-8960.h.

#define SPS_MTI_31   (GIC_SPI_START + 138)

Definition at line 180 of file irqs-8960.h.

#define SPS_MTI_4   (GIC_SPI_START + 111)

Definition at line 153 of file irqs-8960.h.

#define SPS_MTI_5   (GIC_SPI_START + 112)

Definition at line 154 of file irqs-8960.h.

#define SPS_MTI_6   (GIC_SPI_START + 113)

Definition at line 155 of file irqs-8960.h.

#define SPS_MTI_7   (GIC_SPI_START + 114)

Definition at line 156 of file irqs-8960.h.

#define SPS_MTI_8   (GIC_SPI_START + 115)

Definition at line 157 of file irqs-8960.h.

#define SPS_MTI_9   (GIC_SPI_START + 116)

Definition at line 158 of file irqs-8960.h.

#define SPS_SEC_VIOL_IRQ   (GIC_SPI_START + 106)

Definition at line 148 of file irqs-8960.h.

#define SPS_SLIMBUS_BAM_EE0_IRQ   (GIC_SPI_START + 215)

Definition at line 257 of file irqs-8960.h.

#define SPS_SLIMBUS_CORE_EE0_IRQ   (GIC_SPI_START + 214)

Definition at line 256 of file irqs-8960.h.

#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ   (GIC_SPI_START + 30)

Definition at line 72 of file irqs-8960.h.

#define SSBI2_1_SC_CPU0_SECURE_IRQ   (GIC_SPI_START + 29)

Definition at line 71 of file irqs-8960.h.

#define SSBI2_1_SC_CPU1_NON_SECURE_INT   (GIC_SPI_START + 182)

Definition at line 224 of file irqs-8960.h.

#define SSBI2_1_SC_CPU1_SECURE_INT   (GIC_SPI_START + 181)

Definition at line 223 of file irqs-8960.h.

#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ   (GIC_SPI_START + 28)

Definition at line 70 of file irqs-8960.h.

#define SSBI2_2_SC_CPU0_SECURE_IRQ   (GIC_SPI_START + 27)

Definition at line 69 of file irqs-8960.h.

#define SSBI2_2_SC_CPU1_NON_SECURE_INT   (GIC_SPI_START + 180)

Definition at line 222 of file irqs-8960.h.

#define SSBI2_2_SC_CPU1_SECURE_INT   (GIC_SPI_START + 179)

Definition at line 221 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_0   (GIC_SPI_START + 4)

Definition at line 46 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_1   (GIC_SPI_START + 5)

Definition at line 47 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_16   (GIC_SPI_START + 219)

Definition at line 261 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_17   (GIC_SPI_START + 220)

Definition at line 262 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_18   (GIC_SPI_START + 221)

Definition at line 263 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_19   (GIC_SPI_START + 222)

Definition at line 264 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_2   (GIC_SPI_START + 6)

Definition at line 48 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_20   (GIC_SPI_START + 223)

Definition at line 265 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_21   (GIC_SPI_START + 224)

Definition at line 266 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_3   (GIC_SPI_START + 7)

Definition at line 49 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_4   (GIC_SPI_START + 8)

Definition at line 50 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_5   (GIC_SPI_START + 9)

Definition at line 51 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_6   (GIC_SPI_START + 10)

Definition at line 52 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_7   (GIC_SPI_START + 11)

Definition at line 53 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_8   (GIC_SPI_START + 12)

Definition at line 54 of file irqs-8960.h.

#define TLMM_APCC_DIR_CONN_IRQ_9   (GIC_SPI_START + 13)

Definition at line 55 of file irqs-8960.h.

#define TLMM_APCC_SUMMARY_IRQ   (GIC_SPI_START + 16)

Definition at line 58 of file irqs-8960.h.

#define TOP_IMEM_IRQ   (GIC_SPI_START + 91)

Definition at line 133 of file irqs-8960.h.

#define TSENS_UPPER_LOWER_INT   (GIC_SPI_START + 178)

Definition at line 220 of file irqs-8960.h.

#define TSIF1_IRQ   (GIC_SPI_START + 165)

Definition at line 207 of file irqs-8960.h.

#define TSIF2_IRQ   (GIC_SPI_START + 164)

Definition at line 206 of file irqs-8960.h.

#define TSIF_BAM_IRQ   (GIC_SPI_START + 163)

Definition at line 205 of file irqs-8960.h.

#define TSIF_TSPP_IRQ   (GIC_SPI_START + 162)

Definition at line 204 of file irqs-8960.h.

#define TSSC_PENUP_IRQ   (GIC_SPI_START + 145)

Definition at line 187 of file irqs-8960.h.

#define TSSC_SAMPLE_IRQ   (GIC_SPI_START + 144)

Definition at line 186 of file irqs-8960.h.

#define TSSC_SSBI_IRQ   (GIC_SPI_START + 143)

Definition at line 185 of file irqs-8960.h.

#define TV_ENC_IRQ   (GIC_SPI_START + 50)

Definition at line 92 of file irqs-8960.h.

#define USB1_HS_BAM_IRQ   (GIC_SPI_START + 94)

Definition at line 136 of file irqs-8960.h.

#define USB1_HS_IRQ   (GIC_SPI_START + 100)

Definition at line 142 of file irqs-8960.h.

#define USB1_IRQ   (GIC_SPI_START + 142)

Definition at line 184 of file irqs-8960.h.

#define USB2_IRQ   (GIC_SPI_START + 141)

Definition at line 183 of file irqs-8960.h.

#define VCODEC_IRQ   (GIC_SPI_START + 49)

Definition at line 91 of file irqs-8960.h.

#define VFE_IRQ   (GIC_SPI_START + 48)

Definition at line 90 of file irqs-8960.h.

#define VPE_IRQ   (GIC_SPI_START + 47)

Definition at line 89 of file irqs-8960.h.

#define WDT0_ACCSCSSNBARK_INT   (GIC_PPI_START + 4)

Definition at line 29 of file irqs-8960.h.

#define WDT1_ACCSCSSNBARK_INT   (GIC_PPI_START + 5)

Definition at line 30 of file irqs-8960.h.

#define XPU_SUMMARY_IRQ   (GIC_SPI_START + 183)

Definition at line 225 of file irqs-8960.h.