Linux Kernel
3.7.1
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#define IRQ0ENABLE_CSIB_IRQ |
#define IRQ0STATUS_CSIB_IRQ |
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCSI2_CTRL_BURST_SIZE_MASK (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT) |
#define ISPCSI2_CTRL_VP_OUT_CTRL_MASK (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT) |
#define ISPCSI2_CTX_CTRL1_COUNT_MASK (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT) |
#define ISPCSI2_CTX_CTRL2_FORMAT_MASK (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT) |
#define ISPCSI2_CTX_CTRL2_FRAME_MASK (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT) |
#define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT) |
#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT) |
#define ISPCSI2_CTX_CTRL3_ALPHA_MASK (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT) |
#define ISPCSI2_CTX_DAT_OFST_OFST_MASK (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT) |
#define ISPCSI2_CTX_DAT_PING_ADDR | ( | n | ) | ((0x07c) + 0x20 * (n)) |
#define ISPCSI2_CTX_DAT_PONG_ADDR | ( | n | ) | ((0x080) + 0x20 * (n)) |
#define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT) |
#define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT) |
#define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT) |
#define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POL_MASK (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POL_NP (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POL_PN (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POSITION_1 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POSITION_2 (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POSITION_3 (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POSITION_4 (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POSITION_5 (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
#define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
#define ISPCSI2_PHY_CFG_DATA_POL_MASK | ( | n | ) | (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POL_NP | ( | n | ) | (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POL_PN | ( | n | ) | (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_1 | ( | n | ) | (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_2 | ( | n | ) | (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_3 | ( | n | ) | (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_4 | ( | n | ) | (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_5 | ( | n | ) | (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_MASK | ( | n | ) | (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_DATA_POSITION_NC | ( | n | ) | (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)) |
#define ISPCSI2_PHY_CFG_PWR_CMD_MASK (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_CMD_OFF (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_CMD_ON (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_CMD_ULPW (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_STATUS_MASK (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_STATUS_OFF (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_STATUS_ON (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) |
#define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) |
#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK | ( | n | ) | (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n)) |
#define ISPCSIPHY_REG0_THS_SETTLE_MASK (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT) |
#define ISPCSIPHY_REG0_THS_TERM_MASK (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT) |
#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25) |
#define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT) |
#define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN) |
#define ISPCSIPHY_REG1_TCLK_MISS_MASK (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT) |
#define ISPCSIPHY_REG1_TCLK_SETTLE_MASK (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT) |
#define ISPCSIPHY_REG1_TCLK_TERM_MASK (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT) |
#define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT) |
#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT) |
#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT) |
#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT) |
#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT) |
#define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT) |
#define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT) |
#define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) |
#define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT) |
#define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) |
#define ISPHIST_CNT_CLEAR (1 << ISPHIST_CNT_CLEAR_SHIFT) |
#define ISPHIST_PCR_ENABLE (1 << ISPHIST_PCR_ENABLE_SHIFT) |
#define ISPHIST_REG_END_MASK |
#define ISPHIST_REG_MASK |
#define ISPHIST_REG_START_MASK |
#define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4)) |
#define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2) |
#define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3) |
#define ISPRSZ_CNT_HRSZ_MASK (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT) |
#define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT) |
#define ISPRSZ_CNT_VRSZ_MASK (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT) |
#define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT) |
#define ISPRSZ_HFILT_COEF0_MASK (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT) |
#define ISPRSZ_HFILT_COEF1_MASK (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT) |
#define ISPRSZ_IN_SIZE_HORZ_MASK (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT) |
#define ISPRSZ_IN_SIZE_VERT_MASK (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT) |
#define ISPRSZ_IN_START_HORZ_ST_MASK (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT) |
#define ISPRSZ_IN_START_VERT_ST_MASK (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT) |
#define ISPRSZ_OUT_SIZE_HORZ_MASK (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT) |
#define ISPRSZ_OUT_SIZE_VERT_MASK (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT) |
#define ISPRSZ_SDR_INOFF_OFFSET_MASK (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT) |
#define ISPRSZ_SDR_OUTOFF_OFFSET_MASK (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT) |
#define ISPRSZ_VFILT_COEF0_MASK (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT) |
#define ISPRSZ_VFILT_COEF1_MASK (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT) |
#define ISPRSZ_YENH_ALGO_MASK (0x3 << ISPRSZ_YENH_ALGO_SHIFT) |
#define ISPRSZ_YENH_CORE_MASK (0xFF << ISPRSZ_YENH_CORE_SHIFT) |
#define ISPRSZ_YENH_GAIN_MASK (0xF << ISPRSZ_YENH_GAIN_SHIFT) |
#define ISPRSZ_YENH_SLOP_MASK (0xF << ISPRSZ_YENH_SLOP_SHIFT) |
#define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT) |
#define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT) |
#define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT) |
#define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT) |
#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) |
#define OMAP3ISP_CCDC_REG | ( | offset | ) | (OMAP3ISP_CCDC_REG_BASE + (offset)) |
#define OMAP3ISP_CCDC_REG_BASE |
#define OMAP3ISP_CCP2_REG | ( | offset | ) | (OMAP3ISP_CCP2_REG_BASE + (offset)) |
#define OMAP3ISP_CCP2_REG_BASE |
#define OMAP3ISP_CSI2A_REGS1_REG | ( | offset | ) | (OMAP3ISP_CSI2A_REGS1_REG_BASE + (offset)) |
#define OMAP3ISP_CSI2A_REGS1_REG_BASE |
#define OMAP3ISP_CSI2A_REGS2_REG | ( | offset | ) | (OMAP3ISP_CSI2A_REGS2_REG_BASE + (offset)) |
#define OMAP3ISP_CSI2A_REGS2_REG_BASE |
#define OMAP3ISP_CSI2C_REGS1_REG | ( | offset | ) | (OMAP3ISP_CSI2C_REGS1_REG_BASE + (offset)) |
#define OMAP3ISP_CSI2C_REGS1_REG_BASE |
#define OMAP3ISP_CSI2C_REGS2_REG | ( | offset | ) | (OMAP3ISP_CSI2C_REGS2_REG_BASE + (offset)) |
#define OMAP3ISP_CSI2C_REGS2_REG_BASE |
#define OMAP3ISP_CSIPHY1_REG | ( | offset | ) | (OMAP3ISP_CSIPHY1_REG_BASE + (offset)) |
#define OMAP3ISP_CSIPHY1_REG_BASE |
#define OMAP3ISP_CSIPHY2_REG | ( | offset | ) | (OMAP3ISP_CSIPHY2_REG_BASE + (offset)) |
#define OMAP3ISP_CSIPHY2_REG_BASE |
#define OMAP3ISP_H3A_REG | ( | offset | ) | (OMAP3ISP_H3A_REG_BASE + (offset)) |
#define OMAP3ISP_H3A_REG_BASE |
#define OMAP3ISP_HIST_REG | ( | offset | ) | (OMAP3ISP_HIST_REG_BASE + (offset)) |
#define OMAP3ISP_HIST_REG_BASE |
#define OMAP3ISP_PREV_REG | ( | offset | ) | (OMAP3ISP_PREV_REG_BASE + (offset)) |
#define OMAP3ISP_PREV_REG_BASE |
#define OMAP3ISP_REG | ( | offset | ) | (OMAP3ISP_REG_BASE + (offset)) |
#define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE |
#define OMAP3ISP_RESZ_REG | ( | offset | ) | (OMAP3ISP_RESZ_REG_BASE + (offset)) |
#define OMAP3ISP_RESZ_REG_BASE |
#define OMAP3ISP_SBL_REG | ( | offset | ) | (OMAP3ISP_SBL_REG_BASE + (offset)) |
#define OMAP3ISP_SBL_REG_BASE |