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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | ite_dev_params |
| struct | ite_dev |
Macros | |
| #define | ITE_DRIVER_NAME "ite-cir" |
| #define | ite_pr(level, text,...) printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) |
| #define | ite_dbg(text,...) |
| #define | ite_dbg_verbose(text,...) |
| #define | ITE_TX_FIFO_LEN 32 |
| #define | ITE_RX_FIFO_LEN 32 |
| #define | ITE_IRQ_TX_FIFO 1 |
| #define | ITE_IRQ_RX_FIFO 2 |
| #define | ITE_IRQ_RX_FIFO_OVERRUN 4 |
| #define | ITE_BAUDRATE_DIVISOR 1 |
| #define | ITE_LCF_MIN_CARRIER_FREQ 27000 |
| #define | ITE_LCF_MAX_CARRIER_FREQ 58000 |
| #define | ITE_HCF_MIN_CARRIER_FREQ 400000 |
| #define | ITE_HCF_MAX_CARRIER_FREQ 500000 |
| #define | ITE_DEFAULT_CARRIER_FREQ 38000 |
| #define | ITE_IDLE_TIMEOUT 200000000UL |
| #define | ITE_MIN_IDLE_TIMEOUT 100000000UL |
| #define | ITE_MAX_IDLE_TIMEOUT 1000000000UL |
| #define | ITE_BITS_TO_NS(bits, sample_period) ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period)) |
| #define | ITE_RXDCR_PER_10000_STEP 625 |
| #define | ITE_CFQ_400 0x03 |
| #define | ITE_CFQ_450 0x08 |
| #define | ITE_CFQ_480 0x0b |
| #define | ITE_CFQ_500 0x0d |
| #define | ITE_TXMPW_A 0x02 |
| #define | ITE_TXMPW_B 0x03 |
| #define | ITE_TXMPW_C 0x04 |
| #define | ITE_TXMPW_D 0x05 |
| #define | ITE_TXMPW_E 0x06 |
| #define | ITE_RXDCR_DEFAULT 0x01 /* default carrier range */ |
| #define | ITE_RXDCR_MAX 0x07 /* default carrier range */ |
| #define | ITE_TX_PULSE 0x00 |
| #define | ITE_TX_SPACE 0x80 |
| #define | ITE_TX_MAX_RLE 0x80 |
| #define | ITE_TX_RLE_MASK 0x7f |
| #define | IT87_DR 0x00 /* data register */ |
| #define | IT87_IER 0x01 /* interrupt enable register */ |
| #define | IT87_RCR 0x02 /* receiver control register */ |
| #define | IT87_TCR1 0x03 /* transmitter control register 1 */ |
| #define | IT87_TCR2 0x04 /* transmitter control register 2 */ |
| #define | IT87_TSR 0x05 /* transmitter status register */ |
| #define | IT87_RSR 0x06 /* receiver status register */ |
| #define | IT87_BDLR 0x05 /* baud rate divisor low byte register */ |
| #define | IT87_BDHR 0x06 /* baud rate divisor high byte register */ |
| #define | IT87_IIR 0x07 /* interrupt identification register */ |
| #define | IT87_IOREG_LENGTH 0x08 /* length of register file */ |
| #define | IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */ |
| #define | IT87_RDAIE 0x02 /* receiver data available interrupt enable */ |
| #define | IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */ |
| #define | IT87_IEC 0x08 /* interrupt enable control */ |
| #define | IT87_BR 0x10 /* baud rate register enable */ |
| #define | IT87_RESET 0x20 /* reset */ |
| #define | IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */ |
| #define | IT87_RXACT 0x08 /* receiver active */ |
| #define | IT87_RXEND 0x10 /* receiver demodulation enable */ |
| #define | IT87_RXEN 0x20 /* receiver enable */ |
| #define | IT87_HCFS 0x40 /* high-speed carrier frequency select */ |
| #define | IT87_RDWOS 0x80 /* receiver data without sync */ |
| #define | IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */ |
| #define | IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ |
| #define | IT87_TXENDF 0x04 /* transmitter deferral */ |
| #define | IT87_TXRLE 0x08 /* transmitter run length enable */ |
| #define | IT87_FIFOTL 0x30 /* FIFO level threshold mask */ |
| #define | IT87_FIFOTL_DEFAULT |
| #define | IT87_ILE 0x40 /* internal loopback enable */ |
| #define | IT87_FIFOCLR 0x80 /* FIFO clear bit */ |
| #define | IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */ |
| #define | IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ |
| #define | IT87_CFQ 0xf8 /* carrier frequency mask */ |
| #define | IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */ |
| #define | IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */ |
| #define | IT87_RXFBC 0x3f /* receiver FIFO byte count mask */ |
| #define | IT87_RXFTO 0x80 /* receiver FIFO time-out */ |
| #define | IT87_IP 0x01 /* interrupt pending */ |
| #define | IT87_II 0x06 /* interrupt identification mask */ |
| #define | IT87_II_NOINT 0x00 /* no interrupt */ |
| #define | IT87_II_TXLDL 0x02 /* transmitter low data level */ |
| #define | IT87_II_RXDS 0x04 /* receiver data stored */ |
| #define | IT87_II_RXFO 0x06 /* receiver FIFO overrun */ |
| #define | IT85_C0DR 0x00 /* data register */ |
| #define | IT85_C0MSTCR 0x01 /* master control register */ |
| #define | IT85_C0IER 0x02 /* interrupt enable register */ |
| #define | IT85_C0IIR 0x03 /* interrupt identification register */ |
| #define | IT85_C0CFR 0x04 /* carrier frequency register */ |
| #define | IT85_C0RCR 0x05 /* receiver control register */ |
| #define | IT85_C0TCR 0x06 /* transmitter control register */ |
| #define | IT85_C0SCK 0x07 /* slow clock control register */ |
| #define | IT85_C0BDLR 0x08 /* baud rate divisor low byte register */ |
| #define | IT85_C0BDHR 0x09 /* baud rate divisor high byte register */ |
| #define | IT85_C0TFSR 0x0a /* transmitter FIFO status register */ |
| #define | IT85_C0RFSR 0x0b /* receiver FIFO status register */ |
| #define | IT85_C0WCL 0x0d /* wakeup code length register */ |
| #define | IT85_C0WCR 0x0e /* wakeup code read/write register */ |
| #define | IT85_C0WPS 0x0f /* wakeup power control/status register */ |
| #define | IT85_IOREG_LENGTH 0x10 /* length of register file */ |
| #define | IT85_RESET 0x01 /* reset */ |
| #define | IT85_FIFOCLR 0x02 /* FIFO clear bit */ |
| #define | IT85_FIFOTL 0x0c /* FIFO level threshold mask */ |
| #define | IT85_FIFOTL_DEFAULT |
| #define | IT85_ILE 0x10 /* internal loopback enable */ |
| #define | IT85_ILSEL 0x20 /* internal loopback select */ |
| #define | IT85_TLDLIE 0x01 /* TX low data level interrupt enable */ |
| #define | IT85_RDAIE 0x02 /* RX data available interrupt enable */ |
| #define | IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */ |
| #define | IT85_IEC 0x80 /* interrupt enable function control */ |
| #define | IT85_TLDLI 0x01 /* transmitter low data level interrupt */ |
| #define | IT85_RDAI 0x02 /* receiver data available interrupt */ |
| #define | IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */ |
| #define | IT85_NIP 0x80 /* no interrupt pending */ |
| #define | IT85_CFQ 0x1f /* carrier frequency mask */ |
| #define | IT85_HCFS 0x20 /* high speed carrier frequency select */ |
| #define | IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */ |
| #define | IT85_RXACT 0x08 /* receiver active */ |
| #define | IT85_RXEND 0x10 /* receiver demodulation enable */ |
| #define | IT85_RDWOS 0x20 /* receiver data without sync */ |
| #define | IT85_RXEN 0x80 /* receiver enable */ |
| #define | IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */ |
| #define | IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ |
| #define | IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */ |
| #define | IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ |
| #define | IT85_TXENDF 0x20 /* transmitter deferral */ |
| #define | IT85_TXRLE 0x40 /* transmitter run length enable */ |
| #define | IT85_SCKS 0x01 /* slow clock select */ |
| #define | IT85_TXDCKG 0x02 /* TXD clock gating */ |
| #define | IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */ |
| #define | IT85_DLLTE 0x08 /* DLL test enable */ |
| #define | IT85_BRCM 0x70 /* baud rate count mode */ |
| #define | IT85_DLLOCK 0x80 /* DLL lock */ |
| #define | IT85_TXFBC 0x3f /* transmitter FIFO count mask */ |
| #define | IT85_RXFBC 0x3f /* receiver FIFO count mask */ |
| #define | IT85_RXFTO 0x80 /* receiver FIFO time-out */ |
| #define | IT85_WCL 0x3f /* wakeup code length mask */ |
| #define | IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */ |
| #define | IT85_CIRPOIS 0x02 /* power on/off interrupt status */ |
| #define | IT85_CIRPOII 0x04 /* power on/off interrupt identification */ |
| #define | IT85_RCRST 0x10 /* wakeup code reading counter reset bit */ |
| #define | IT85_WCRST 0x20 /* wakeup code writing counter reset bit */ |
| #define | IT8708_BANKSEL 0x07 /* bank select register */ |
| #define | IT8708_HRAE 0x80 /* high registers access enable */ |
| #define | IT8708_C0DR 0x00 /* data register */ |
| #define | IT8708_C0MSTCR 0x01 /* master control register */ |
| #define | IT8708_C0IER 0x02 /* interrupt enable register */ |
| #define | IT8708_C0IIR 0x03 /* interrupt identification register */ |
| #define | IT8708_C0RFSR 0x04 /* receiver FIFO status register */ |
| #define | IT8708_C0RCR 0x05 /* receiver control register */ |
| #define | IT8708_C0TFSR 0x06 /* transmitter FIFO status register */ |
| #define | IT8708_C0TCR 0x07 /* transmitter control register */ |
| #define | IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */ |
| #define | IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */ |
| #define | IT8708_C0CFR 0x04 /* carrier frequency register */ |
| #define | IT8708_C0SCK 0x03 /* slow clock control register */ |
| #define | IT8708_C0WCL 0x05 /* wakeup code length register */ |
| #define | IT8708_C0WCR 0x06 /* wakeup code read/write register */ |
| #define | IT8708_C0WPS 0x07 /* wakeup power control/status register */ |
| #define | IT8708_IOREG_LENGTH 0x08 /* length of register file */ |
| #define | IT8708_CSCRR 0x00 |
| #define | IT8708_CGPINTR 0x01 |
| #define | IT8708_CSCRR_SCRB 0x3f |
| #define | IT8708_CSCRR_PM 0x80 |
| #define | IT8708_CGPINT 0x01 |
| #define | IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */ |
| #define | IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */ |
| #define | IT8709_IOREG_LENGTH 0x02 /* length of register file */ |
| #define | IT8709_MODE 0x1a /* request/ack byte */ |
| #define | IT8709_REG_IDX 0x1b /* index of the CIR register to access */ |
| #define | IT8709_REG_VAL 0x1c /* value read/to be written */ |
| #define | IT8709_IIR 0x1e /* interrupt identification register */ |
| #define | IT8709_RFSR 0x1f /* receiver FIFO status register */ |
| #define | IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */ |
| #define | IT8709_IDLE 0x00 |
| #define | IT8709_WRITE 0x01 |
| #define | IT8709_READ 0x02 |
| #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */ |
| #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */ |
| #define IT85_C0IIR 0x03 /* interrupt identification register */ |
| #define IT85_C0RFSR 0x0b /* receiver FIFO status register */ |
| #define IT85_C0TCR 0x06 /* transmitter control register */ |
| #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */ |
| #define IT85_C0WCR 0x0e /* wakeup code read/write register */ |
| #define IT85_C0WPS 0x0f /* wakeup power control/status register */ |
| #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */ |
| #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */ |
| #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */ |
| #define IT85_FIFOTL_DEFAULT |
| #define IT85_HCFS 0x20 /* high speed carrier frequency select */ |
| #define IT85_IEC 0x80 /* interrupt enable function control */ |
| #define IT85_IOREG_LENGTH 0x10 /* length of register file */ |
| #define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */ |
| #define IT85_RDAI 0x02 /* receiver data available interrupt */ |
| #define IT85_RDAIE 0x02 /* RX data available interrupt enable */ |
| #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */ |
| #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */ |
| #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */ |
| #define IT85_RXEND 0x10 /* receiver demodulation enable */ |
| #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */ |
| #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */ |
| #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */ |
| #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ |
| #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */ |
| #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ |
| #define IT85_TXRLE 0x40 /* transmitter run length enable */ |
| #define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */ |
| #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */ |
| #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */ |
| #define IT8708_C0CFR 0x04 /* carrier frequency register */ |
| #define IT8708_C0IIR 0x03 /* interrupt identification register */ |
| #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */ |
| #define IT8708_C0SCK 0x03 /* slow clock control register */ |
| #define IT8708_C0TCR 0x07 /* transmitter control register */ |
| #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */ |
| #define IT8708_C0WCL 0x05 /* wakeup code length register */ |
| #define IT8708_C0WCR 0x06 /* wakeup code read/write register */ |
| #define IT8708_C0WPS 0x07 /* wakeup power control/status register */ |
| #define IT8708_HRAE 0x80 /* high registers access enable */ |
| #define IT8708_IOREG_LENGTH 0x08 /* length of register file */ |
| #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */ |
| #define IT8709_IIR 0x1e /* interrupt identification register */ |
| #define IT8709_IOREG_LENGTH 0x02 /* length of register file */ |
| #define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */ |
| #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */ |
| #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */ |
| #define IT8709_REG_VAL 0x1c /* value read/to be written */ |
| #define IT8709_RFSR 0x1f /* receiver FIFO status register */ |
| #define IT87_BDHR 0x06 /* baud rate divisor high byte register */ |
| #define IT87_BDLR 0x05 /* baud rate divisor low byte register */ |
| #define IT87_FIFOTL_DEFAULT |
| #define IT87_HCFS 0x40 /* high-speed carrier frequency select */ |
| #define IT87_II_TXLDL 0x02 /* transmitter low data level */ |
| #define IT87_IIR 0x07 /* interrupt identification register */ |
| #define IT87_IOREG_LENGTH 0x08 /* length of register file */ |
| #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */ |
| #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */ |
| #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */ |
| #define IT87_RXEND 0x10 /* receiver demodulation enable */ |
| #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */ |
| #define IT87_TCR1 0x03 /* transmitter control register 1 */ |
| #define IT87_TCR2 0x04 /* transmitter control register 2 */ |
| #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */ |
| #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */ |
| #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */ |
| #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ |
| #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */ |
| #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ |
| #define IT87_TXRLE 0x08 /* transmitter run length enable */ |
| #define ITE_BITS_TO_NS | ( | bits, | |
| sample_period | |||
| ) | ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period)) |
| #define ite_dbg | ( | text, | |
| ... | |||
| ) |
| #define ite_dbg_verbose | ( | text, | |
| ... | |||
| ) |
| #define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */ |
1.8.2